Unit 01 Digtal Logic Circuits

1. 2. 3. 4. 5. 6. 7. 8. Introduction Logic Gates Boolean Algebra De-Morgans Theorem and Inverted Gates Karnaugh Map technique Combinational Circuits Adders Sequential Circuits 8.1 R-S Flip-flop 8.2 JK 8.3 D 8.4 T

Prepared by: Tosha Bhatt

1.0 Introduction
The Digital Computer is a. Digital System that uses two-symbol language called binary system, which has two Digits 0 and 1. A. Binary Digit is called a. Bit. The group of binary bits can be used to represent numbers as well as alphabets and special symbols. It is easy to convert concepts into the real electronic circuits if we use binary system instead of our Decimal system. As only two symbols are required to represent binary digit, only two voltage levels are sufficient to deal it in signal form. In Logic we have two alternatives either TRUE or FALSE. Just like this in binary Digital systems we have 0 or 1. Thus it is easy to translate Logical idea into digital signal. All Digital Circuits have power to process arithmetic as well as logical information. The chapter starts with explanation of Boolean algebra and ends with the discussions of various Logic circuits.

2.0 Logic gates

The two state of binary system is 1 and 0. In typical computer 1 is represented by +5 v and 0 is represented by 0 v. The processing and manipulation of binary information is done by Electronic circuit modules, which are known as Logic Gates. There are mainly three basic gates corresponding to AND, OR and Complement operation. Other derived Gates are NAND, NOR and EX-OR as well as EX-NOR. The name, Graphic Symbol and Algebraic function for all with Truth table is shown below.

Name

Graphic symbol

Algebraic function X = A. B or X = AB

Truth table
A B 0 1 0 1 B 0 1 0 1 A 0 1 x 1 0 x 0 0 0 1 x 0 1 1 1

A AND B X

0 0 1 1 A

A OR B X X=A+B

0 0 1 1

Inverter

X = A

Buffer

X=A
A

A 0 1 B 0 1 0 1

x 0 1 x 1 1 1 0

A NAND B X X = (AB)

0 0 1 1

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NOR

A X B

X = (A + B)

A 0 0 1 1

B 0 1 0 1 B 0 1 0 1 B 0 1 0 1

x 1 0 0 0 x 0 1 1 0 x 1 0 0 1

A Exclusive-OR B X

X=AB or X = AB + AB X = (A B) or X = AB + AB

A 0 0 1 1 A 0 0 1 1

A Exclusive-NOR B X

Digital logic gates AND The Output of AND gate is 1 only when both inputs are 1 otherwise 0 OR The Output of Or gate is only 0 when both inputs are 0 otherwise 1 NOT The output of NOT gate is always complementing of input. NAND - NOR The NAND function is the complement of the AND function and NOR is the complement of OR. Both NAND and NOR gates may have more than two inputs, and the output is always the complement of the AND and OR function, respectively. Exclusive-OR When two inputs are unequal output is 1 otherwise 0. Exclusive-NOR Ex-NOR is complement of Ex-OR that is when both inputs are equal output is 1.

3 Boolean Algebra
Boolean algebra is an algebra that deals with binary variables and logic operations. Letters such as A, B, x and y, designates the variables. The three basic logic operations are AND, OR and complement. A Boolean function can be expressed algebraically with binary variables, the logic operation symbols, parentheses and equal sign. For a given value of the variables, the Boolean function can be either 1 or 0. Consider, for example, the Boolean function F = x + yz The function F is equal to 1 if x is 1 or both y and z are equal to 1; F is equal to 0 otherwise. But saying that y = 1 is equivalent to saying that y = 0 since y is the complement of y. therefore, we may say that F is equal to 1 if x = 1 or if yz = 01. The relationship between a function and its binary variables can be represented in a truth table. To represent a function in a truth table we need a list of the 2 combinations of the n binary variables. As shown in the under given figure, there are either possible distinct combinations for assigning bits to the three variables x, y, and z. the function F is equal to 1 for those combinations where x = 1 or yz = 01; it is equal to 0 for all other combinations.
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X 0 0 0 0 1 1 1 1

Y 0 0 1 1 0 0 1 1

Z 0 1 0 1 0 1 0 1

F 0 1 0 0 1 1 1 1

Truth Table

A Boolean function can be transformed from an algebraic expression into a logic diagram composed of AND, or and inverter gates. The logic diagram for F is shown in the under given figure. There is an inverter for input y to generate its complement y. There is an AND gate for the term yz, and an OR gate is used to combine the two terms. In a logic diagram, the variables of the function are taken to be the inputs of the circuit, and the variable symbol of the function is taken as the output of the circuit.
X Y Z Logic Diagram F

The under given table lists the most basic identities of Boolean algebra. All the identities in the table can be proven by means of truth tables. The first eight identities show the basic relationship between a single variable and itself, or in conjunction with the binary constants 1 and 0. The next five identities (9 through 13) are similar to ordinary algebra. Identity 14 does not apply in ordinary algebra but is very useful in manipulating Boolean expressions. Identities 15 and 16 are called DeMorgans theorems and are discussed below. The last identity states that if a variable is complemented twice, one obtains the original value of the variable. (1) (2) (3) (4) (5) (6) (7) (8) x+0=x x. 0 = 0 x+1=1 x. 1 = x x+x=x x. x = x x + x = 1 x. x = 0 (17) (9) x+y=y+x (10) xy = yx (11) x + (y + z) = (x + y) + z (12) x (yz) = (xy) z (13) x (y + z) = xy + xz (14) x + yx = (x + y)(x + z) (15) (x + y) = xy (16) (xy) = x + y (x) = x

Basic Identities of Boolean algebra

The identities listed in the table apply to single variables or to Boolean functions expressed in terms of binary variables. For example, consider the following Boolean algebra expression: AB + CD + AB + CD
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By letting x = AB + CD the expression can be written as x + x. rom identity 5 in the above table, we find that x + x = x. thus the expression can be reduced to only two terms: AB + CD + AB + CD = AB + CD

4 De-Morgans Theorem and Inverted Gates

DeMorgans theorem is very important in dealing with NOR and NAND gates. It states that a NOR gate that performs the (x + y) function is equivalent to the function xy. Similarly, a NAND function can be expressed by either (xy) or (x + y). For this reason the NOR and NAND gates have two distinct graphic symbols, as shown in the under given two figure. Instead of representing a NOR gate with an OR graphic symbol followed by a circle, we can represent it by an AND graphic symbol proceeded by circles in all inputs. The invert AND symbol for the NOR gate follows from DeMorgans theorem and from the convention that small circles denoted complementation. Similarly, the NAND gate has two distinct symbols, as in the under given figure.

x y Z OR invert x y Z

x (x + y + z) y z

xyz=(x + y + z) Invert AND

(xyz) AND Invert

x y z

x + y + z= (xyz) Invert OR

5 Karnaugh Map Technique:

Simplification of Algebraic equation is an important activity. If algebraic equation is not simplified (minimized) it will require more gates to implement the equation. For example if we have F= (xy + xy) z. We want to implement it using gates. How many Gate it will require? Naturally five gates. Three AND, one OR and one NOT. It can be implemented as shown below. X F Y

Z Let try to simplify same equation first.

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Take x common F= x (y+y) z We know y+y =1 Thus F=x z. Now our simplified equation is too small and can be implemented by a. single AND Gate .Wow!!!!!!!!!! Its wonderful. Doesnt it?

X F Z

The example shown above depicts the advantage of Boolean function simplification. Some simple Boolean function can be simplified mathematically by using rules of Boolean algebra. To simplify complex Boolean equations there is one technique developed by mathematician Karnaugh that is known as Karnaugh-Map technique. Under this technique for n variable, the possible square in K-map will be 2 to power n. Thus for 3 variables number of square should eight. Each square represents the minterm. The 2, 3 and 4variable map looks like below. 2-Variable K-map Y y y X X X

3-Varible K-map

yz x x

yz

yz

yz

4-Variable K-map zw xy xy zw zw zw

xy xy
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Boolean expression reduction Procedure: Assume first that we have one Boolean expression to reduce , which is not expanded . Step-1 Expand the Boolean expression, meaning if F=xy+x Let F=xy+x.1 =xy+x (y+y) (Because y+y=1) =xy+xy+xy Step-2 Find out how many variables are there Step-3 Draw the corresponding n-var map Step-4 Write down 1 in those squares , which correspond to minterms in your expanded equation . Step-5 Now form groups of 1,s . It may be pair , quad , or octal etc . If it is not possible to make such group , let it remain individual . Step-6 writes down reduced term for the area covered by these groups. Step-7 Combine all these reduced terms with operator OR(+) .

EXAMPLES : 1. Reduce F=xy+xy+xy Here n=2 therefor 4 squares should be there Draw 2-var K-map with 4 squares

Y X X 1 1

y 1

Two pairs are possible as shown above . The reduced terms are x for horizontal pair and y for vertical pair . Combining them with + operator F= x+ y

Example 2 Reduce F= xyz + xyz + xyz + xyz N=3 Thus 8 Squares Draw 3-variable K-map
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Put 1 for 4 minterms of expression

Yz X 1

yz 1 1

yz 1 1

yz

In above K-map one quad and two pairs are possible . Reduced ter for quad is z Reduced term for pairs are xy and xy Thus F= xy+ xy + z DONT care Conditions : If the minterm in the Boolean equation is changed , the function output will change . But some minterms are such that they dont affect the output F . Whether you put 1 or 0 in the corresponding minterm square , it will not affect the F . Such type of minterms is known as dont care conditions . They are denoted by X mark in K-map. Universal Gates: UNIVERSAL NAND GATE: The NAND Gate is universal gate because any digital system can be implemented with it. With the help of NAND gate we can do operation of NOT gate ,OR gate, and AND gate.
A A+B

Figure shows the operation of OR gate with the connection of Three NAND gate .

Universal NOR GATE: The NOR gate is Universal because any Boolean function can be implemented with it. The conversion of AND, OR,NOT gate to NOR is shown in figure. The not operation is obtain from a one input NOR gate. It is another symbol for an inverter circuit the or operation requires to NOR gate. They first produce the inverter OR and the second act as a normal output for OR operation. The AND operation is achieved through a Nor gate with additional inverter at each input.

6 Combination Circuits
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A combination circuit is a connected arrangement of logic gates with a set of input and outputs. Definition : The Circuit is called combinational if at any given time, the binary values of the outputs are a function of the binary combination of the inputs. A block diagram of a combination circuits is shown in the under given figure. The n binary input variables come from an external source, the m binary output variables go to an external destination, and in between there is an interconnection of logic gates. A combination circuit transforms binary information from the given input data to the required output data. Combination circuits are employed in digital computers for generating binary control decisions and for providing digital components required for data processing. A combination circuit can be described by a truth table showing the binary relationship between the n input variables and the m output variables. The truth table lists the corresponding output binary values for each of the 2n input combinations. A combination circuit can also be specified with m Boolean functions, one for each output variable. Each output function is expressed in terms of the n input variables. n input variable Combination circuit m output variables

Block diagram of a combination circuit Analysis: The analysis of a combination circuit starts with a given logic circuit diagram and culminates with a set of Boolean functions or a truth table. 1. Design: The design of combination circuits starts from the verbal outline of the problem and ends in a logic circuit diagram. The demonstrate the design of combination circuits, we present two examples of simple arithmetic circuits. These circuits serve as basic building blocks for the construction of more complicated arithmetic. The examples of combinational circuits are Decoder , Encoder , Multiplexer , and Demultiplexer etc.

7 ADDERS Half-Adder The most basic digital arithmetic circuit is the addition of two binary digits. A combination circuit that performs the arithmetic addition of two bits is called a half-adder. One that performs the addition of three bits (two significant bits and a previous carry) is called a full-adder. The name of the former stems from the fact that two half-adders are needed to implement a full-adder. The input variables of a half-adder are called the augends and addend bits. The output variables the sum and carry. It is necessary to specify two output variables because the sum of 1 + 1 is binary 10, which has two digits. We assign symbols x and y to the two input variables, and S (for sum) and C (for carry) to the two output variables. The truth table for the half-adder is shown in the under given figure. The C output is 0 unless both inputs are 1. The S output represents the least significant bit of the sum. The Boolean functions for the two outputs can be obtained directly from the truth table:
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S = xy + xy = x y C = xy The logic diagram is shown in the under given figure. It consists of an exclusive-OR gate and an AND gate. x 0 0 1 1 y 0 1 0 1 C 0 0 0 1 S 0 1 1 0 X Y
S

C Logical diagram Half-adder

Truth Table

Full-adder A full adder is a combination circuit that forms the arithmetic sum of three input bits. It consists of three inputs and two outputs. Two of the input variables, denoted by x and y, represent the two significant bits to be added. The third input, z, represents the carry from the previous lower significant position. Two outputs are necessary because the arithmetic sum of three binary positions. Two outputs are necessary because the arithmetic sum of three binary digits ranges in value from 0 to 3, and binary 2 or 3 needs two digits. The two outputs are designated by the symbols S (for sum) and C (for carry). The binary variable S gives the value of the least significant bit of the sum. The binary variable C gives the output carry. The truth table of the full-adder is shown in the under given figure. The eight rows under the input variables designate all possible variables are determined from the arithmetic sum of the input bits. When all input bits are 0, the output is 0. The S output is equal to 1 when only one input is equal to 1 or when all three inputs are equal to 1. The C output has a carry of 1 if two or three inputs are equal to 1.

x 0 0 0 0 1 1 1 1

Inputs y 0 0 1 1 0 0 1 1

z 0 1 0 1 0 1 0 1

Outputs C S 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1

The maps in under given figure are used to find algebraic expressions for the two output variables. The 1s in the squares for the maps of S and C are determined directly from the minterms in the
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truth table. The squares with 1s for the S output do not combine in-groups of adjacent squares. But since the output is 1 when an odd number of inputs are 1, S is an odd function and represents the exclusive-OR relation of the variables. The squares with 1s for the C output may be combined in a variety of ways. One possible expression for C is C = xy + (xy + xy)z Realizing that xy + xy = x y and including the expression for output S, we obtain the two Boolean expressions for the full-adder; S=xyz C = xy + yz + zx y 1
X

y 1 1 x 1 z 1 1

1 z

Maps for Full-adder The logic diagram of the full-adder is drawn in the under given figure. Note that the full adder circuit consists of two half-adders and an OR gate. When used in subsequent chapters, the full-adder (FA) will be designated by a block diagram as also shown in the under given figure.

x y

carry

Logic Diagram x y z Block Diagram

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FA

FA C

8 Sequential Circuits
When Output of any circuit at any moment is dependent of Inputs as well as outputs at previous moment than it is known as Sequential Circuit . It always incorporates feedback in the circuit .A sequential circuit is an interconnection of flip-flops and gates. The gates by themselves constitute a combination circuit, but when included with the flip-flops, the overall circuit is classified as a sequential circuit. The block diagram of a clocked sequential circuit is shown in the under given figure. It consists of a combination circuit and a number of clocked flipflops. In general, any number or type of flip-flops may be included. As shown in the diagram, the combination circuit block receives binary signals from external inputs and from the outputs of flipflops. The outputs of the combination circuit go to external outputs and to input of flip-flops. The gates in the combination circuit determine the binary value to be stored in the flip-flops after each clock transition. The outputs of flip-flops, in turn, are applied to the combination circuit inputs and determine the circuits behavior. This process demonstrates that the external outputs of a sequential circuit are functions of both external inputs and the present state of the flip-flops. Moreover, the next state of flip-flops is also a function of their present state and external inputs. Thus a sequential circuit is specified by a time sequence of external inputs, external outputs, and internal flip-flop binary states.

Input Combination Circuits Flip-flops

Output

Clock Feedback Block diagram of a clocked synchronous sequential circuit

8.1 RS Flip-Flops The flip-flop is a circuit , which has basically two states . SET state and RESET state . One can change the state of flip-flop by applying giving some inputs to it. R-S flip-flop is the simplest flip-flop with indefinite state .

R Q

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Q 12

S 1 0 0 0

R 0 0 1 0

Q 1 1 0 0

Q 0 0 1 1

That means when input are 00 there is no change in the output state , it remains same as the previous state . When SR=10 than Q=1 which is SET state . When SR=01 than Q=0 which is RESET state .

Clock pulse: A clock signal is a signal used to coordinate the actions of two or more circuits. A clock signal oscillates between a high and low state, normally with a 50% duty cycle, and it is usually in the form of a square wave. Circuits using the clock signal for synchronization may become active at the rising edge, falling edge, or both edges of the clock cycle. CLOCKED RS FLIP-FLOP When one clock signal is combined with the Inputs than it is known as Clocked RS flipflop. It is connected in such a way that Inputs are applied to FF only when clock is present. Circuit is drawn below .

R Q

CLOCK

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TRUTH TABLE S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q(t+1) s RQ 00 0 01 11 1 10

0 1 0 0 1 1 not defined not define

1 pair and 1 Quad in K-map

Thus one can write equation 8.2 J-K Flip Flop

Q(t+1) = S + RQ

One of the great disadvantages of Clocked RS Flip-flop is that it has two un-defined states . Thus it has limited application. To avoid this un-defined state the concept of J-K flip-flop is brought. It is known that the output states Q and Q are never equal as they are complement of each other . Thus if we employ feedback from output to input at the AND gate both the inputs never be equal , which in turn avoid the un-defined(SR=11) state .

S
SR FLIPFLOP

R
K

CIRCUIT OF J-K FLIP-FLOP The truth table of J-K flip flop is same as RS flip-flop , only difference is that as both Inputs can never be equal at point S and R in the circuit , the 11 state is avoided . When previous Q=1 and afterwards if 11 appears at input S will be 1 and R will be 0 . Thus we can say that due to feedback 11 at Inputs is converted to 10 at input provided previous Q is 1 . same way if previous Q = 0 and 11 appears at input 11 is converted to 01 at points s and R . Our new Truth -table for J-K is as shown below .
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J 0 0 0 0 1 1 1 1

K 0 0 1 1 0 0 1 1

Q 0 1 0 1 0 1 0 1

Q(t+1) J 0 1 0 0 1 1 1 0 Q

CP K KQ J 0 00 01 1 11 10 Q

Thus from two pairs of K-map we can write Equation for next state Q(t+1) = JQ + KQ 8.3 D FLIP-FLOP J-K Flip-Flop can be converted in the D- flip-flop by simply connecting both J and inverted K . That means Inverted K is tied with J and applied as single Input as shown in circuit below .

CP K

JK
Q Q

D 0 0 1 1

Q 0 1 0 1

Q(t+1) 0 0 1 1

0 0 1

From the K-map we can see that there is one pair possible .hence the equation will be Q(t+1) = D

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8.4 T FLIP FLOP T flip-flop is same as J-K flip-flop except that both J and k are directly tied together . So that only that input combinations of J-K flip flop are required to be considered for which both J and k inputs are equal . T J Q

J K
K T - FLIP FLOP T 0 0 1 1 Q 0 1 0 1 Q(t+1) 0 1 1 0

In T flip-flop Q(t+1) = TQ + TQ as O/p is Ex-OR of Inputs

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