A Partially-Exhaustive Gate Transition Fault Model

Brion Keller, Dale Meehl, Anis Uzzaman

Cadence Design Systems Endicott, NY, USA { Kellerbl, Meehl, Uzzaman }@cadence.com
AbstractThis paper shows a way to define a partiallyexhaustive gate transition fault model for use in catching defects that escape when using more traditional fault models. We define the gate-level transitions ATPG must create for this fault model and how this may catch un-modeled defects. Future work will analyze results of applying tests generated using this fault model against a commercial chip design. Keywords-delay defect modeling, transition delay fault model.

Richard Billings
Advanced Micro Devices Austin, TX, USA { Richard.billings } @amd.com inverter, so this defect would cause the input of the inverter to be stuck at ground, or 0, and the output to be stuck at 1. These abstract models are called faults, and the set of such behaviors being tested for are called a Fault Model. The most commonly used fault model is the Stuck-At model. Based on many years of use, it does a very good job of detecting defects that cause static (non time-varying) incorrect behavior. This would include hard shorts and opens in the various metal traces, for instance. In recent years, newer technologies have been exhibiting time-varying behavior due to defects, and these behaviors are emulated by the Transition Fault model [2], in which a pin is too slow during a state transition. This will occur when a short or open is resistive rather than hard, for instance. Figure 2, highlights how a time sensitive defect requires a capture before it stabilizes by the time traditional stuck-at test speeds captures occur. Fault models normally denote the local behavior of a defect and point out what is required to excite the defect; however, detecting such defects requires a combination of exciting the defect and propagation of its effect to an observation point. Note that the transition fault model is modeling a local defect and that observation of delay defects may require excitation and propagation along paths that allow detection of small delays something that is built into a path-delay fault model [2].

I.

INTRODUCTION

To understand the purpose of a fault model, it is useful to know how defects are manifested. Errors, glitches, or accidents in the manufacturing process can produce defects that may cause a chip to not behave exactly the way it was intended. Defects in the silicon are presumed to cause incorrect behavior, later if not immediately, and therefore must be identified so the circuit can be rejected.

Figure 1. Shorting and Detached Substrate defects. Photos courtesy of IBM. For example, in Figure 1, the left picture shows there is some extra metal shorting two metallic traces. In the right picture, a metal trace has become detached from the substrate and buckled, most likely during a chemical mechanical polishing process step. If the buckled trace is not touching the other trace, there may be no functional error, but do you want to ship it? Later, real world vibration may cause it to either short to its neighbor, or break off and create an open. While we would like to directly test for each and every possible defect, there is in fact no way to directly observe all of them; instead, we observe their failure effects on circuit operation, and categorize those behaviors. It is impossible to know all possible silicon defects that might occur during the manufacturing process [1]. It is possible to abstract particular failure behaviors that are commonly found in the manufacturing process. An example would be a short between a transistor gate metal to the power supply Ground. The transistor gates are the input of the

Figure 2. Time Sensitive Transition Defects. The stuck-at and transition fault model do a very good job to help test and identify single failures found in silicon, but sometimes the defects are more complex and conditional in nature. These complex behaviors might involve multiple nets being required to be at certain values in-order for the defect to become excited (activated). The stuck-at and transition fault models need help to understand and use these interactions to accurately test for and identify defects that do not match the behavior of those fault models.

Pattern faults [12] are a fault modeling technique unique to Cadences Encounter Test product. Pattern Faults allow the tool to model defects that are not well modeled by the traditional stuck at or transition fault model. For instance, a bridging fault between two nets may be modeled by specifying required values on those nets (or at the output pins of the gates that source the nets), and expected good and faulty values that result on the affected net. Fault Tuples [13] are a more general extension to Pattern Faults. This is a very powerful and general capability that allows fault excitation conditions to be described in a way that test patterns can then be generated. It is used to generate patterns for path delay, bridging defects, cross-talk, and diagnostic fault-isolation. Pattern faults have also been used to generate gateexhaustive (static) fault models [3]. Gate exhaustive faults are used to help guide ATPG to create test sets in which all possible gate input states are applied and observed [3-7]. These give higher defect coverage and it is natural to wonder if a gate-exhaustive transition fault model would also improve defect detection. II. GATE-EXHAUSTIVE TRANSITION FAULTS Gate exhaustive faults can be defined for any primitive with more than one input. Examples of the fault sets for MUX and XOR cells are shown in Figure 3 and Figure 4. For the MUX gate, four input combinations are needed to test all the faults in a traditional stuck-at fault model. With a gate exhaustive fault model, it doubles the amount of input combinations required by exercising all possible input combinations. The input combinations ensure that the data pins are held at the same and different values for each select state. This helps detect an internal or external bridge or pass gate failure if present during testing. Once the faults are modeled, they are defined as gate exhaustive pattern faults. During the initialization process for ATPG, the gate exhaustive pattern faults will be instantiated for each instance for the particular cell it was defined for.

input nodes of the structure and propagating the resulting values at the output nodes to observation points. Gate exhaustive static fault models have been shown more effective in detecting defective chips over the standard stuck-at fault and n-detect fault models [3]. Could the same concept of applying gate exhaustive static faults be applied to the gate transition fault model? For a gate exhaustive transition fault model, lets examine what this would mean. 3 Input AND Gate (3 Input, 1 Output)
Transition Pin Fault Model (Input Combinations) Initial Transition Gate Exhaustive Transition Fault Model (Input Combinations) Initial Transition
001, 111 100, 001, 011 100, 001, 101 100, 001, 110 100, 110, 001 100, 110, 100 001, 110, 010 001, 110, 000 001,

1xx 011, x1x 101, x0x 111, xx0 111, xx1 110, 0xx 111

111 011, 111 101, 111 110, 111 111 010, 111 000, 011 111, 011 101, 011 110, 011 011 010, 011 000, 101 111, 101 011, 101 110, 101 101 010, 101 000, 110 111, 110 011, 110 101, 110 110 010, 110 000, 001 111, 001 011, 001 101, 001 001 010, 001 000, 100 111, 100 011, 100 101, 100 100 010, 100 000, 010 111, 010 011, 010 101, 010 010 100, 110 000, 000 111, 000 011, 000 101, 000 000 001, 000 010

Figure 5. 3-input AND Transition Gate Exhaustive Model. Looking at a standard 3-input AND gate (Figure 5), a total of six tests are needed to test the standard transition fault model. In a fully gate exhaustive transition fault model, the number of required tests increases to 56 tests (8 possible starting states times 7 possible different ending states). The additional tests exercise multiple pins switching at the same time to help excite potential internal bridge, cross talk, or pin dependant defects. These include gates slow to rise when certain inputs pairs are changed, slow to fall on a certain pin when other pins stay 1, slow to rise output faults when certain input pins change, and slow to fall on all inputs. III. PARTIALLY-EXHAUSTIVE TRANSITION FAULTS Although there is benefit to applying more and different tests to excite static defects and propagate their effects to observe points as shown in [3] and [9], it can be prohibitively expensive to go after a fully gate-exhaustive transition fault model. The most basic approach for a gate-exhaustive transition fault model would pair each of 2n input starting states with all 2n - 1 possible different end states on the inputs of each n-input gate. This defines 2n(2 n -1) possible input pin transition state combinations to represent faults. For a 2input gate, there would be 12 faults, which isnt too onerous. A 3-input gate would have 56 faults and a 4-input gate would have 240 faults, so it is obvious this can get very expensive. Rather than pursue a fully gate-exhaustive transition fault model, we propose a somewhat reduced set of faults that we call a partially-exhaustive gate transition fault model. This reduced set of faults attempts to cover the more interesting subset of the fully exhaustive set. The number of faults per gate for various fault models is shown in Table 1.

Figure 3. MUX Gate Exhaustive Fault Model.

Figure 4. XOR Gate Exhaustive Fault Model. During ATPG, required stimuli and expected responses are defined in terms of static values or transitions on the pins of the logic to be tested. When a pattern fault is selected by ATPG, the test pattern generator sensitizes the fault by justifying the required values and transitions to the

Table 1. Faults per gate for different fault models.

Fault Model Single Stuck Fault Transition Fault Gate Exhaustive - static Gate Exhaustive transition Partial Gate Exhaustive transition Enhanced Partial Gate Exhaustive transition
n

# faults for ninput gate 2(n+1) 2(n+1) 2

n n

n=2 6 6 4 12 7 8

n=3 8 8 8 56 19 26

n=4 10 10 16 240 47 80

2 (2 1) 2n 1 + n(2n-1) 2n 1 + CT

primarily because it forces inputs ending in the controlling value to go through a transition and limits to just a single input being at the controlling value in the ending state. The enhanced partially exhaustive gate transition fault model allows any and all inputs to be at the controlling value at the ending state as long as they all go through a transition to get there. An enhanced partially exhaustive gate transition fault model for a 3-input AND gate would include the faults from Table 2, Table 3 and Table 4 a total of 26 faults. Table 3. Partially-exhaustive input pin transition to controlling values for 3-input AND gate.
Start 100 101 110 End 011 011 011 Out Transition 00/1 00/1 00/1 Comment Input 1 slow to fall when other inputs rise Input 1 slow to fall when input 2 rises Input 1 slow to fall when input 3 rises

The partially-exhaustive gate transition fault model includes the exhaustive set of starting states with at least one controlling value on the inputs and the ending state of all non-controlling values for gates that have controlling values. An example for a 3-input AND gate is shown in Table 2. The partially-exhaustive gate transition fault model also includes all possible input starting states for other inputs when a single input transitions to the controlling value for the gate. An example of this set for a 3-input AND gate is shown in Table 3. These two sets of faults provide a reasonable subset of the fully exhaustive transition set for a gate. If desired, additional faults can be added to the second set for faults with inputs transitioning to the controlling value. By adding faults that have two or more inputs transitioning to the controlling value, you get a more complete set, but at the expense of having substantially more faults in the model. The equation shown in Table 1 for the number of faults per gate in the partially exhaustive plus model uses CT, the number of controlling transition faults, computed using:

111

011

10/1

Input 1 slow to fall when other inputs are stable Input 2 slow to fall when other inputs rise

010

101

00/1

011

101

00/1

Input 2 slow to fall when input 1 rises

110

101

00/1

Input 2 slow to fall when input 3 rises

111

101

10/1

Input 2 slow to fall when other inputs are stable Input 3 slow to fall when other inputs rise

001

110

00/1

011

110

00/1

Input 3 slow to fall when input 1 rises

101

110

00/1

Input 3 slow to fall when input 2 rises

CT = (
i =1

n! )(2 ni ) i!(n i )!

(1)

111

110

10/1

Input 3 slow to fall when other inputs are stable

Only the first term (i=1) of the summation for CT is used for the non-enhanced partially exhaustive model. Table 2. Exhaustive transitions for 3-input AND gate ending in 111.
Start 000 001 010 011 100 101 110 End 111 111 111 111 111 111 111 Out Transition 01/0 01/0 01/0 01/0 01/0 01/0 01/0 Comment Any input or gate slow to rise when all inputs change Gate slow to rise when first 2 inputs change Gate slow to rise when first and last inputs change Gate slow to rise when first input changes Gate slow to rise when last 2 inputs change Gate slow to rise when middle inputs changes Gate slow to rise when last input changes

Table 4. Enhanced partially-exhaustive gate transition faults for 3-input AND gate.
Start 011 111 101 111 110 111 111 End 100 100 010 010 001 001 000 Out Transition 00/1 10/1 00/1 10/1 00/1 10/1 10/1 Comment Inputs 2 & 3 slow to fall when input 1 rises Inputs 2 & 3 slow to fall when input 1 is stable Inputs 1 & 3 slow to fall when input 2 rises Inputs 1 & 3 slow to fall when input 2 is stable Inputs 1 & 2 slow to fall when input 3 rises Inputs 1 & 2 slow to fall when input 3 is stable All inputs slow to fall

IV.

EXPERIMENTAL RESULTS

The number of faults for the partially-exhaustive transition fault model is less than the fully exhaustive

We implemented the partially exhaustive gate transition fault model using the Pattern Fault capability of the Cadence Encounter Test product [11]. This fault modeling mechanism

allows defining faults for any unique module within the hierarchy of the design, so we define the faults just for each unique sized gate in the circuit (or for each library cell). Although we will provide analysis of results of applying tests that target the partially-exhaustive transition fault model against a commercial chip, at this time we have only ATPG and simulation data available. The data show that fault counts go up substantially and run times for ATPG go up a bit more than proportional to fault counts on each design.

V.

SUMMARY AND CONCLUSIONS

Figure 6. Test case design sizes and fault counts The data collected below are from 6 designs. The design sizes are summarized in Figure 6. The gate exhaustive test (GET) fault counts on average where 1.3x-1.6x larger than the standard transition fault model. This represents at least a doubling of the faults for ATPG and simulation. There was one exception: Chip D. For this particular design the number of gate exhaustive transition faults was less than the standard pin fault counts because a small number of primitive gates had more than two inputs. Examining the ATPG performance and pattern counts (Figure 7), the increased fault count does drive the ATPG CPU time to double in most cases. Many GET transitions may be unobservable, leading to longer run time. The pattern count also doubles in most cases as the gate exhaustive faults drive more explicit pin values to be obtained. The gate exhaustive ATPG patterns achieved slightly higher transition pin fault coverage. This might be attributed to the application of a higher number of test patterns achieving serendipitous mark-off [8]. On average, gate exhaustive transition ATPG patterns achieved 10% higher test coverage than the pin fault model ATPG against the gate exhaustive transition fault model. This represents a large transition fault population that is not tested with todays standard test techniques.

We showed how to use Pattern Faults to model partiallyexhaustive gate-level transition fault sets. Although there is significant expense to target such fault sets, it is similar to an n-detect transition test set for n>10. Reducing test escapes can be an expensive endeavor, but this approach ensures the tests do create unique local excitation criteria for each fault. The expense of partially-exhaustive gate transition fault model can be lowered somewhat by restricting gates to 4 or fewer inputs, breaking larger gates into several smaller gates that are equivalent. This can also be done virtually by having exhaustive pattern faults be done in groups of input pins on a large gate requiring those inputs not in the group to be at a non-controlling value in the ending state only. The static and transition gate-exhaustive fault mechanism can be extended to library cells and macros as well, in a manner similar to what was done with regions in [9]. The partially gate exhaustive transition fault model can be useful for both catching defects and diagnosing them. Static gate-exhaustive faults have been shown to more closely match silicon fall-out [10] and it is likely this will hold true for the transition faults as well. We expect to have silicon data to report on within a half year after ATS 2009. REFERENCES
[1] [2] [3] [4] [5] J. H. Patel Stuck-at Fault: A Fault Model for the Next Millennium Proc. International Test Conference, P10.2, 1998. A. K. Majhi and V. D. Agrawal Tutorial: Delay Fault Models and Coverage VLSI Design, 1998 K. Y. Cho, S. Mitra, and E. J. McCluskey Gate Exhaustive Testing Proc. International Test Conference, P31.3, 2005. I. Pomeranz and S. M. Reddy, On Test Data Compression and nDetection Test Sets, Design Automation Conf., 2003 C. Bamhart, V. Brunkhorst, F. Distler, 0. Farnsworth, B. Keller and B. Koenemann, "OPMISR: The Foundation for Compressed ATPG Vectors", in Proc. Intl. Test Conf., Oct. 2001, pp. 748-757. I. Pomeranz and S. M. Reddy, "On n-Detection Test Sets and Variable n -Detection Test Sets for Transition Faults", in Roc. 17th VLSITest Symp., April 1999, pp. 173-179. S. C. Ma, P. Franco and E. J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Experiment Results," in Proc. Intl. Test Conf., Oct. 1995, pp. 663-672. G. Bhargava, J. Sage, and D. Meehl, Achieving Serendipitous Ndetect Mark-Offs in Multi-Capture-Clock Scan Patterns, in Proc Intl. Test Conf, 2007, Paper 30.2 A. Jas, S. Natarajan and S. Patil, The Region-Exhaustive Fault Model, in Proc. Asian Test Symposium, 2007, pp. 13-18. R. Guo, S. Mitra, E. Amyeen, J. Lee, S. Sivaraj and S. Venkataraman, Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive, 2006, Proc. VLSI Test Symposium, pp. 71-76. www.cadence.com/products/ld/true_time_test U.S. Patent 5546408, Hierarchical Pattern Faults for Describing Logic Circuit Failure Mechanisms, 1996. R. D. Blanton, K. N. Dwarakanath and R. Desineni, Defect Modeling Using Fault Tuples, IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, Nov. 2006, pp 2450-2464.J. Clerk Maxwell, A Treatise on Electricity and Magnetism, 3rd ed., vol. 2. Oxford: Clarendon, 1892, pp.6873.

[6]

[7]

[8]

[9] [10]

[11] [12] [13]

Figure 7. ATPG and simulation results.