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UC3842/UC3843/UC3844/UC3845
SMPS Controller
Features
Low Start up Current Maximum Duty Clamp UVLO With Hysteresis Operating Frequency up to 500KHz
Description
The UC3842/UC3843/UC3844/UC3845 are fixed frequencycurrent-mode PWM controller. They are specially designed for Off-Line and DC to DC converter applications with minimum external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator and a high current totempole output for driving a Power MOSFET. The UC3842 and UC3844 have UVLO thresholds of 16V (on) and 10V (off). The UC3843 and UC3845 are 8.5V(on) and 7.9V (off). The UC3842 and UC3843 can operate within 100% duty cycle. The UC3844 and UC3845 can operate with 50% duty cycle.
8-DIP 8-SOP
14-SOP
* NORMALLY 8DIP/8SOP PIN NO. * ( ) IS 14SOP PINNO. * TOGGLE FLIP FLOP USED ONLY IN UC3844, UC3845
Rev. 1.0.1
2002 Fairchild Semiconductor Corporation
UC3842/UC3843/UC3844/UC3845
Note: 1. Board Thickness 1.6mm, Board Dimension 76.2mm 114.3mm, (Reference EIA / JSED51-3, 51-7) 2. Do not exceeed PD and SOA (Safe Operation Area)
14SOP
8SOP
AMBIENT TEMPERATURE ()
Thermal Data
Characteristic Thermal Resistance Junction-ambient Symbol Rthj-amb(MAX) 8-DIP 100 8-SOP 265 14-SOP 180 Unit C/W
Pin Array
8DIP,8SOP 14SOP
COMP 1
VREF
COMP 1
14 VREF
VFB 2
VCC
N/C
13
N/C
CURRENT SENSE
OUTPUT
VFB 3
12
VCC
RT/ CT 4
5 GND
N/C 4
11 PWR VC
CURRENT SENSE
10 OUTPUT
N/C
GND
RT/C T 7
PWR GND
UC3842/UC3843/UC3844/UC3845
Electrical Characteristics
(VCC=15V, RT=10k, CT=3.3nF, TA= 0C to +70C, unless otherwise specified) Parameter REFERENCE SECTION Reference Output Voltage Line Regulation Load Regulation Short Circuit Output Current OSCILLATOR SECTION Oscillation Frequency Frequency Change with Voltage Oscillator Amplitude ERROR AMPLIFIER SECTION Input Bias Current Input Voltage Open Loop Voltage Gain Power Supply Rejection Ratio Output Sink Current Output Source Current High Output Voltage Low Output Voltage CURRENT SENSE SECTION Gain Maximum Input Signal Power Supply Rejection Ratio Input Bias Current OUTPUT SECTION Low Output Voltage High Output Voltage Rise Time Fall Time Start Threshold Min. Operating Voltage (After Turn On) VOL ISINK = 20mA ISINK = 200mA VOH tR tF ISOURCE = 20mA ISOURCE = 200mA TJ = 25C, CL= 1nF (Note 3) TJ = 25C, CL= 1nF (Note 3) UC3842/UC3844 UC3843/UC3845 UC3842/UC3844 UC3843/UC3844 13 12 14.5 7.8 8.5 7.0 0.08 1.4 13.5 13.0 45 35 16.0 8.4 10.0 7.6 0.4 2.2 150 150 17.5 9.0 11.5 8.2 V V V V ns ns V V V V GV VI(MAX) PSRR IBIAS (Note 1 & 2) Vpin1 = 5V(Note 1) 12V VCC 25V (Note 1,3) 2.85 0.9 3 1 70 -3 3.15 1.1 -10 V/V V dB A IBIAS VI(E>A) GVO PSRR ISINK ISOURCE VOH VOL Vpin1 = 2.5V 2V VO 4V (Note3) 12V VCC 25V (Note3) Vpin2 = 2.7V, Vpin1 = 1.1V Vpin2 = 2.3V, Vpin1 = 5V Vpin2 = 2.3V, RL = 15k to GND Vpin2 = 2.7V, RL = 15k to Pin 8 2.42 65 60 2 -0.6 5 -0.1 2.50 90 70 7 -1.0 6 0.8 -2 2.58 1.1 A V dB dB mA mA V V f f/VCC VOSC TJ = 25C 12V VCC 25V 47 52 0.05 1.6 57 1 kHz % VP-P VREF VREF VREF ISC TJ = 25C, IREF = 1mA 12V VCC 25V 1mA IREF 20mA TA = 25C 4.90 5.00 6 6 -100 5.10 20 25 -180 V mV mV mA Symbol Conditions Min. Typ. Max. Unit
UC3842/UC3843/UC3844/UC3845
UC3842
High peak currents associated with capacitive loads necessitate careful grounding techniques Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
UC3842/UC3843/UC3844/UC3845
UC3842/44 UC3843/45
During Under-Voltage Lock-Out, the output driver is biased to a high impedance state. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with output leakage current.
UC3842/UC3843/UC3844/UC3845
Oscillator timing capacitor, CT, is charged by VREF through RT and discharged by an internal current source. During the discharge time, the internal clock signal blanks the output to the low state. Selection of RT and CT therefore determines both oscillator frequency and maximum duty cycle. Charge and discharge times are determined by the formulas: tc = 0.55 RT CT
0.0063RT 2.7 t D = R T C T I n --------------------------------------- 0.0063R T 4
UC3842/UC3843/UC3844/UC3845
Shutdown of the UC3842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.
UC3842/UC3843
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%. Note that capacitor, CT, forms a filter with R2 to suppress the leading edge switch spikes.