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VSS
AI01640
NC 1 28 NC
MOT 1 24 VCC MOT 2 27 VCC
NC 2 23 SQW NC 3 26 SQW
NC 3 22 NC NC 4 25 NC
AD0 4 21 RCL AD0 5 24 RCL
AD1 5 20 NC AD1 6 23 NC
AD2 6 19 IRQ AD2 7 22 IRQ
M48T86 M48T86
AD3 7 18 RST AD3 8 21 RST
AD4 8 17 DS AD4 9 20 DS
AD5 9 16 NC AD5 10 19 NC
AD6 10 15 R/W AD6 11 18 R/W
AD7 11 14 AS AD7 12 17 AS
VSS 12 13 E VSS 13 16 E
AI01641 VSS 14 15 NC
AI01642
2/23
M48T86
For the 28 lead SOIC, the battery/crystal package AD0-AD7 (Multiplexed Bi-Directional Address/
part number is "M4T28-BR12SH1". Data Bus). The M48T86 provides a multiplexed
Automatic deselection of the device provides in- bus in which address and data information share
surance that data integrity is not compromised the same signal path. The bus cycle consists of
should V CC fall below specified Power-fail Dese- two stages; first the address is latched, followed by
lect Voltage (V PFD) levels. The automatic deselec- the data. Address/Data multiplexing does not slow
tion of the device remains in effect upon power up the access time of the M48T86, since the bus
for a period of 200ms (max) after V CC rises above change from address to data occurs during the in-
VPFD, provided that the Real Time Clock is running ternal RAM access time. Addresses must be valid
and the count down chain is not reset. This allows prior to the falling edge of AS, at which time the
sufficient time for V CC to stabilize and gives the M48T86 latches the address present on AD0-
system clock a wake up period so that a valid sys- AD7. Valid write data must be present and held
tem reset can be established. stable during the latter portion of the R/W pulse. In
a read cycle, the M48T86 outputs 8 bits of data
The block diagram in Figure 3 shows the pin con- during the latter portion of the DS pulse. The read
nections and the major internal functions of the cycle is terminated and the bus returns to a high
M48T86.
impedance state upon a high transition on R/W.
SIGNAL DESCRIPTION AS (Address Strobe Input). A positive going
pulse on the Address Strobe (AS) input serves to
VCC, VSS. DC power is provided to the device on
demultiplex the bus. The falling edge of AS causes
these pins.The M48T86 utilizes a 5V VCC.
the address present on AD0-AD7 to be latched
SQW (Square Wave Output). During normal op- within the M48T86.
eration (i.e. valid VCC), the SQW pin can output a
MOT (Mode Select). The MOT pin offers the flex-
signal from one of 13 taps.The frequency of the
ibility to choose between two bus types. When
SQW pin can be changed by programming Regis-
connected to VCC, Motorola bus timing is selected.
ter A as shown in Table 10. The SQW signal can
When connected to V SS or left disconnected, Intel
be turned on and off using the SQWE bit (Register
bus timing is selected. The pin has an internal pull-
B; bit 3). The SQW signal is not available when
down resistance of approximately 20K ohms.
VCC is less than VPFD.
3/23
M48T86
OSCILLATOR /8 / 64 / 64
IRQ
DS
BCD/BINARY RCL
R/W INCREMENT
BUS
INTERFACE STORAGE
AS REGISTERS
(114 BYTES)
AD0-AD7
AI01643
DS (Data Strobe Input). The DS pin is also re- IRQ (Interrupt Request Output). The IRQ pin is
ferred to as Read (RD). A falling edge transition on an open drain output that can be used as an inter-
the Data Strobe (DS) input enables the output dur- rupt input to a processor. The IRQ output remains
ing a a read cycle. This is very similar to an Output low as long as the status bit causing the interrupt
Enable (G) signal on other memory devices. is present and the corresponding interrupt-enable
E (Chip Enable Input). The Chip Enable pin bit is set. IRQ returns to a high impedance state
must be asserted low for a bus cycle in the whenever Register C is read. The RST pin can
M48T86 to be accessed. Bus cycles which take also be used to clear pending interrupts. Because
place without asserting E will latch the addresses the IRQ bus is an open drain output, it requires an
present, but no data access will occur. external pull-up resistor to V CC.
4/23
M48T86
RST (Reset Input). The M48T86 is reset when RCL (RAM Clear). The RCL pin is used to clear
the RST input is pulled low. With a valid VCC ap- all 114 storage bytes, excluding clock and control
plied and a low on RST, the following events oc- registers, of the array to FF(hex) value. The array
cur: will be cleared when the RCL pin is held low for at
1. Periodic Interrupt Enable (PIE) bit is cleared to least 100ms with the oscillator running. Usage of
a zero. (Register B; Bit 6) this pin does not affect battery load. This function
is applicable only when V CC is applied.
2. Alarm Interrupt Enable (AIE) bit is cleared to a
zero.(Register B; bit 5) R/W (Read/Write Input). The R/W pin is utilized
to latch data into the M48T86 and provides func-
3. Update Ended Interrupt Request (UF) bit is
tionality similar to W in other memory systems.
cleared to a zero. (Register C; Bit 4)
4. Interrupt Request (IRQF) bit is cleared to a zero. ADDRESS MAP
(Register C Bit 7) The address map of the M48T86 is shown in Fig-
5. Periodic Interrupt Flag (PF) bit is cleared to a ure 9. It consists of 114 bytes of user RAM, 10
zero. (Register C; Bit 6) bytes of RAM that contain the RTC time, calendar
6. The device is not accessible until RST is re- and alarm data, and 4 bytes which are used for
turned high. control and status. All bytes can be read or written
7. Alarm Interrupt Flag (AF) bit is cleared to a zero. to except for the following:
(Register C; Bit 5) 1. Registers C & D are read-only.
8. The IRQ pin is in the high impedance state. 2. Bit 7 of Register A is read-only.
9. Square Wave Output Enable (SQWE) bit is The contents of the four Registers A, B, C, and D
cleared to zero. (Register B; Bit 3). are described in the "Registers" section.
10.Update Ended Interrupt Enable (UIE) is cleared
to a zero. (Register B; Bit 4)
5/23
M48T86
TIME, CALENDAR, AND ALARM LOCATIONS shows the binary and BCD formats of the time, cal-
The time and calendar information is obtained by endar, and alarm locations. The 24/12 bit (Regis-
reading the appropriate memory bytes. The time, ter B; Bit 1) cannot be changed without
calendar, and alarm registers are set or initialized reinitializing the hour locations. When the 12-hour
by writing the appropriate RAM bytes. The con- format is selected, a logic one in the high order bit
tents of the time, calendar, and alarm bytes can be of the hours byte represents PM. The time, calen-
either Binary or Binary-Coded Decimal (BCD) for- dar, and alarm bytes are always accessible be-
mat. Before writing the internal time, calendar, and cause they are double buffered. Once per second
alarm register, the SET bit (Register B; Bit 7) the ten bytes are advanced by one second and
should be written to a logic "1". This will prevent checked for an alarm condition. If a read of the
updates from occurring while access is being at- time and calendar data occurs during an update, a
tempted. In addition to writing the time, calendar, problem exists where seconds, minutes, hours,
and alarm registers in a selected format (binary or etc. may not correlate. However, the probability of
BCD), the Data Mode (DM) bit (Register B; Bit 2), reading incorrect time and calendar data is low.
must be set to the appropriate logic level ("1" sig- Methods of avoiding possible incorrect time and
nifies binary data; "0" signifies Binary Coded Dec- calendar reads are reviewed later in this text.
imal (BCD data). All time, calendar, and alarm
bytes must use the same data mode. The SET bit NON-VOLATILE RAM
should be cleared after the Data Mode bit has The 114 general purpose non-volatile RAM bytes
been written to allow the Real Time Clock to up- are not dedicated to any special function within the
date the time and calendar bytes. Once initialized, M48T86. They can be used by the processor pro-
the Real Time Clock makes all updates in the se- gram as non-volatile memory and are fully acces-
lected mode. The data mode cannot be changed sible during the update cycle.
without reinitializing the ten data bytes. Table 3
6/23
M48T86
5V 5V
960Ω 1.15kΩ
FOR ALL
OUTPUTS IRQ
EXCEPT IRQ
AI01644 AI01645
7/23
M48T86
VCC
4.5V
VPFD
VSO
tF tR
tREC
AI01646
8/23
M48T86
Table 9. AC Characteristics
(TA = 0 to 70 °C; VCC = 4.5V to 5.5V)
M48T86
Symbol Parameter Unit
Min Typ Max
tCYC Cycle Time 160 ns
When an interrupt event occurs, the related flag bit One, two, or three bits can be set when reading
(Register C; Bit 6 = PF; Bit 5 = AF; Bit 4 = UF) is Register C. Each utilized flag bit should be exam-
set to a logic "1". These flag bits are set indepen- ined when read to ensure that no interrupts are
dent of the state of the corresponding enable bit in lost.
Register B and can be used in a polling mode with- The second flag bit usage method is with fully en-
out enabling the corresponding enable bits. The abled interrupts. When an interrupt flag bit is set
interrupt flag bits are status bits which software and the corresponding enable bit is also set, the
can interrogate as necessary. IRQ pin is asserted low. IRQ is asserted as long as
When a flag is set, an indication is given to soft- at least one of the three interrupt sources has its
ware that an interrupt event has occurred since the flag and enable bits both set. The IRQF bit (Regis-
flag bit was last read; however, care should be tak- ter C; Bit 7) is a "1" whenever the IRQ pin is being
en when using the flag bits as all are cleared each driven low. Determination that the RTC initiated an
time Register C is read. Double latching is includ- interrupt is accomplished by reading Register C.A
ed with Register C so that bits which are set, re- logic "1" in the IRQF bit indicates that one or more
main stable throughout the read cycle. All bits interrupts have been initiated by the M48T86. The
which are set high are cleared when read. Any act of reading Register C clears all active flag bits
new interrupts which are pending during the read and the IRQF bit.
cycle are held until after the cycle is completed.
9/23
M48T86
tCYC
AS
tASW tASD
DS
tDSL tDSH
R/W
AD0-AD7
AI01647
tCYC
AS
DS
tDSL tDSH
R/W
tCS tCH
tAS tAH
tDW tDHW
AD0-AD7
AI01648
10/23
M48T86
AS
tCYC
DS
tDSL tDSH
tRWS tRWH
R/W
tCS tCH
tAH
tAH tDHR
AD0-AD7
(Read)
AI01649
11/23
M48T86
0 00 0 SECONDS
13 0D 3 MINUTES ALARM
4 HOURS BCD OR
14 0E BINARY
5 HOURS ALARM FORMAT
6 DAY OF WEEK
7 DATE OF MONTH
8 MONTH
9 YEAR
114 STORAGE REGISTERS
BYTES 10 REGISTER A
11 REGISTER B
12 REGISTER C
13 REGISTER D
127 7F
AI01650
UPDATE CYCLE INTERRUPT SQW frequency selection shares the 1-of-15 se-
After each update cycle, the update cycle ended lector with the periodic interrupt generator. Once
flag bit (UF) (Register C; Bit 4) is set to a "1". If the the frequency is selected, the output of the SQW
update interrupt enable bit (UIE) (Register B; Bit 4) pin can be turned on and off under program control
is set to a "1", and the SET bit (Register B; Bit 7) is with the square wave enabled (SQWE).
a "0", then an interrupt request is generated at the
end of each update cycle. OSCILLATOR CONTROL BITS
When the M48T86 is shipped from the factory the
SQUARE WAVE OUTPUT SELECTION internal oscillator is turned off. This feature pre-
Thirteen of the 15 divider taps are made available vents the lithium energy cell from being dis-
to a 1-of-15 selector, as shown in the block dia- charged until it is installed in a system. A pattern of
gram of Figure 3. The purpose of selecting a divid- "010" in Bits 4-6 of Register A will turn the oscilla-
er tap is to generate a square wave output signal tor on and enable the countdown chain. A pattern
on the SQW pin. The RS3-RS0 bits in Register A of "11X" will turn the oscillator on, but holds the
establish the square wave output frequency. countdown chain of the oscillator in reset. All other
These frequencies are listed in Table 10. The combinations of Bits 4-6 keep the oscillator off.
12/23
M48T86
UPDATE CYCLE read valid time and date information. If this inter-
The M48T86 executes an update cycle once per rupt is used, the IRQF bit (Register C; Bit 7) should
second regardless of the SET bit (Register B; Bit be cleared before leaving the interrupt routine.
7). When the SET bit is asserted, the user copy of A second method uses the Update-In-Progress
the double buffered time, calendar, and alarm (UIP) bit (Register A; Bit 7) to determine if the up-
bytes is frozen and will not update as the time in- date cycle is in progress. The UIP bit will pulse
crements. However, the time countdown chain once per second. After the UIP bit goes high, the
continues to update the internal copy of the buffer. update transfer occurs 244µs later. If a low is read
This feature allows accurate time to be main- on the UIP bit, the user has at least 244µs before
tained, independent of reading and writing the the time/calendar data will be changed. Therefore,
time, calendar, and alarm buffers. This also guar- the user should avoid interrupt service routines
antees that the time and calendar information will that would cause the time needed to read valid
be consistent. The update cycle also compares time/calendar data to exceed 244µs.
each alarm byte with the corresponding time byte The third method uses a periodic interrupt to deter-
and issues an alarm if a match or if a "don't care" mine if an update cycle is in progress. The UIP bit
code is present in all three positions. is set high between the setting of the PF bit (Reg-
There are three methods of accessing the real ister C; Bit 6). Periodic interrupts that occur at a
time clock that will avoid any possibility of obtain- rate greater than t BUC allow valid time and date in-
ing inconsistent time and calendar data. The first formation to be reached at each occurrence of the
method uses the update-ended interrupt. If en- periodic interrupt.The reads should be completed
abled, an interrupt occurs after every update cycle within 1/(t PL/2 + t BUC) to ensure that data is not
which indicates that over 999ms are available to read during the update cycle.
13/23
M48T86
UIP
tBUC tUC
AI01651
UIP
tBUC tUC
tPI tPI tPI
PF
UF
AI01652B
14/23
M48T86
REGISTER A
MSB
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
UIP OSC2 OSC1 OSC0 RS3 RS2 RS1 RS0
15/23
M48T86
REGISTER B
MSB
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
SET PIE AIE UIE SQWE DM 24/12 DSE
16/23
M48T86
REGISTER C
MSB
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
IRQF PF AF UF 0 0 0 0
REGISTER D
MSB
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
VRT 0 0 0 0 0 0 0
17/23
M48T86
18/23
M48T86
Example: M48T86 MH 1 TR
Device Type
M48T
Package
PC = PCDIP24
MH (1) = SOH28
Temperature Range
1 = 0 to 70 °C
Note: 1. The SOIC package (SOH28) requires the battery/crystal package (SNAPHAT) which is ordered separately under the part number
"M4T28-BR12SH1" in plastic tube or "M4T28-BR12SH1TR" in Tape & Reel form.
Caution: Do not place the SNAPHAT battery/crystal package "M4T28-BR12SH1" in conductive foam since will drain the lithium button-cell
battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
19/23
M48T86
Table 13. PCDIP24 - 24 pin Plastic DIP, battery CAPHAT, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 8.89 9.65 0.3500 0.3799
A1 0.38 0.76 0.0150 0.0299
A2 8.36 8.89 0.3291 0.3500
B 0.38 053 0.0150 0.0209
B1 1.14 1.78 0.0449 0.0701
C 0.20 0.31 0.0079 0.0122
D 34.29 34.80 1.3500 1.3701
E 17.83 18.34 0.7020 0.7220
e1 2.29 2.79 0.0902 0.1098
e3 25.15 30.73 0.9902 1.2098
eA 15.24 16.00 0.6000 0.6299
L 3.05 3.81 0.1201 0.1500
N 24 24
Figure 15. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Outline
A2 A
A1 L C
B1 B e1
eA
e3
1 PCDIP
20/23
M48T86
Table 14. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 3.05 0.1201
A1 0.05 0.36 0.0020 0.0142
A2 2.34 2.69 0.0921 0.1059
B 0.36 0.51 0.0142 0.0201
C 0.15 0.32 0.0059 0.0126
D 17.71 18.49 0.6972 0.7280
E 8.23 8.89 0.3240 0.3500
e 1.27 – – 0.0500 – –
eB 3.20 3.61 0.1260 0.1421
H 11.51 12.70 0.4531 0.5000
L 0.41 1.27 0.0161 0.0500
α 0° 8° 0° 8°
N 28 28
CP 0.10 0.0039
Figure 16. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2 A
C
B e eB
CP
D
N
E H
A1 α L
1
SOH-A
21/23
M48T86
Table 15. M4T28-BR12SH - SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 9.78 0.3850
A1 6.73 7.24 0.2650 0.2850
A2 6.48 6.99 0.2551 0.2752
A3 0.38 0.0150
B 0.46 0.56 0.0181 0.0220
D 21.21 21.84 0.8350 0.8598
E 14.22 14.99 0.5598 0.5902
eA 15.55 15.95 0.6122 0.6280
eB 3.20 3.61 0.1260 0.1421
L 2.03 2.29 0.0799 0.0902
Figure 17. M4T28-BR12SH - SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline
A1 A2
A A3
eA B L
eB
D
SH
22/23
M48T86
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
23/23