Power Integrity: Effective management of timing, power, and signal integrity

By Pete McCrorie and Harish Kriplani

As device geometries shrink and device densities increase, it has become increasingly difficult to design chips that are robust from the perspectives of timing, power, and noise. Good power integrity cannot be achieved by simply modifying power routing just prior to tapeout based on signoff analysis results. It comes as a result of paying attention to power requirements throughout the design flowfrom early design conception, through implementation, all the way to signoff. This paper explains how a comprehensive power integrity solution that is integrated with design implementation and timing/SI analysis is necessary to avoid missed tapeout windows or failed silicon.

Technology and Design Trends that Impact Power Integrity

Perhaps the most significant technology trend (in the sense that it drives many of the others) is that process technologies continue to shrink for ASIC and ASSP designs. More than ever, design teams need to be more concerned with minimizing power consumption for the following reasons: Smaller geometries enable more functionality to be packed within same area of silicon Larger designs can be physically implemented in a single chip Leakage of the transistors continues to increase with each new technology (Figure 1) The overall result is that power-per-mm2 continues to increase and therefore the need for power management increases.

Figure 1: Leakage power increases with advanced technology Given the growing concerns around managing power consumption, design teams are employing advanced low-power design techniques to minimize power and help with the cooling issues

associated with large designs. Advanced low-power design techniques include the use of multiswitching threshold transistors (Multi-Vt), using multiple power supply domains with multiple voltages (MSMV), power shut-off (PSO) and dynamic voltage and frequency scaling (DVFS). Often, a combination of these techniques must be used to meet the required power targets.

Multi-Vt Transistors
One of way to manage leakage involves using transistors with different switching thresholds. Low-threshold transistors enable high performance but suffer from high leakage. On the other hand, high-threshold transistors suffer less leakage but offer less performance. Advanced standard cell libraries now contain cells that are optimized for power or optimized for timing. These cells enable design implementation solutions to automatically optimize timing performance, while minimizing leakage power.

Multi-Supply, Multi-Voltage (MSMV)

The use of multiple power domains running at different voltages enables power savings, but this also makes the life of a design engineer more complex. By reducing the supply voltage, signals transition over a smaller voltage, which results in reduced switching currents. Designs using multiple voltage domains need careful planning (a) to ensure that timing can be met at the selected supply voltages, and (b) because voltage level shifters need to interface signals crossing from one "voltage domain" to another. Signal integrity issues become even more complex with MSMV, because nets driven with higher supply voltages (called super-aggressors) can inject more noise into adjacent nets that are driven by lower voltages.

Power Shut Off (PSO)

Power Shut Off describes the technique of inserting power switches between the power rails and the active logic, thereby allowing the logic to be completely powered off when not currently required. The impact of PSO on power analysis is obvious, the number of power switches needs to be optimized based on IR drop and power ramp-up time constraints.

Dynamic Voltage and Frequency Scaling (DVFS)

If all of the above weren't complicated enough, advanced design teams use a technique called Dynamic Voltage and Frequency Scaling (DVFS) to further minimize the power consumption of their designs. DVFS refers to dynamically changing the supply voltage based on the required frequency of operation of local logic blocks. Logic that needs to run at full speed gets maximum supply voltage, while logic that can run at reduced speed gets reduced voltages. This design technique is most appropriate for complex SoC designs that have multiple modes of operation. However, it dramatically increases the complexity of analysis.

Thermal Analysis
On-chip temperature control has been a known problem for some time; this mainly involves using special cooling techniques associated with the packagesfins, fans, liquid cooling, etc. In general, packages with higher cooling characteristics cost more, so minimizing on-chip power can result in significant cost reductions if a cheaper package can be utilized.

Focus around on-chip temperature variations is somewhat new, and increasing with the use of multiple modes of operation. Thermal variations directly impact timing and SI analysis by changing device characteristics, thereby causing additional setup/hold time violations. On-chip thermal analysis also enables a design team to understand if high leakage components are located in high temperature areas; relocation of such components could result in a cooler chip that requires less expensive packaging.

Manufacturing Effects
On top of all the complexities associated with creating the design itself, design teams must also account for the complexities associated with the manufacturing process, because small variations in the process can result in large variations in timing, power, and signal integrity. Multi-mode, multi-corner (MMMC) analysis is becoming more common, where chip performance is validated for many modes of operation at multiple process corners. As the number of corners increases, a statistical approach is necessary to bound the runtimes. Statistical static timing analysis (SSTA) is already in use for advanced designs, and there is a growing focus on statistical leakage power analysis (SLPA) to better optimize power across all process corners. The end result is that most aspects of designing and verifying modern IC designs are becoming increasingly challenging, while the cost of missing the schedule continue to grow. Data from the Global Semiconductor Association (GSA) shows that 89% of designs miss their deadlines by an average of 44%, and that the cost of being even three months late can equate to as much as $500M in lost profits.

Power Integrity Analysis

A comprehensive power integrity analysis solution must enable a design team to understand how power, timing, and signal integrity interact, potentially resulting in silicon failures. This solution must obviously be available for pre-tapeout signoff; however, it is extremely important that it is also available during the complete physical design implementation flow, including: Floorplanning Physical Implementation Signoff This means that the solution must be tightly integrated into the design environment. It is important that the integrated power/timing/SI analysis solution provides consistent results throughout the design flow, otherwise there is the potential that significant late-stage re-work will be required to address newly uncovered problems. During floorplanning, design teams need to determine the approach to deliver power across the design. The two most common approaches are to use tree routing and grid (mesh) routing for the power rails. Power integrity analysis helps a design team understand the tradeoffs associated with each approach (typically tree routing uses less area and is less robust without careful attention, while gridded power routing costs more in area and provides a very robust

network). At the early floorplanning stages, comprehensive design data is not typically available, so the power analysis solution must provide the best accuracy with the available data. During physical implementation, design teams are trying to complete the placement of the blocks/cells and optimize timing. At this stage, most of the design data is available, and so a more accurate analysis can be accomplished. Because achieving timing closure is tough, a fixed operating voltage is often assumed at this point the challenge is to create power rails that meet these requirements. Once a design is getting close to tapeout, comprehensive, full-chip, full-accuracy analysis is required to try to catch any remaining issues that might cause silicon failure or yield issues. There are five major requirements a power/timing/signal integrity analysis solution must support; the following section discusses these requirements in more detail.

1. Power Rail Design and Optimization

During the early stages of power rail design, static power integrity analysis is used to help ensure that the power network is sufficiently robust. Static analysis is used for two reasons, first because static analysis can be used for both IR drop and power rail electromigration, and second because there isnt sufficient design data during floorplanning to enable dynamic analysis. It is during the floorplanning stage that design teams must decide on the structure of the power routing tree versus grid. Once the optimal structure is determined, power integrity analysis is used to ensure that the width of the routes and the number of vias are sufficient to meet IR drop and electromigration requirements.

2. De-coupling Capacitance Insertion and Optimization

As a logic gate switches, it draws/sources transient currents of very short duration from/to the power rails. When large a number of gates simultaneously switch, the resulting large transient currents could lead to large dynamic IR drops through resistive power network. While nonswitching logic acts as a local de-coupling capacitance, to mitigate this problem, de-coupling capacitance cells are inserted to provide a local charge source that minimizes the local IR drop in the area by reducing the current drawn through the power rails. The challenge for the design team is to optimize the number, location, and size of the decoupling capacitance cells too few causes high dynamic IR drops, while too many extends the power-up time, increases leakage current, impacts yield, and impacts die area. Achieving optimal de-coupling capacitance utilization requires accurate dynamic analysis during design implementation. It is wise to initially start with de-coupling capacitance around high-drive buffers in clock and data networks. De-coupling capacitance can then be optimized during early rail analysis. As more accurate power dissipation information becomes available, when blocks of logic have been created, more accurate dynamic analysis should be used to further tune the amount and location of the added de-coupling capacitors. Figure 2 illustrates a proposed decoupling capacitance insertion and optimization flow.

Initial De-coupling Capacitance Insertion (rules-based)

Dynamic IR Drop Analysis

ECO

IR Drop-aware Timing Analysis

De-coupling Capacitance Optimization

Figure 2: Recommended de-coupling capacitance insertion and optimization flow.

3. Power Switch Insertion and Optimization

In many modern power-sensitive designs, to minimize power consumption it is necessary for different functional blocks to be implemented in such a way that they can be completely powered-down and isolated when not in use. Power switches are used to isolate the block from the power supply, as shown in figure 3.

Power Switches

Power Switches

VDD

Block Under Power Management

Power Switches

VDD

Power Switches

Figure 3: Power switches connect the block to the un-switched VDD power rail. When the chips Power Management Unit (PMU) detects that a block is not currently needed, it initiates a series of events to power-down the block. Before any power-down can occur, however, surrounding logic must be isolated and/or stabilized to prevent possible data

corruption. Once the surrounding logic has been isolated and/or stabilized, the block is powered-down by deactivating the power switches. Once the PMU logic detects that a block is again required, it triggers another sequence of events that start the powering-up cycle. Powering-up a block can demand a large, dynamic current, known as rush current, and design teams need to make sure that this rush current does not create problems in the surrounding logic by causing local IR drop. Controlling the amount of rush current is achieved by changing the number and size of the power switches and the sequential delay between them, as shown in figure 4.
Rush Current

Fast power-up time Potential local IR drop

Time

Rush Current

Slower power-up time minimizes local IR drop

Time

Figure 4: High rush current (top) versus lower rush current (bottom). An advanced power integrity solution helps a design team determine how to optimize the power switches. Too many power switches can increase rush current, while too few can increase the IR drop seen by the logic. There needs to be a careful balance. The planning and optimization of power switches should be driven by detailed IR drop analyses, where steady state analysis shows the IR drop when the logic is operating normally, and dynamic power-up analysis shows the impact on surrounding logic when blocks are re-activated. In practice, the number/size of the power switches is determined by the maximum tolerable IR drop, and the sequencing delay is used to manage the rush currents.

4. Impact of IR drop on timing, including clock jitter

Dynamic IR drop varies from cycle-to-cycle, depending on the amount of switching activity. This IR drop variation in-turn causes delay variation in both clock networks and signal paths, leading to clock jitter, increases in clock skew, and additional setup and/or hold violations. Clock Jitter is defined as the variation in the arrival time of the clock edge as illustrated in Figure 5. Clock jitter analysis identifies the difference in late and early arrival times of clock edges at various register clock pins. The late paths are calculated based on high-activity or max IR drop results, while early paths are calculated based on low-activity or min IR drop results.

Figure 5: Clock Jitter due to IR drop-induced delay variation. Clock Skew analysis identifies the difference in arrival times of the launch and capture registers as illustrated in Figure 6. Clock Skew analysis uses high activity IR drop for late path delay calculation and low activity IR drop for early path delay calculation.

Figure 6: Clock Skew due to IR drop-induced delay variation. In addition to IR drop induced clock skew, IR drop on the gates within the signal paths causes delay variation for the signals, which in turn causes additional setup and hold time violations. Hopefully, it is now clear why it is increasingly important that IR drop-aware static timing analysis be performed, to account for the impact of IR drop on clock jitter, clock skew, and setup and hold times.

5. Impact of IR drop on Signal integrity

Signal integrity issues are caused when a switching net (aggressor) injects noise onto an adjacent net (victim). Signal integrity analysis determines whether the injected noise will be propagated into a downstream latch/flip-flop and captured as an incorrect logic state. IR drop can decrease the drive strength of a victim net, making it even more prone to signal integrity issues. Because of this, it is important to take into account IR drop during signal integrity analysis.

Summary
Design teams are increasingly facing parallel challenges of minimizing power while at the same time continuing to close timing and avoid signal integrity issues under complex conditions. While timing closure remains the number number-one issue that challenges most design teams, power management has rapidly ascended to become the number number-two concern. Physics dictates that power, timing and signal integrity are all inter-related, and that independent analysis of each of these components will not catch all of the potential issues. The conclusion is that effective management of timing, power, and signal integrity requires an integrated analysis solution within the design environment, enabling analysis from early floorplanning to pre-tapeout signoff.

Pete McCrorie is currently focused on product marketing for power rail analysis and mixed signal implementation at Cadence. Before joining Cadence, McCrorie was managing all extraction and analysis products at Simplex. McCrorie has his Masters degree in Physics with Electronics from Liverpool University, UK. Harish Kriplani is currently an R&D Group Director at Cadence, where he is responsible for architecting and managing solutions for power/power grid analysis and design. Kriplani received his BTech from IIT Kanpur and PhD from University of Illinois at Urbana-Champaign and holds 5 US patents.