RESUME

Mr. Vittal.M Mobile:+91-9741712529 e-mail: vitthalt@karmic.co.in

PROFILE: During the Last three mount have complete the full chip design include the nine modules and top level integration include the DRC and LVS, and 2 year working experience in IC Testing (Dual to single controller conversion) and Digital layout design for Karmic Training Centre, Includes Layout of combination and sequential circuit, Memory controller modules. Also done verilog extraction of basic gates and simulation. Trained in Analog layouts from last 3 months. Undergone 2 years of training in various aspects of VLSI design. TECHNICAL SKILL: Simulation tools Layout design tools Operating Systems Programming Skills

: NGSpice, Spice3, Spice2cpp, H2flot,Xcall,TUI,cver,ncverilog, : Magic, cadence, : LINUX, Ubuntu, WINDOWS, : Basics of C, Perl, HTML, Pascal, ITP, VDHL, and Verilog.

PROFESSIONAL EXPERIENCE: 1. 0.35um Technology ( Magic Tool ) 2. 28nm Technology ( Cadence Tool ) PROJECTS: 1. Full chip integration
Client: KARMIC Nesargi India Duration: Sept 2012 to Dec 2012

Team size: 4
Description and Responsibilities:

1. Integrating the 9 modules into one chip

2. Pin reduction at top level 3. Integrating modules with 2x10 and 2x20 pad frame 4. Induvidual modules simulation at top level 5. Overall layout and simulation using SPICE tool.

REFERENCES: Dr. S S Mahant-Shetti, MD KarMic.

2. standard cell layout design and characterization : Client: Karmic Design Center Duration: March 2012 to August 2012 Team Size: 1 Description and Responsibilities: 1. Design and characterization of a standard cell. 2. Physical verification using vhdl, verilog, alliance, LTspice, and spice3. 3. Understand the basic process technology, fabrication techniques. 4. DRC and LVS completed blocks. 5. parasitic extraction 6. Layout verification of using Gemini tools. 3. VHDL & Verilog projects: Client: Karmic Design Center Duration: January 2012 to February 2012 Team Size: 1 Description and Responsibilities: 1. verilog extraction of basic gates and simulation 2. Create the Test Bench on GPIO Verilog Modules. 4. VLCT DIB_Daig And TTR projects: Client: Ti Dallas Duration: August 2011 to October 2011 Team Size: 1 Description and Responsibilities: 1. working on Test Time reduction(TTR) 2. Correlation. And IC Pakaging 3. Wrote the Dib DaigTUI program, for Tesing the Board Device, 5. VLCT Conversion projects: Client: Ti Dallas Duration: October 2010 to August 2011 Team Size: 1 Description and Responsibilities: 1. Conversion programming to convert the Dual controller device to single controller device, and to convert in Straight Conversion(ResultsRecardActive) and UserStd Conversion(ProcessTest).

6. VLCT LAB Programing: Client: Karmic Training Center Duration: Jun 2010 to October 2010 Team Size: 1 Description and Responsibilities: 1. Understanding the Test chip Boards 2. Understanding the Clock Boads and Device functionality testing. 7. Analog Layouts: Client: Karmic Training Center Duration: November 2010 March 2011. Team Size: 1 Description and Responsibilities: 1. Differential amplifiers, Oscillator, Digital and Resistor blocks layouts. 2. Learned different types of matching and floor planning. 3. Comparator, Bias circuits layouts. 4. DRC and LVS (Assura) completed blocks. 5. Antenna checks. 6. RC extraction and parasitic reduction 8. Microprocessor 2013: Client: Karmic Training Center Duration: August 2009 to March 2010 Team Size: 5 Description and Responsibilities: 1. Worked on MEMORY design and layout of MSP430 2013. 9. Booth Multiplier: Client: Karmic Training Center Duration: January 2009 to April 2009 Team Size: 5 Description and Responsibilities: 1. Worked on 1616 Booth multiplier in 0.35u technology magic layout. 2. Worked on 1616 cross digital multiplier using the booth algorithm. 3. Layout verification of complete chip using Gemini tools. 10. PCB: Client: Karmic Training Center Duration: November 2008 to December 2008 Team Size: 2 Description and Responsibilities:

1. Worked on Mat switch project. This circuit produces a warning beep when somebody crosses a protected area in the home or office. The switch, hidden below the floor mat, triggers the alarm when the person walks over it. TRAINING AND SEMINARS 1. Conversion Projects (Singal to dual controller). 2. DIB Daig Program. 3. Correlation. And IC Pakaging 4. Analog preamp layout design and digital integrated circuits. 5. VLSI and CMOS integrated circuits. 6. Electrical circuits. 7. Attended workshops on VDAT. 8. Memory, EDUCATION 1. SSLC (Ningappayya.Shesappayya.Dingabarimat, Government High School Siddapur,) 2. MITx6.002x( completing online learning initiative of MASSACHUSETTS INSTITUTE OF TECHNOLOGY circuits and Electronics 6.002x) Taluk: Bilagi, Dist: Bagalkot, Karnataka, India, PERSONAL DETAILS Date of birth 09/01/1992.[DD/MM/YEAR/] Languages known Kannada and English. Declaration: I hereby declare that the information furnished above is to the best of my knowledge. Place : Belagaum Date : 20-02-2013 [DD MM YEAR]

[Vittal.M]