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Waqas Bin Khalid Lab 4

1) In this lab I learned how to make my master clock a slow clock. The master clock is set at a frequency of 50 MHz that is too fast for the naked eye to see any combination or do any computation. The master clock is slowed using a 24-bit signal. I also learned how to control inputs through a button on the board. Instead of slowing the master clock using a 24-bit signal, a push button switch can be used to generate a slow clock. Slow clock through switch is implemented through the debounce module. I learned how to program state machines using FPGA implemented an 1101 sequence detector. Learned about different VHDL programming constructs i.e. the use of switch and if-else statements in VHDL. 2) There are two types of state machines: Moore and Mealy. For Moore state machines, the outputs are functions only of the present state. Mealy state machines may have outputs that are functions of both the present state and the present inputs. Figure 1 illustrates the difference between the two types of state machines.

The additional operations involved in describing Mealy state machines versus Moore machines are minimal. To implement a Mealy state machine, an output must be described as a function of both the state bits and the inputs. Generally, synthesis tools support the use of both types of state machines. In the Moore machine model output depends only on the present state but in the Mealy machine the output depends on the both present state and the input. In the VHDL language, each state may be translated to an alternative of a case statement. The state transitions may then be specified with if statements.

3) Easy to write, to read, and to maintain sequential machines in VHDL. The code is less error-prone. High abstraction level for the logic and it is easy to trace the input and output logic. Concentration is on the algorithm and not on the schematic. Increased productivity and sequence detector is easily implemented using a state diagram in VHDL. The behavioral description of the state machine is made easier than the description by specifying the equations. In the same time, by using such a description the possibility of errors is reduced. 4) In this lab I learned how to make my master clock a slow clock. The master clock is set at a frequency of 50 MHz that is too fast for the naked eye to see any combination or do any computation. The master clock is slowed using a 24-bit signal. I also learned how to control inputs through a button on the board. Instead of slowing the master clock using a 24-bit signal, a push button switch can be used to generate a slow clock. Slow clock through switch is implemented through the debounce module. I learned how to program state machines using FPGA implemented an 1101 sequence detector. Learned about different VHDL programming constructs i.e. the use of switch and if-else statements in VHDL. 5) ----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 20:11:19 10/03/2012 -- Design Name: -- Module Name: Sequence_Detector - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Sequence_Detector is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; input : in STD_LOGIC; btn : in STD_LOGIC; output : out STD_LOGIC); end Sequence_Detector; architecture Behavioral of Sequence_Detector is type stateType is (stateA, stateB, stateC, stateD); signal currentState, nextState : stateType; --signal clkDiv :STD_LOGIC_VECTOR (24 downto 0); --signal sClk : STD_LOGIC; signal dbtn : STD_LOGIC; signal tempOutput : STD_LOGIC; begin DB1: entity work.debounce(fsm) port map(clk => clk, reset => '0', sw => btn, db_level => dbtn); -process (clk)

--------sClk <= clkDiv(24); process (dbtn,reset) begin ---if (reset='1') then currentState <= stateA; --default state on reset. output <= '0'; if (dbtn'event and dbtn = '1' ) then --(rising_edge(clk)) then CLK = '1' ) then if (reset='1') then currentState <= stateA; --default state on reset. output <= '0'; else currentState <= nextState; --state change. output <= tempOutput; end if; end if; end process; process(currentState,input) begin --elsif (CLK' event and end if; end process; begin if (clk'event and clk = '1') then clkDiv <= clkDiv + 1;

case currentState is when stateA => if input = '0' then nextState <= stateA; tempOutput <= '0'; else nextState <= stateB; tempOutput <= '0'; end if; when stateB => if input = '0' then nextState <= stateA; tempOutput <= '0'; else nextState <= stateC; tempOutput <= '0'; end if; when stateC => if input = '0' then nextState <= stateD; tempOutput <= '0'; else nextState <= stateC; tempOutput <= '0'; end if; when stateD => if input = '0' then nextState <= stateA; tempOutput <= '0'; else nextState <= stateB;

tempOutput <= '1'; end if; end case; end process; end Behavioral;

----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 19:34:41 10/03/2012 -- Design Name: -- Module Name: Counter - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Four_Counter is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC;

output : out STD_LOGIC_VECTOR (3 downto 0)); end Four_Counter; architecture Behavioral of Four_Counter is signal clkDiv: STD_LOGIC_VECTOR (24 downto 0); signal sClk: STD_LOGIC; signal r_reg: STD_LOGIC_VECTOR (3 downto 0); begin process(clk) begin if(clk'event and clk = '1') then clkDiv <= clkDiv + '1'; end if; end process; sClk <= clkDiv(24); process(sClk,reset,r_reg) begin if(reset = '1') then r_reg <= "0000"; elsif(sClk'event and sClk = '1') then r_reg <= r_reg + '1'; end if;

end process; output <= r_reg; end Behavioral;

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