The inputs required for the flow chart are -Instruction set summary -Execution unit specification -Rules

of operation To use the method first postulate an initial version of the EU with operational rules of EU.

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Clock gen

Bus controller

Control store
1

State sequencer
5

Inst- 3 Decoder

Control word decoder

2

Execution unit
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0.

With architecture specification as input begin with initial execution unitrefinement- final execution unit
Once flowcharts are fairly complete derive control word format using flowchart states. After defining control word formats assign bit patterns to the control fields that minimizes control word decoders between control store and execution unit Instruction decoders are defined by flowcharts and architecture specification Completed flowcharts, control word format and initial bus specification bus controller Define logic of state sequencer (which tells what to do next)
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1.

2.

3. 4.

5.

Specifications of a Processor
-Programmers Registers ( Index and pointer registers, GPRs)

-Instruction Types (data movement instructions, arithmetic and logic instructions, program control instructions)

-Addressing Modes (immediate addressing, direct addressing, register addressing, implied addressing.)

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MIN Processor
Instruction Format

Opcode
displacement

Rx

Mode

Ry

Optional depending on addressing mode

Rx- First operand register Ry- second operand register Mode- Second operand addressing mode.

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Addressing Modes
AB - Base ( RY) plus displacement A I - Register Indirect. RY holds the operand address AR Register Direct. Result stored in RY, for two operand instructions RY is an operand source

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Programmers Register Set

R0 R1 R2 R3 R4 : : RN
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Operations
ADD, AND, SUB, AND, OR, XOR BZ Branch if zero bit set LOAD Second operand source and RX destination STORE POP - Post increment with register indirect only PUSH- Pre decrement with register indirect only TEST
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Execution Unit
IRE Internal A Bus IRF

DO

A0

PC

T2

R0

RN

T2

ALU

DI Internal B Bus

Ext add bus

Ext data bus

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Making a flow chart

- Register transfer notation is used to describe the operation of the execution unit
- Each statement in this notation is called a task (notation has s source-bus-destination) - Each state comprises of one or more tasks. - Use rectangles for states ( In a micro coded implementation each state becomes a control word and a control word sequence is succession of states)

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ADD RX AR RY ( Register- Register)

RR ADD

rx a alu ry b alu
Time

t1 b ry

Parallel tasks are listed in alphabetical order In a micro coded implementation each state is one micro cycle
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ADD RX AI (RY) ( Register- Memory)

RM ADD

edb di ry b ao

di b alu rx a alu

Time

ry b ao t1 a do

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Flow charts till now does not show PC incrementing and Instruction fetch

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edb irf pc b ao rx a alu ry b alu

Pre fetch of next instruction

Current instruction execution

t1 b ry
pc a alu +1 alu

PC Incrementing

t1 b pc

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In a microcoded controller the control word specifies the tasks in a single state Tasks are commands to external bus controller, the execution unit and state sequencer Flowcharts usually emphasize changes in sequence and concurrency for whatever the controller is doing Flowcharts show sequential state flow made up of concurrent tasks Shows address calculation sequences and operation sequences.
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RM

ADD

edb irf pc b ao
edb di ry b ao di b alu rx a alu ry b ao t1 a do pc a alu +1 alu t1 b pc

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Rules of Operation
-A transfer from source to bus to destination takes one state time -A source can drive upto three destination loads. For ex: the task T1 B ALU, AO, PC has three destination loads -Input to ALU are from the A (internal) bus and either K (values 0, +1, -1) or the B bus -When ALU is destination T1 automatically loaded from the ALU output at the end of state time -A transfer to AO bus activates on-chip external bus controller.
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Level 1 flowcharts

Separate an instructions execution into operation tasks and house keeping tasks.

Operation tasks are required to perform an instruction unique to particular instruction

House keeping tasks, such as PC increment, next instruction fetch are common to all instructions.

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ADD RX AR RY
RR ADD edb irf pc b ao pc a alu +1 alu

rx a alu ry b alu

t1 b ry

irf ire t1 b pc House keeping tasks

Operation tasks

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ADD RX AI (RY) RM edb di ry b ao di b alu rx a alu ry b ao t1 a do Operation tasks ADD edb irf pc b ao pc a alu +1 alu

irf ire t1 b pc
House keeping tasks

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Level 2 Flowcharts

Housekeeping tasks merged with the operation tasks to form level 2 flowcharts.

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RR
rx a alu ry b alu

ADD

edb irf pc a alu, ao t1 b ry +1 alu irf ire t1 b pc

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RM

ADD

edb irf pc a alu, ao +1 alu edb di ry b ao, t2 t1 a pc di b alu rx a alu irf ire t1 a do t2 b ao

In the register to register ADD example, if AO had not been accessible from A bus feedback on the EU

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Feedback on controller design doing flowcharts for entire instruction set - 20 address mode sequences - 50 instruction types - 8 states per instruction 50 * 20 * 8 - size.
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Divide the sequence into address mode sequence ( calculates address mode ) Execution sequence ( completes the instruction ) Share the address mode sequence Pay for time

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Register Indirect edb di ry b ao , t2

Base plus displacement edb di pc a alu , ao +1 alu t1 a pc

di b alu ry a alu
edb di t1 b ao, t2

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At the beginning of instruction execution, IRE is assumed to contain the current instruction. It must be loaded by the previous instruction, each instructions control word sequence fetch the next instruction.
Instruction execution begins with address mode sequence and implicitly branches into execution sequence

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ADD rx a alu ry b alu edb irf pc a alu, ao +1 alu irf ire t1 a pc SUB rx a alu ry b alu edb irf pc a alu, ao +1 alu irf ire t1 a pc
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t1 a ry

EXECUTION SEQUENCE FOR REG-REG OPERATIONS

t1 a ry

Execution sequence for standard dual operand instructions ( ADD, AND, SUB ) are identical except for the (implied) ALU function.
They can use a common execution sequence if the opcode directly specifies the ALU operation

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ADD, AND, SUB

rx a alu ry b alu edb irf pc a alu , ao t1 b ry +1 alu

irf ire t1 b pc
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ADD
di b alu rx a alu t1 a do t2 b ao edb irf pc a alu, ao +1 alu irf ire t1 b pc AND edb irf pc a alu, ao +1 alu irf ire t1 a pc
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di b alu rx a alu
t1 a do t2 b ao

EXECUTION SEQUENCE WITH MEMORY OPERANDS

ADD, AND, SUB di b alu rx a alu t1 a do t2 b ao

edb irf pc a alu , ao +1 alu

irf ire t1 b pc
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LOAD ry a alu, rx edb irf pc a alu, ao 0 alu +1 alu irf ire t1 a pc STORE EXECUTION SEQUENCE FOR REG-REG OPERATIONS

rx a alu, ry edb irf pc a alu, ao 0 alu +1 alu irf ire t1 a pc

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LOAD

edb irf pc a alu , ao ry b rx, t2 +1 alu irf ire t1 b pc t2 a alu 0 alu

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STORE

edb irf pc a alu , ao rx b ry, t2 +1 alu

irf ire t1 b pc t2 a alu 0 alu

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LOAD di b rx, t2 edb irf pc a alu, ao +1 alu irf ire t1 a pc EXECUTION SEQUENCE WITH MEMORY OPERANDS

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LOAD

di b rx, t2 edb irf pc a alu , ao +1 alu

irf ire t1 b pc t2 a alu 0 alu

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STORE
rx a alu, do t2 b ao 0 alu

edb irf pc a alu , ao +1 alu

irf ire t1 b pc

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POP edb di edb irf ry a alu,ao pc a alu, ao +1 alu +1 alu di b rx t1 a ry irf ire t1 a pc

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PUSH ry a alu -1 alu rx a do t1 b ao,ry edb irf pc a alu, ao +1 alu irf ire t1 a pc

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POP edb di ry a alu , ao +1 alu

di b rx t1 a ry edb irf pc a alu , ao +1 alu irf ire

t1 b pc
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PUSH ry a alu -1 alu rx a do t1 b ao, ry edb irf pc a alu , ao +1 alu irf ire t1 b pc
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Branch Instruction
edb irf ry a alu,ao +1 alu Z =1 (branch) Z =0 (no branch) edb irf pc a alu, ao +1 alu irf ire t1 b pc
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irf ire t1 a pc

TEST di b t2 t2 a alu 0 alu edb irf pc a alu, ao +1 alu irf ire t1 b pc EXECUTION SEQUENCE WITH MEMORY OPERANDS

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