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(1)
H s K
p
K
i
s
( ) + (2)
H z
K
i
T
K
p
K
i
T
K
p
z
z
( )
+ +
1
]
1
1
]
1
_
,
2 2
1
1
1
(3)
Although a PLL using the PI algorithm for the loop filter
guarantees zero steady state error for a step input change, its
dynamic behavior can be very different depending upon
choices of integral gain, K
i ,
and the proportional gain, K
p
.
Since the sampling interval, T, is also the measured period,
the value of T used in (3) will change depending upon the
variance in system frequency. This is usually not a problem
because the power system frequency normally changes less
than a tenth of a Hertz and does so at a typical rate on the
order of hundredths of a Hertz per second.
The discrete transfer function expressed in (4) is for the
phase error, T
zce
. This transfer function uses the PI lowpass
filter algorithm expressed by (3) while K
a
and K
b
are defined
by K
i
and K
p
as shown in (5) and (6). (4) has a zero a =0
on the unit circle and two poles which must lie inside the
unit circle to insure PLL stability. Adjusting these poles can
attenuate the the higher frequencies making the control loop
less responsive to fast changes of the frequency of the input
signal as well as making the filter more stable.
T
z c e
z
z K
a
z K
b
+ + +
1
2
2 1 ( ) ( )
(4)
K
K
T
K
a
i
p
+
2
(5)
K
K
T
K
b
i
p
2
(6)
Experimentally, variations in control response are ob-
served by monitoring the phase error, T
zce
, as shown in Fig.
5. These plots agree well with simulation results for the fil-
ter types using MATLAB. The four cases are generated
using the values of K
i
and K
p
shown in Table I with T set to
1/60 s. All four algorithms achieve zero steady state error
for a step change of the frequency on the input signal thus
confirming earlier observations about the PLL using PI al-
gorithm for the loop filter.
TABLE I. Chart of constants used in Fig. 5 simulations.
Type Ki Kp Ka Kb
A 0.0025 0.5 0.8 -0.2
B 0.0012 0.7555 0.9 -0.610
C 0.0006 0.8315 0.9 -0.763
D 0.00006 0.8925 0.9 -0.885
5
-1 0 1 2 3 4
53 Hz
69 Hz
Zero
Crossing
Error - Hz
Filter type "A"
Filter type "B"
Filter type "C"
Filter type "D"
Signal Frequency
Time - seconds
Fig. 5. Four experimental dynamic responses of the phase-locked
loop control system shown in Fig. 3 to a step change of input fre-
quency of 69 to 53 Hz.
A filter with slightly underdamped characteristics simi-
lar to the Type B filter is used for the pre-lock lowpass
filter to obtain phase lock quickly, within 0.5 seconds as
demonstrated by the zero phase error. A similar filter to the
Type D filter, with significantly overdamped characteris-
tics, is used after phase lock because this filter rejects higher
frequencies and has a high degree of momentum. Mathe-
matically, a critically damped response can be achieved us-
ing K
a
= 0.9 and K
b
= -0.6975. As mentioned previously, the
power system will vary by at most 0.1 Hertz from its 60
Hertz nominal value and these variations occur at a rate of
hundredths of Hertz per second or slower. The noise spec-
trum is known to exist at somewhat higher frequencies.
Therefore, a filter of the Type D nature, designed for its
slow response, rejects the noise while retaining sufficient
bandwidth to effectively track the desired system frequency.
(The feedforward aspect of the control loop provides a wide
bandwidth for the commanded period, overcoming what
may appear as a very sluggish control loop response. Feed-
forward also overcomes windup problems.) In other words,
this algorithm takes advantage of known system behavior in
applying appropriate filtering. Hence, frequency measure-
ment noise such as that illustrated in Fig. 3 does little to
change the computed locked period. The mechanism to
achieve the dynamic filter is discussed in Section VII. An
important observation from Table I and Figure 5 is that
lower integral gains result in a slower responding system.
When choosing the PI algorithm constants or even the
order of the lowpass filter algorithm, one must consider the
performance criteria for a given application. This is beyond
the scope of this discussion. The reader is referred to [6] for
additional information. The processing power of the
87C196KD-20 allows implementation of high order lowpass
filter algorithms or limited change-rate algorithms.
VII. PHASE LOCK DETECTOR
When the PLL control system in Fig. 4 has obtained
lock, the Phase error, T
zce
, is nominally zero. A lock detec-
tor is implemented which tracks the sum of squares of the
T
zce
over a finite length window of past values as expressed
by (7). From experimentation, the sum squared term, S
2
, for
a window of 20, is less than 1000 when the system has
achieved phase lock. The pulse generation for the SCR
gates is inhibited unless operating in phase lock. The proc-
essor code to implement thic control will be discussed in
greater detail in Section IX.
S Tzce
i
i n k
i n
2
2
( ) (7)
The lock detection circuit is also used to adjust the pa-
rameters of the PI loop switching from a fast response algo-
rithm before lock is achieved to a slow response algorithm
after becoming locked. During operations, if the lock detec-
tion algorithm indicates a loss of lock, the phase-locked
loop is switched back to the fast response filter algorithm
until lock is acquired again.
VIII. OUTPUT CONTROL
Fig. 6 illustrates the feedforward method to determine
the SCR gate firing times. The closed-loop portion of Fig. 6
is described by (8) and the open-loop portion by (9). Ini-
tially, the zero phase reference, T
ref
, is set to zero phase, T
zcn
,
shown in Fig. 4. T
ref
updates after a delay equal to six times
Pd/6 plus the delay control variable T
D
. T
ref
updates using
the most recent value of Pd computed in the PLL. Hence T
ref
and T
zcn
are both phase-locked to the input signal but are
not necessarily equal: The update timing of T
ref
depends
upon the delay control whereas T
zcn
depends upon the PLL
input signal. The locked period, Pd, computed in the PLL
contains the disturbance rejection information.
To obtain command tracking as a separate matter, the
firing times are computed according to (9). The variable, K,
serves as the HSO output pin sequence table pointer as well
as the multiplier for Pd/6 in (9). K is incremented each
Pd/6 period from zero to five.
T
ref
n
T
ref
n
Pd
+
+
1
(8)
T
HSO
K
T
ref
n
K
Pd
T
D
+ +
6
(9)
6
T
Pd
HSO
T
HSO
T
HSO
T
HSO
T
HSO
T
HSO
T
1 2 3 4 5 6
Tref
n
Pd/6
Pd/6
Pd/6
Pd/6
Pd/6 1/z
D
Fig. 6. Control diagram for SCR firing timing.
IX. PROCESSOR SOFTWARE
The 87C196KD processor operates in one of three rou-
tines: A main routine containing the processor default code
and two real-time interrupts routines shown in Fig. 7 and
Fig. 8. Upon power up, the code begins execution by setting
all initial conditions and allocating the various microproces-
sor resources for this particular application.
Clear Start Flag
Start HSO
from ISR
Return
Save
Event
Time
Tzcm
S<=Limit?
Yes
No
No
Start Flag
Set?
Reset
Run & Lock
Flags
Set Tref=Tzc
Phase Control
S,
Tzc, Pd,
Pd/6
Compute filtered
and
from PLL
algorithm
Compute
zero crossing
time -
Compute
sum squared,
of
Event?
Capture
time
HSI ISR
pos. on
neg. on
Yes
from ISR
Return
Fig. 7. High speed input interrupt service routine flow diagram.
Two HSI interrupts are generated per cycle of the power
system voltage and processed to determine the measured
zero crossing as explained in IV. After the second, or Posi-
tive-on, generated interrupt, the measured zero crossing
time, T
zcm,
is calculated, becoming an input to the the phase
filtering algorithm, explained in V and VI. Three variables
set by this routine for use in the high speed output interrupt
service routine are as follows: the zero phase time T
zc
, the
period of the locked frequency Pd, and the period of a signal
corresponding to six times the locked frequency Pd/6. At
the expense of a few more optoisolators, the sampling inter-
val could be defined as one-sixth of a period, with an atten-
dant improvement in command tracking. This improvement
comes at the additional expense of a sixfold increase in
computation burden which is still within the microcontrol-
ler's capability as demonstrated in Section X of this paper.
Other methods for dividing the period are discussed in [23].
During the HSO interrupt service routine shown in Fig.
8, the processor determines which outputs are to be set high
during the next sixth of the cycle by retrieving data from two
gate firing sequence tables. Three timed events are sched-
uled during the output interrupt service routine: the first
two events pulse two of the six gate signals high and specify
at what time the events occur. The third event, an arbitrary
fixed delay after the first two events, resets all HSO pins
low. The third event is also programmed to generate the
next HSO interrupt thus making the interrupts self perpetu-
ating while generating gate firing pulses. By disabling HSO
interrupts, this process for generating gate pulses is termi-
nated.
7
Run Flag
None set
Tref, Pd,
T and
Compute HSO pin
from firing table
Determine
HSO pin states
high event times
Flags?
HSO ISR
from
Determine HSO pins
from sequence table
Schedule pin high
and pin low events
Pd/6,
from ISR
Return
from ISR
Return
d,
Fig. 8. High speed output interrupt service routine flow diagram.
Only when a signal from the operator first initiates the
generation of the gate firing pulses, the actual zero crossing
time, T
zc
, is copied into the gate firing reference variable,
T
ref
which subsequently stays synchronized with the actual
zero crossing by using the periods, Pd and Pd/6, computed
in the HSI interrupt service routine. Although (8) specifies
that T
ref
is incremented by Pd, the actual time when this
update occurs may shift forward and back in relation to the
corresponding actual zero crossing by the amount specified
by the operator for T
D
, the delay time. Hence, for a negative
delay time T
D
, T
ref
will update before T
zc
. Thus it is neces-
sary to maintain two zero crossing time references, T
zc
for
the PI algorithm and T
ref
for scheduling the gate firing
pulses.
X. OPERATIONS
Fig. 9 shows the six experimental outputs to the SCR
gates for a zero phase delay. The pulse widths are exagger-
ated for illustrative purposes and are programmable in proc-
essor code. The second firing pulse overcomes discontinuous
conduction, for example, at startup, and is ordinarily deleted
in continuous conduction. The range of delay is zero to 52.4
ms or from zero to over 1000 degrees for 60 Hz nominal
input. The upper restriction is imposed by the crystal fre-
quency used with the 87C196KD processor and the 16 bit
timer used to schedule output events. Since the delay is in-
corporated on a feedforward command outside the PLL algo-
rithm, there are no restrictions on the size of step in phase
delay. The advantage of a feedforward command for delay
is its improved tracking performance: Any change in the
desired firing angle is implemented in its entirety at the very
next instant that a new command is applied without affect-
ing the disturbance rejection of the PLL.
The waveforms generated by experimental data shown
in Fig. 9 are independent of frequency within the range of
40 to 70 Hz. No changes in code or hardware are required
to operate on a 50 Hz power system. There is sufficient
dynamic range in the mathematics of the PLL algorithm to
accommodate the period offset to 50 Hz without loss of per-
formance.
-20 -10 0 10 20 30
Time - ms
S3
S2
S1
S4
S5
S6
A
B
C
Gate
Pulses
Input
Voltage
Fig. 9. Experimental results of HSO outputs to the SCR gate con-
trols for a zero degree phase delay. Dual pulses are for illustration
purposes.
The execution time for the HSI interrupt service routine
is less than 40 s and the execution time for the HSO inter-
rupt service routine is 18 s. This represent a 0.34% utiliza-
tion. Fixed point math was used in the control algorithms
with 32 bit precision. The program required 650 bytes of
the possible 32K bytes of internal ROM and 75 bytes of the
possible 2K bytes of internal RAM. None of the 8 analog
input channels were used as well as numerous other re-
sources provided by the 87C196KD processor. In other
words, there remains a great deal of opportunity for incorpo-
rating sophisticated outer control loops using the same proc-
essor.
XI. CONCLUSION
An embedded microcontroller produces a minimal parts
implementation of a Phase Controlled Rectifier with phase-
locked loop-based generation of gate signals. Two inexpen-
sive optoisolators used for the phase detector reduce instru-
mentation requirements. Innovative analog and digital sig-
nal processing improve the accuracy of the zero crossing
time. Dynamic digital phase-locked loop characteristics
provide improved capture and lock performance. A feed-
forward method separates disturbance rejection from com-
8
mand tracking: Rapid, accurate response to commands oc-
curs while rejecting a wide range of disturbances, including
disturbances both faster and slower than the command. The
flexibility and simplicity of the processor based design
makes this converter extremely efficient and reliable. The
processors capabilities will permit expansion of the control
algorithms to include, for example, protective algorithms,
closed loop constant voltage control, or closed loop constant
current output control.
XII. BIOGRAPHY
Richard W. Wall born 1946 received his BSEE from the
Pennsylvania State University (68) and MEEE and PhD EE
from the University of Idaho(80, 89). He worked for Idaho
Power Co. for 18 years in the communications, protective
relaying and R&D departments before joining the University
of Idaho Department of Electrical Engineering. He teaches
Embedded Microcontrollers and Senior Design. His re-
search interests include protective relaying and networked
distributed control.
Herbert L. Hess received his BS from the US Military Acad-
emy ('77), MS from the Massachusetts Institute of Technol-
ogy ('82), and PhD from the University of Wisconsin-
Madison ('93), where he held a Hertz Fellowship. He served
on the faculty of the US Military Academy from 83-88. In
93, he joined the University of Idaho, where he is an Assis-
tant Professor of Electrical Engineering. His research inter-
ests include analysis, design, and control of electric ma-
chines, drive systems, and power converters and their effects
on the quality of electric power.
XIII. ACKNOWLEDGMENT
This research was supported in part by a grant from Univer-
sity of Idaho Instructional Media Services entitled "Power
Electronic Converters for Hands-on Investigation in the
Classroom."
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9
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