2 bit Asynchronous (ripple) Counter: and Circuit diagram J CL K 1 Q

Explain Asynchronous Counter

QA
J Q

QB

K
Q

K
Q

Truth table illustrating state of flipflops for counters. QB QA

Block Diagram of 2-bit Asynchronous Counter

No. of input pulses

CL K

QA(LS B) QB(MSB )

3 bit Asynchronous (ripple) Counter: Counter and Circuit

Explain Asynchronous

CL K

QC

QB

QA

diagram and Truth table illustrating state of flipflops for counters (Do yourself) QB QC QA J Q J Q J Q CL K 1 CL K

K
Q

K
Q

K
Q

Block Diagram of 3-bit Asynchronous Counter

QA(LS B)

QB

QC(MSB )

4 bit Asynchronous (ripple) Counter: Explain Asynchronous Counter and Circuit diagram and Truth table illustrating state of flipflops for counters (Do yourself)(CLK QD QC QB QA) J CL K 1 Block Diagram of 4-bit Asynchronous Counter CL K Q

QA

QB

QC

QD

K
Q

K
Q

K
Q

K
Q

QA(LS B) QB

QC

QD(MS B)
THESE ALL ARE UP COUNTERS AS THEY COUNT IN INCREASING ORDER OR ADVANCES UPWARD THROUGH ITS SEQUENCE (0,1,2,3,4,5,6,7,..) NOW IN DOWN COUNTERS:

2 bit Asynchronous (ripple) Counter: (down) Explain Asynchronous Counter and Circuit diagram and truth table illustrating state of flipflops CL QB QA for counters is ---------K QA QB J Q J Q CL K 1 CL K

K
Q

K
Q

Block Diagram of 2-bit Asynchronous Counter

QA(LS B) QB(MSB )

3 bit Asynchronous (ripple) Counter: (Down) Explain Asynchronous Counter and Circuit diagram and Truth table illustrating state of flipflops for CL QC QB counters (Do yourself) Q Q K J Q

QA

QA

CL K 1

K
Q

K
Q

K
Q

Block Diagram of 3-bit Asynchronous Counter CL K

QA(LS B)

QB

QC(MSB )
4 bit Asynchronous down counter (do yourself) DIVIDE BY N COUNTER OR MODULO COUNTER OR MOD-N COUNTER (ASYNCHRONOUS) (N------BASE) MOD-3 Counter: Explain Asynchronous J Counter and Circuit diagram and Truth tableQ illustrating state of No. of clk flipflops for counters. QA QB J Q pulses CL K 1 Block Diagram of DIVIDE BY 3 Counter Here we use feedback NAND gate to fed in clear (asynchronous) input in parallels to all flip-flops such that at the count of 3, all flip-flops are reset to zero. Flip-flops required=(2n>N) ie.(2n>3) so n=2 K K
Q Q
CL R

QB

QA

CL R

CL K

QA(LS B) QB(MSB )

MOD-10 Counter or Asynchronous Decade Counter: Explain Asynchronous Counter and Circuit diagram and Truth table illustrating state of flipflops for counters. (Do yourself)(CLK QD QC QB QA)

J CL K 1

QA

QB

QC

QD

K
Q

CL R

K
Q

CL R

K
Q

CL R

K
Q

CL R

Block Diagram of Asynchronous Divide By 10 Counter Here we use feedback NAND gate to fed in clear (asynchronous) input in parallels to all flip-flops such that at the count of 10, all flip-flops are reset to zero. Flip-flops required=(2n>N) ie.(2n>10) so n=4

CL K

QA(LS B) QB

QC

QD(MS B)
MOD-7 counter has 3 flipflops..do MOD-5 counter has 3 flipflopsdo Down counter for Modulo counters (MOD-10, MOD-7) How many flip-flops are required to construct MOD-60 counter? Design Divide by 20 counter. CL K QD QC QB QA

How many flip-flops are required to construct Divide by 5 counter?

Up/Down Counter: An up/down counter is one that is capable of progressing in either direction through a certain sequence. Also called Bidirectional counter, and can have any specified sequence of states. 2 bit Up/Down Asynchronous Counter: Explain Asynchronous Up/Down Counter and Circuit diagram and Truth table illustrating state of flipflops for counters. (Do yourself)(CLK QB QA)

QA

J
UP/ DOWN

QB

CL K 1

CL K

UP/DOW N

QB

QA

K
Q

K
Q

Block Diagram of 2 bit Up/Down Asynchronous Counter

1 UP/ DOWN CL K

QA

QA(LS B)

QB(MSB )

4 bit Up/Down Asynchronous Counter: : Explain Asynchronous Up/Down Counter and Circuit diagram and Truth table illustrating state of flipflops for counters. (Do yourself)(CLK QD QC QB QA)

UP/ DOWN

CL K

J QA

J QB

J QC

J QD

K 1
Q

K
Q

K
Q

K
Q

UP/ DOWN

CL K

QA

QB QC

QA(LS B) QB

QC
Draw truth table in accordance to above waveform and Do practice for 3 bit, Decade (MOD-10) Up/down counter. 2 bit Synchronous Counter: Explain Synchronous Counter and Circuit diagram and truth table illustrating state of flipflops for No. of input QB QA counters. QA QB pulses J Q J Q 1 K
Q

QD(MS B)

K Block Diagram of 2-bit

Q

CL CL K K

Synchronous Counter

QA(LS B) QB(MSB )

3 bit Synchronous Counter: Circuit

Explain Synchronous Counter and

CL K

QC

QB

QA

diagram and Truth table illustrating state of flipflops for counters (Do yourself) QB QC J Q QA J Q J Q 1 K CL CL K K
Q

K
Q

K
Q

Block Diagram of 3-bit Synchronous Counter

QA(LS B)

QB

QC(MSB )

4 bit Synchronous Counter: Explain Synchronous Counter and Circuit diagram and Truth table illustrating state of flipflops for counters (Do yourself)(CLK QD QC QB QA) 1 J Q

QA

QB

QC

Q QD

K CL K CL K
Q

K
Q

K
Q

K
Q

Block Diagram of 4-bit Synchronous Counter

QA(LS B) QB

QC

QD(MS B)
THESE ALL ARE UP COUNTERS AS THEY COUNT IN INCREASING ORDER OR ADVANCES UPWARD THROUGH ITS SEQUENCE (0,1,2,3,4,5,6,7,..) NOW IN DOWN COUNTERS:

2 bit Synchronous Counter: (down) Explain Synchronous Counter and Circuit diagram and truth table illustrating state of flipflops for CL QB QA counters is ---------QA QB K J Q J Q 1 K CL K
Q

K
Q

CL K

Block Diagram of 2-bit Synchronous Counter

QA QA(LS B) QB(MSB )

3 bit Synchronous Counter: (DOWN) Explain Synchronous Counter and Circuit diagram and Truth table illustrating state of flipflops for counters (Do CL QC QB yourself) K QB QC J Q QA J Q J Q 1 K
Q

QA

K
Q

K
Q

CL K CL K

Block Diagram of 3-bit Synchronous Counter

QA

QB

QA(LS B) QB

QC(MS B)

2 bit and 4 bit Synchronous down counter (do yourself) UP/DOWN Synchronous Counter: 2 bit and 3 bit do yourself.

4 bit Up/Down Synchronous Counter: : Explain Synchronous Up/Down Counter and Circuit diagram and Truth table illustrating state of flipflops for counters. (Do yourself)(CLK QD QC QB QA)

1
UP/ DOWN

QA

QB

QC

QD

K
Q

K
Q

K
Q

K
Q

CL K

UP/ DOWN

CL K

QA QB QC QA(LS B) QB

QC

QD(MS B)

Synchronous Decade Counter or MOD-10 Counter: Explain Synchronous Counter and Circuit diagram and Truth table illustrating state of flipflops for counters. (Do yourself)(CLK Q3 Q2 Q1 Q0)

J0

Q0

J1

Q1

J2

Q2

J3

Q Q 3

K0 CL K
Q

K1
Q

K2
Q

K3
Q

Q3

Block Diagram of Synchronous Decade Counter CL K

Q0(LS B) Q1

Q2

Q3(MSB )
CL K Q3 Q2 Q1 Q0