An Efficient All-Digital Phase-Locked Loop with Input Fault Detection

Tin-Yam Yau, Tri Caohuu and Jeonghee Kim Department of Electrical Engineering San Jos State University, San Jos, CA, U.S.A. Abstract An all-digital phase-locked loop (ADPLL) having a fault detection of the input reference signal was modeled in Verilog hardware descriptive language (HDL) and is presented in this paper. The design can track an input signal with frequency ranging from 61kHz to 43MHz in a maximum locked-in time of five reference cycles. In the case of loss of input reference, it can continue to generate an output signal with the previously stored parameters and report the anomaly as status. The functional and timing requirements of the design were verified using Synopsys electronic design automation (EDA) tools. The ADPLL can be utilized as an intellectual property (IP) core to reduce the development time of an application-specified integrated circuit (ASIC) product. The input fault monitoring capability can provide operational feedback that improves the overall system reliability. Keywords Phase-locked loop, ASIC, HDL, fault detection. 1. Introduction With the recent emergence of systemon-a-chip (SoC), great emphasis has been placed on maximizing speed and functionality while minimizing power consumption and production cost of an ASIC chip [1]. Composed of only digital elements such as combinational logic and flip-flops, an ADPLL is both portable and
Input Fault Detector reference lead lag status active count load sync clock

reusable across different designs and semiconductor technologies [2]. It also facilitates the benefit of system simulation at a high hierarchy level during the debug phase [3]. These factors decrease the overall ASIC time-tomarket, because the ADPLL can be easily integrated into any design as an IP core. Latest works in the advancement of ADPLL primarily focus on achieving lower output jitter and faster lock-in acquisition for high speed applications. Following reference [3] as guidance, the structure of the ADPLL is divided into five building blocks, as shown in Figure 1. Phase-frequency detector (PFD) determines the differences in frequency and phase between the input reference signal and the output signal. Digitally-controlled oscillator (DCO) acts as the built-in high speed system clock. Input fault detector observes for irregularity on the input signal. Controller provides instruction on how to recreate the resulting waveform. Frequency divider constructs the output with the proper frequency by dividing down the DCO clock. In this project, a fully operational ADPLL that can be incorporated into an ASIC design was modeled with Verilog HDL and synthesized into circuit using standard cell library available from any EDA tools. It achieved faster lock-in speed than reference [3] by utilizing a direct approach in acquiring a lock. It also features a monitoring process capable of detecting an input failure and registering the condition as error.

PFD

Controller

Freqeuncy Divider

output

start select

DCO

Figure 1. Block diagram of ADPLL.

978-1-4244-9224-4/11/$26.00 2011 IEEE

The following sections 2 to 6 elaborate on the details of each major component. Section 7 presents the results from the synthesis and waveform simulation. The performance of the ADPLL is compared to the designs from other literatures in section 8. Lastly, section 9 summarizes the benefits of the proposed design. 2. Phase-Frequency Detector If the input reference deviates in frequency, the ADPLL needs to know so that it can adjust its output accordingly. The PFD spots this variation and perceives the change as whether the rising edge of the reference signal is ahead or behind the rising edge of the output. A schematic of the PFD is depicted in Figure 2 [3],[4],[5].
Vdd D Q CLR lead

3. Digitally-Controlled Oscillator The most important component of the ADPLL is the DCO, which functions as the local oscillator supplying internal timing for all the synchronous circuits. A block diagram of the schematic is shown in Figure 3. The ring oscillator output fosc is configurable by manipulating the numeric value of de_sel, which controls the length of time before fosc can switch state. The start signal acts as an active low reset to the entire DCO circuitry and serves as a mean to shut off the DCO. The output of the oscillator is forwarded to a series of clock dividers. Multiplexer offers the DCO clock the options between fosc, fosc/2, fosc/4, or fosc/8 [3].
Ring Oscillator fosc fosc/2 start de_sel

ref_clk

Vdd CLR D Q out_clk lag

fdco 2 fosc/4

fosc/8

Figure 2. Schematic of PFD. At the start-up condition, both lead and lag remain logic high. A rising edge on ref_clk while out_clk is low causes lead to become low and lag to stay high. A subsequent rising edge on out_clk resets both flip-flops and triggers lead to return to high. The period of time in which lead is low represents how much ref_clk is leading out_clk in phase. In contrast, a rising edge on out_clk when ref_clk is low prompts lag to become low and lead to stay high. The lag signal is restored to high when the next rising edge of ref_clk arrives. The length of a logic low lag corresponds to the duration in which ref_clk lags out_clk in phase. The circuit measures the time difference between each input-output rising edge pair by ensuring that only one of the lead and lag signals is active at any time within a period of either the input or output signal.

Figure 3. Block diagram of DCO. The ring oscillator section of the DCO takes advantage of the propagation delay of combinational logic gates when their outputs swing from logic low to high or high to low due to an input change. Multiple delay elements are cascaded together to form a configuration allowing multiple selections of frequency depending on the number of active delay elements. The schematic of this formation is illustrated in Figure 4 [3],[6]. The oscillation frequency of fosc can be determined by the following formula.

f osc =

1 2[(de _ sel t de ) + t NAND ]

freq_sel

(1)

start

de_fb de_sel[14] de_sel[15]

fosc

de_sel[0]

de_out[0]

de_out[14]

de_out[15]

Figure 4. Schematic of ring oscillator. tde represents the time for a signal to propagate through one delay element, and tNAND is the propagation delay of the NAND gate. In order to produce a DCO clock with 50% duty cycle, no more than one delay element should be activated at a time by restricting the value of de_sel to the power of 2. 4. Input Fault Detector One unique attribute of the ADPLL in this project is its ability to check for input failure in the case of loss of signal. When an error is discovered, the controller is notified and the frequency divider is instructed to continue to produce the output waveform with the last known good characteristics. Meanwhile, status bits are generated to communicate detailed information about the fault situation, such as whether the input signal is stuck at logic high or at low. The input fault detector operates on two separate binary counters. One counter aggressively attempts to set the error flag while the other tries to clear it. The DCO counter is clocked by the DCO clock and sets the flag when its count attains maximum value. It also examines the polarity of the reference input when the failure is uncovered. The reference counter is clocked by the input signal and resets the error flag when its count reaches maximum value. The idea is that the flag will never be activated as long as the input remains operational, because the reference counter keeps clearing the flag before the DCO counter has a chance to change it. When the DCO counter measures an irregular length of an idling input, it stores the logic state of the faulty input signal. If the signal is still not working by the next count, the condition is reported as error status. Figure 5 demonstrates the timing of the process.

dco_clk dco_cnt ref_clk chk_ref fault_los[1] ref_hi

M-1 M M+1

Figure 5. Timing diagram of fault detector. 5. Controller The responsibility of handling all the information regarding the reference signal provided by the PFD and the input fault detector resides in the controller. Equipped with the values on the amount of frequency and phase variations, it constructs and conveys commands to the frequency divider on how to formulate the output waveform. In the case of loss of input signal, it also halts the update of data to the frequency divider in prevention of using the characteristics of a faulty input as reference.

delay element

The controller takes a very direct approach in determining whether to increase or decrease the output frequency. It quantizes the period of the input reference as a number of DCO clock cycles [3]. A finite-state machine computes the length of each reference period by monitoring the rising and falling transitions of the input. As a result, a final count value representing the period length of the input is calculated for each reference cycle. The state machine is consisted of three states, which are START, REF_HI, and REF_LO. Its state transition flow chart is displayed in Figure 6. A frequency range detector is also embedded within the state machine. It ensures that any input frequency outside the tracking range of the ADPLL is ignored, because the state machine counter has a fixed bit resolution. The controller also supplies a sync signal to the frequency divider for aligning the output to the input reference. It acts as a restart indicator to the frequency divider in effort to remove any phase artifact between the input and output waveforms.

If the measured reference period is too short or too long, the frequency divider has difficulty duplicating the waveform because the parameter exceeds beyond its capability. A modification is applied to the state machine to include a frequency range detector. As the counter is incrementing during the REF_HI or REF_LO state, a flag is set if the counter result is less than the minimum limit or the maximum count value is realized. When it is time to update the final sum at the next rising edge of the reference signal, an inactive flag means that the number is valid for the frequency divider to use. Any amount outside the constraint boundary causes the out-of-range flag to become true and the output of the ADPLL to revert back to the previous frequency before the condition is violated. 6. Frequency Divider Receiving a set of commands from the controller, the frequency divider reconstructs an output that resembles a time-quantized version of the input signal. The register obtains the count value when the load signal indicates that the data is ready. Using the DCO clock as the timing source, the frequency divider creates an output according to the maximum count attained. It initially begins counting down by subtracting 2 from the number. When the number reaches zero, it switches the polarity of its output. It then initiates the count up procedure by adding 2 to the number. When the sum reaches the maximum count value, it again swaps its output polarity. The two-step method repeats indefinitely and permits the creation of an output waveform with a 50% duty cycle. When the sync signal emerges, the frequency divider defaults its output to logic high, reloads its local counter, and proceeds to the step of counting down [3]. Figure 7 presents the transition diagram portraying the technique.

START

ref_clk rise? Y R_HI REF_L

Max cnt? N Increment cnt

ref_clk rise? Y Save cnt Reset cnt N Max cnt? N Increment cnt

ref_clk fall? Y

Figure 6. Transition diagram of state machine.

A sync? Y Count down cnt = max_cnt Y A DCO N

Table 2. ADPLL circuit specifications.

Lock-in frequency range DCO frequency range Acqusition time Input fault detection time Input out-of-range detection time 0.061 43MHz 16 262MHz 5 ref cycles > 256 DCO cycles > 1 ref cycles

Count down? Y N cnt = 0? Y Invert output Count up Output high cnt - 2 A

Count up? Y N
cnt = max_cnt?

Three bits are responsible for communicating the occurrence of a failure on the input signal. Table 3 explains the meaning of each fault code. Bit 2 stands for the error bit, and it becomes true whenever a fault happens. Bit 1 is the out-of-range bit. Bit 0 represents the stuck bit, and its logic level corresponds to the polarity at which the input is stuck. Table3. Input fault error code.
Bit 2 0 0 0 0 1 1 1 1 fault_status Bit 1 Bit 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Description No error No error No error No error Loss of signal, stuck low Loss of signal, stuck high Out of range Not applicable

Y Invert output Count down Output low cnt + 2 A

Figure 7. Transition diagram of frequency divider. 7. Simulation Result Synopsys Design Vision was used to translate the ADPLL model into an actual hardware circuit. The design compiler optimized the circuit to meet the timing requirements specified by the Toshiba TC240C cell library. Major performance aspects of the ADPLL, including slack time, area, and power, were evaluated using Synopsys Design Vision [7]. An outline of the assessment is provided in Table 1. With the synthesized ADPLL described in Verilog HDL, post-synthesis waveform timing analysis is feasible using real gate delays from the TC240C library. A summary of the specifications derived from the emulated waveforms is presented in Table 2. Table 1. Design Vision performance measurements.
Process technology Operating voltage Smallest slack time Total cell area Total area Total dynamic power 0.25m 2.5V 0ns 1177.5 2809.369m2 13.48mW

Figure 8(a) and (b) demonstrate when the loss of signal transpires and the input is stuck at either logic low or high, respectively. Figure 9(a) and (b) illustrate the situations in which the reference signal is outside of the acquisition range of the ADPLL. In all scenarios, the ADPLL output resumes at the previously recorded frequency when the conditions are detected.
(a)

(b)

Figure 8. Input reference stuck at (a) logic low and (b) logic high.

(a)

cases, status bits reported the fault condition and conveyed detailed information about the error.

(b)

Figure 10. Tacking ability of ADPLL. Figure 9. Input reference beyond (a) smallest lock-in limit and (b) largest lock-in limit. 8. Result Analysis Even though the complementary metal oxide semiconductor (CMOS) process technology employed in this project was not as advanced comparing to those used in recent publications, the ADPLL has a remarkable acquisition speed at least twice as fast, as shown in Table 4. With its straightforward scheme of quantifying the reference period, it effectively replicates each cycle of the waveform after the measurement is made without much delay. However, the biggest drawback of the ADPLL is its power dissipation. The power calculation resulted in 13.48mW with an operating voltage of 2.5V, while the design in [3] consumed only 1.98mW running at 1V. Table 4. Comparison of acquisition time.
Ref Freq (MHz) 800 200 0.12 43 52 Lock Time (Ref Cycle) 10 14 12 5 30

The ADPLL is highly versatile because it was fully developed in Verilog HDL. Its attributes can be modified during the design phase to meet any timing specification and to adapt to any target technology. The bit resolution of the controller and frequency divider modules affects the frequency range of the circuit. The amount of delay elements involved in the DCO directly relates to the jitter performance and the speed of the CMOS technology. Because of its portability and programmability, an ADPLL IP core can shorten the overall development cycle; therefore, making it an ideal solution to satisfy the timing requirement of an ASIC product. References [1] R. Reis, M. Lubaszewski, and J. A. Jess, Design of Systems on a Chip: Design and Test. Dordrecht: Springer, 2006. [2] R. E. Best, Phase-Locked Loops: Design, Simulation, and Applications, 5th ed. New York: McGraw-Hill, 2003. [3] S. Moorthi, D. Meganathan, D. Janarthanan, P. Kumar, and J. Perinbam, Low Jitter ADPLL based Clock Generator for High Speed SoC Applications, World Academy of Science, Engineering and Technology, vol. 42, pp. 632-636, 2008. [4] D. Sheng, C. Chung, and C. Lee, An AllDigital Phase-Locked Loop with High Resolution for SoC Applications, VLSI Design, Automation and Test, 2006 International Symposium, pp. 1-4, April 2006. [5] E. Mokhtari and M. Sawan, CMOS HighResolution All-Digital Phase-Locked Loop, Micro-NanoMechatronics and Human Science, 2003 IEEE International Symposium, vol. 1, pp. 221-224, December 2003. [6] R. Stefo, J. Schreiter, J. Schlussler, and R. Schuffny, High Resolution ADPLL Frequency Synthesizer for FPGA- and ASIC-based Applications, FieldProgrammable Technology (FPT), 2003

[8] (CMOS 32nm) [3] (CMOS 90nm) [9] (CMOS 180nm) Project (CMOS 250nm) [6] (CMOS 350nm)

9. Conclusion In this project, an ADPLL with input fault detection ability was fully modeled and synthesized using the Toshiba TC240C 0.25m CMOS technology. The design demonstrated through simulation the proficiency to acquire a lock onto an input signal with frequency varying from 61kHz to 43MHz in merely five cycles, as shown in Figure 10. When the input was at fault, it automatically resumed output formation by employing the last known correct parameters. When the input drifted beyond its acquisition range, its output also by design swapped back to the previously established frequency. In both

IEEE International Conference, pp. 28-34, December 2003. [7] Design Compiler User Guide, March, 2003. [Online]. Available: https://www.toshiba.com/taec/components/ Generic/asic_design/ndm1_15a/Synopsys/D CUG.pdf. [Accessed: September 15, 2010]. [8] J. Zhao and Y. Kim, A Novel All-Digital Phase-Locked Loop With Ultra Fast Frequency and Phase Acquisition, 2009 IEEE International Midwest Symposium on Circuits and Systems, pp. 487-490, August 2009. [9] C. Zhang, Y. Li, H. Li, Q. Wang, and Y. Peng, The Implementation and Analysis of a New Self-Sampling PI Control All Digital Phase-Locked Loop, Machine Learning and Cybernetics, 2006 International Conference, pp. 241-246, August 2006.