Design of a Solar Array Peak Power Tracking System

NASA1 Engineering, Inc.

Chad Alberts Justin Braun Anna Fowler May 1, 2006

Executive Summary
The objective of this project was to develop a working prototype for a solar array peak power tracker. Each solar array is a non-linear device which contains a maximum power point. Tracking this point for a solar array allows for an increase in the reliability of a satellites power supply during the sunlight and the achievement of maximum power in order to charge a back up battery. This battery would to be used as the power source during an eclipse [1]. The basic design of the peak power tracker connected a solar array simulator, DC-DC converter chip, and load simulator in a series connected boost converter (SCBC) design. The converter chip included a trim output option allowing for a variable voltage conversion. This option was controlled by an MCH12 microcontroller. The implemented algorithm compared past and present voltage, current, and conductance values. The input current value was sent to the microcontroller by use of a Hall Effect Current sensor, while the input voltage was sent by way of a voltage divider and also was used to power the microcontroller. The desired outcome of this project was to present a stand-alone digital solution. However, difficulty in writing the program led to a project which would require further work to create a design which could be tested.

Table of Contents
1.0 Introduction 1.1 Problem Identification 1.2 System Specifications 1.3 Operational Description 1.4 Design Deliverables 1.5 Implementation Considerations 2.0 Design Decisions 2.1 Design Configuration 2.2 DC-DC Converter Chip 2.3 Microcontroller 2.4 Algorithm 3.0 System Design 3.1 Hardware Solution 3.2 Software Solution

1 1 1 2 2

5 5 6 7

9 11

4.0 Test Results 4.1 Voltage Sensor_______________________________________13 4.2 Current Sensor 14 15 4.3 Solar Array Simulator 5.0 Project Information 5.1 Gantt Timeline 5.2 Budget 6.0 Conclusions

17 18 19

7.0 References 8.0 Biographical Information Appendices

20 21 22

List of Figures
Figure 1- Basic diagram of solar array peak power tracker Figure 2- Basic SCBC (Series Connected Boost Converter) configuration Figure 3- Basic hardware design Figure 4- Voltage division circuit Figure 5- Hall Effect current sensor Figure 6- Flow chart for microcontroller algorithm Figure 7- Plot of voltage sensor input vs. output Figure 8- Plot of current sensor input vs. output Figure 9- Plot of solar array simulator test results Figure 10- Main tasks for project Figure 11- Gantt timeline for project 2 4 9 10 10 12 14 15 16 17 18

List of Tables
Table 1- Summary of specifications for DC-DC converter chips Table 2- Decision matrix for DC-DC converter chips (3-best, 1-worst) Table 3- Summary for the microcontroller factors Table 4- Decision matrix for microcontroller with values (2-best, 0-worst) Table 5- Design matrix for software implementation method Table 6- Voltage sensor test results Table 7- Current sensor test results Table 8- Estimated project budget 6 6 7 7 8 13 14 18

1.0 Introduction

1.1 Problem Identification

Each satellite in orbit above the Earths atmosphere is powered by a non-linear solar array. A challenge arises since a satellite will travel through intervals of darkness while in the Earths shadow, known as eclipses. A battery is the alternate power source during an eclipse which must be continuously recharged during each period of daylight. The goal of the solar array peak power tracker is to assure that the maximum power is supplied by the solar array to the satellite. After a prototype development, NASA will use this technology to allow for a solar array to power a satellite and charge a battery as much as possible. This would help to ensure that the satellite will be powered during each eclipse period. It is NASAs desire that the design be a stand-alone, digital solution. Other specifications are that the device must maintain a safe current level (approximately 10 amperes), include interfacing with power electronics and sensors, and must be able to be packaged in less than a four square inch board area. NASA also requires that the group use an 8051 microcontroller or a controller with equivalent capabilities, and a Vicor DC-DC converter chip in a series connected boost converter (SCBC) configuration. These specifications were analyzed in the initial stages of the design to assure that they would best meet the needs of this project.

1.2 System Specifications

Digitally controlled solution Include interfacing with power electronics and sensors Maintain required voltage equal to 42 V Sustain optimal voltage for maximum power. This value, or set of values, is based on the solar array simulator capabilities. Maintain safe current level (approximately 10 amps) Use Vicor chip, must be isolated to prevent short circuit

Use 8051 microcontroller, or a microcontroller with equivalent capabilities Can be packaged in less than four square inch board area Low cost

1.3 Operational Description

The basic design for the solar array peak power tracker consists of the solar array, Vicor DC-DC converter connected in a series connected boost converter (SCBC) configuration, the microcontroller, and the load as shown in Figure 1. Voltage and current sensors are also marked in the diagram, and each of these input values will be sent to the microcontroller. Both the solar array and the load are grounded.

Solar Array

VICOR SCBC

Load

Microcontroller Figure 1- Basic diagram of solar array peak power tracker The solar array current is tracked by a Hall Effect current sensor, whose location is denoted by a diamond in the figure above. As the solar array input power varies, the sensor sends the values of the current to the microcontroller. The array output voltage is decreased by a factor using a voltage divider which allows for a voltage level the microcontroller can handle. The algorithm uses the IncCond (Incremental Conductance) method, which will be described later. At this step, an algorithm adjusts the DC-DC conversion using a trim option. The optimal conditions for peak power are based upon the solar array output and are accounted for in the microcontrollers algorithm.

1.4 Design Deliverables

It is the desire of the group to provide NASA with a working prototype that would ultimately be capable of processing voltages and currents to achieve maximum power from a solar array panel to a load. This prototype is desired to be reliable, cost efficient and provide accurate results to

limit power loss. Several pieces of equipment were provided by NASA to produce a prototype: a Vicor chip, solar array simulator, load simulator, and Hall Effect current sensor.

1.5 Implementation Considerations

Economic Since NASA is a government funded program, there existed limits to the funding of the project. It real world applications, cost of the prototype and the engineering time (assume $25 per hour) involved would be assessed. Since this is a senior project, students were not paid for their time. NASA would have input on the budget concerning future reach and design of this project, especially in the balance between cost and quality of the parts. In some cases, NASA may emphasize the quality and reliability of the parts since a failure could result in the complete loss of the satellite. Also, the maintenance of a satellite comes at a high cost and is not always feasible. Environmental There was little concern towards the impact our design would pose to the environment upon malfunction. In application the satellite would operate in orbit outside the earths atmosphere; therefore immediate effects on the Earths environment would be minute. If the system were to fail and the satellite were to lose power, it would either stay in outer-space or burn on entrance to the Earths atmosphere. Due to its size, there is minimal danger either way. This design is beneficial to the environment because a better power regulation system will improve the life cycle of the satellite, therefore lowering the need to launch new satellites. At the same time this would lower the number of dead satellites in space. Sustainability The system was designed in a way that it is applicable to different satellites with various power needs, battery sizes, and tolerances. This could be done in a way that the engineer can alter the systems program or the converter chip. Although the product will be used in space, NASA would provide the necessary protection against extreme temperatures and protection against debris. Future work regarding sustainability would include a means by which the system could be corrected from a space station if an error should occur rather than losing the satellite due to power failure. Manufacturability Due the fact satellites are not mass-produced for the consumer world, manufacturability is not a main constraint to assess in this project. In general this prototype is designed to be a simple and low price solution which is maintenance-free and reliable. Ethical The design team members did abide by the IEEE Code of Ethics. This included proper citation of sources and accurate work logs, among other things. Health and Safety

The system is designed such that installing, testing, and normal operation do not pose a danger to any persons present. More specifically the product must avoid overheating of the battery or load. This is mainly controlled in the design by the capabilities of the solar array simulator to set a maximum voltage and current. The effect of this in outer space may not affect the safety of individuals, but it may during testing of the product. Social There exists no direct impact on society due to the fact the product will be in space. However, since NASA is a government agency the cost of the product will come out of tax payers pocket.

Political Since NASA is a government funded program, we have abided by the information they have given to us. Also, the need for such research and results was compiled in a form that can be presented to the public and government to show its worth.

2.0 Design Decisions

2.1 Design Configuration

Much of the research and design decisions for this project were made in coordination with NASA. Due to his preference and familiarity with voltage conversion, the NASA representative requested that the DC-DC converter be connected in a series connected boost converter (SCBC) configuration. Several research papers were also provided to our group emphasizing the benefits of this configuration. These include high efficiency, high power density, inherent fault tolerance, and relatively low cost [3].

Figure 2- Basic SCBC (Series Connected Boost Converter) configuration

2.2 DC-DC Converter Chip

Our system design requires the use of a DC-DC converter because the load requires more voltage than the array can supply. The array supplies around 30 V, and the load requires about 42 V. This means that the system needs to boost the voltage by 12 V. Since the SCBC configuration is used, a buck (step down) converter with an input voltage of 30 V and an output voltage of 12 V is needed. The converter output voltage is adjusted by the microprocessor to track the peak power point. Therefore the converter selected needed the capability to adjust the output voltage. Table 1 summarizes the features of different DC-DC converters that met the above mentioned requirements [4, 5, 6]:

Table 1- Summary of specifications for DC-DC converter chips

Alternative 1 2 3 4 Manufacturer Vicor Vicor C&D Artesyn Part Number VI-2W1-CV VI-221-CW VKA100LS12 BXB100-24S12FLT Price ($) 0 (235) 0 (183) 115 136.52 Input (V) Optimal (Range) 24 (18-36) 36 (21-56) 24 (21-36) 24 (18-36) Output (V) 12 12 12 12 Max Power (W) 150 100 100 100

To make the final choice of a converter chip, a decision matrix (Table 2) was formed. In Table 1, the Vicor chips were priced at zero because NASA was able to supply each. Since this was the lowest possible price for a chip, the first two alternatives were rated a 3, or best in the decision matrix. NASA also preferred the use of the Vicor chips, earning the Vicor chips a 3 or the best rating in the manufacturer criteria of Table 2. The input voltage was not included in the decision matrix because all the choices were the same 6 V away from the optimal input voltage. After applying the points method to Table 2, the DC-DC converter chip that we chose to implement was the Vicor VI-2W1-CV. Table 2- Decision matrix for DC-DC converter chips (3-best, 1-worst) Alternative Manufacturer Price Max Power Total 1 3 3 3 9 2 3 3 2 8 3 2 2 2 6 4 2 1 2 5

2.3 Microcontroller
The microcontroller was responsible for regulating the system and assuring the voltage applied to the load would deliver maximum power. The inputs of the microcontroller were the voltage and current values of the solar array. For this application, two main microcontrollers were available for use. They included the Motorola MC68MC68HC12 and the Intel 8051. The MC68HC12 was a readily available system at Ohio Northern University since it was used in the coursework. Hence, there was no development cost, and the team was already familiar with the program. On the other hand, development cost for the Intel 8051 was approximately $200, and the time to purchased, ship, and set up the program had to be accounted for. The familiarity of the microcontroller was also low since it was not used in the universitys coursework. Finally, in the development of the project for real application, the Intel 8051 was advantageous because it

10

was available in a hardened material that can protect against radiation. All the above factors were evaluated in the decision matrix in Table 3 [8, 9].

Microcontroller Motorola MC68MC68HC12 Intel 8051

Table 3- Summary for the microcontroller factors Readily AvailableDevelopment Familiarity specially hardened cost no yes $111 ($0) $170 Course work unknown

Language Assembly, C Assembly, C

Table 4- Decision matrix for microcontroller with values (2-best, 0-worst) Readily Available- Development Familiarity Language Microcontroller specially hardened Cost 40% 20% 20% 20% Motorola 1 2 2 2 MC68MC68HC12 Intel 2 1 0 2 8051

Total 1.8 1

In the decision of which microcontroller to choose, familiarity was the most critical factor because it would save both time and money in labor costs. For this reason, the MC68HC12 was chosen.

2.4 Algorithm
Several algorithms were available that could detect the peak power point. The P&O (perturb and observe) algorithm was based on checking voltage and power values. Just as the name of it states, the input voltage would be increased or decreased until maximum power was reached. The drawback was that it would oscillate at that maximum point for a certain amount of time, causing power loss. The IncCond (incremental conductance) algorithm was based on the slope of the power. The slope, also interpreted as the derivative of power, allowed the voltage and current to be checked. This would produce more accurate readings and limit power loss. The combination of the two algorithms would have been the most efficient, but wouldve had approximately the same accuracy. The operation of the combination of each algorithm would involve implementing the P&O algorithm for a certain amount of time then switching to the IncCond algorithm until max power was found [7]. The decision matrix in Table 5 shows a comparison between the different algorithms. They were all feasible algorithms to implement, but as the points indicate, the IncCond algorithm was the best choice. Cost and complexity were two related factors since the more complex the system was, the more time was needed to implement the design. Consequently, the increase in time

11

would have increased the labor hours, and therefore increased the cost. The final column in the decision matrix indicates that the IncCond was best choice. Further description of the chosen algorithm can be found later in this report.

Table 5- Design matrix for software implementation method Efficiency Cost Complexity Accuracy Algorithm 20% 30% 30% 20%
1-low, 3-high 1-high ,3-low 1-high ,3-low 1-low, 3-high

Total 1.8 2.8 1.8

P&O IncCond. P & 0 and IncCond

1 2 3

2 3 1

2 3 1

2 3 3

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3.0 System Design

3.1 Hardware Solution

The basic design for the hardware for this project can be seen below (see Figure 6). The algorithm used to track the peak power for the solar array requires values for the solar array voltage and current as inputs. For this reason it is necessary that the design send these values to the microprocessor using sensors. The output of the algorithm is the varying voltage value sent to the trim component of the DC-DC converter. This element of hardware is also discussed in the following text.

Figure 3- Basic hardware design The solar array simulator provided by NASA supplies an array voltage in the range of 0-30 V. However, sending a value on the high end of the range is not feasible due to the fact that the microcontroller is limited to voltages on the 0-5 V range. For this reason a voltage divider circuit is implemented which uses a known factor to step down the input voltage. The gain necessary was determined to be 0.1, and was determined as follows:

Gain =

Vout 3 = = 0.1 , 30 Vin

(Eq 1)

where Vout is the voltage sent to the microcontroller and Vin is the solar array voltage. The voltage divider circuit is designed based on voltage division seen below. The resulting circuit is found in Figure 4. To summarize, the value sent to the microcontroller is one tenth of the actual solar array voltage.

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Vout = Vin

1k 1k = Varray (1k + 9k ) (1k + 9k )

(Eq 2)

Figure 4- Voltage division circuit The next step was to determine a means for sending the value of the solar array input current to the microcontroller. In discussing this issue with the NASA representative it was recommended that the design implement a non-invasive Hall Effect current Sensor. This is a 3-pin device which allows for a wire to run through the center of its structure. The sensor then sends the current of that wire through a single pin at a fraction of its original value. By connecting a resistor from the pin to ground, a voltage value can be sent to the microcontroller which is proportional to the current. The circuit for the Hall Effect current Sensor is pictured below.

Figure 5- Hall Effect current sensor As seen above, the current out of the current sensor is 1/1000th of the array current. Running this value over a 100 resistor allows for an output voltage that is one tenth of the array current. This value is then sent to the microcontroller.

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Vm = I m Rm = (0.001 I array ) 100 = 0.1 I array

(Eq 3)

Testing was also performed on the current sensor and the conversion factor was confirmed as 1000. Details regarding the procedure and results are found later in this report. Finally, the trim option in the Vicor DC-DC converter was investigated. When connecting no voltage to the trim pin the converter simply added 12 V to the input voltage. Varying a voltage value on the trim, however, varied the voltage added to the input. For this particular component, a range of voltage increases from 6-13.2 V is possible given trim voltages in the range of 1.252.75 V. The conversion factor for the trim voltage to the increase in output voltage is linear and is seen below. This conversion factor was also confirmed.
Vtrim 4.8 = Voutput

(Eq 4)

3.2 Software Solution

The incremental conductance algorithm is described in the flow chart of Figure 6. Prior to implementation of this algorithm in the microcontroller, all the necessary initializations of control registers, ports, variables, and values are performed. Following this initialization, the sampled values of V present and I present are read and converted to digital values using an on-chip A/D converter. Once these values are found, the change between the past and present values, V and I , are calculated. The next steps of the Incremental Conductance algorithm involves comparing and checking the values. There are two stages to the algorithm, stage 1 and stage 2, as indicated in the figure below. If the magnitude of change in the voltage is greater than an allowable tolerance, the algorithm enters stage 1. In this stage, the algorithm determines if the source conductance is equal to the load conductance. If the change in conductance is less than an allowable tolerance, the algorithm will loop back to the retrieve new present values, otherwise, the algorithm will decide if it is a positive change or a negative change. A positive or negative change increases or decreases the trim value, respectively, by a large step. If the magnitude of change in the voltage is less than an allowable tolerance the algorithm enters stage 2. In this stage, if the magnitude of change in the current is less than an allowable tolerance, the algorithm loops back and retrieves new values. Otherwise, a positive or negative change increases or decreases the trim value, respectively, by a small step. If the trim needes to be adjusted, the generated digital code of the trim value is converted to an analog signal using a D/A converter and then sent to the Vicor chip. Problems occurred in the implementation of the algorithm due to miscalculation of values. These miscalculations surfaced from manipulation of values pre and post operation. Not fully understanding how the microcontroller works with signed and unsigned values during calculations especially division of values.

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start

Initialize

Store

Vpast I past

Retrieve

Vpresent

Transfer to

Vpresent I present Vpast I past

A/D Converter

Stage 1
V

Calculate

and

Stage 2
yes

V < 1
no

yes
I I + < 2 V V

I < 3
no

yes

no

yes

I I > +2 V V

I > 3
no

yes

no

Increase

Vref

Decrease

Vref

Decrease

Vref

Increase

Vref

D/A converter

To trim

Figure 6- Flow chart for microcontroller algorithm

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4.0 Test Results

4.1 Voltage Sensor

Testing of the voltage sensor was done by varying the voltage sent to the sensor and recording the corresponding output. These values are shown in Table 6. Table 6- Voltage sensor test results Input (V) Output (V) 5 0.4944 10 0.988 15 1.4823 20 1.9785 25 2.471 30 2.97 5 0.4916 10 0.9825 15 1.4738 20 1.9662 25 2.455 30 2.932 5 0.4785 10 0.9552 Next a graph of the input versus output voltage was made and is shown in Figure 7. The slope of the trend line represents the average gain of the sensor for the various inputs. Since the sensor was designed for a gain of 0.1, a slope of 0.0987 is very good, having a percent error of only 1.3%.

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Sensor Voltage - Input Vs. Output

3.5 3 y = 0.0987x - 0.0067 2.5 Sensor Output 2 1.5 1 0.5 0 0 5 10 15 20 25 30 35

Sensor Input

Figure 7- Plot of voltage sensor input vs. output Slight deviations from an ideal 0.1 gain could be attributed to resistance within the wires or measuring instrument precision.

4.2 Current Sensor

Testing the voltage sensor was done in a similar manner to that of the voltage sensor. The current running through the sensor was varied and the resulting outputs were recorded. Table 7 shows these results. Table 7- Current sensor test results Input (A) Output (V) 0.973 0.08272 1.972 0.18155 2.979 0.2781 3.952 0.3745 5.01 0.4726 6.1 0.5751 1.623 0.14692 3.26 0.308 4.8 0.4697 6.6 0.6332 8.3 0.793 9.76 0.9554 4.615 0.444 9.44 0.9187 A graph of input vs. output was made and is shown in Figure 8. This sensor was also designed to have a gain of 0.1, so 0.0984 is also very good, with a percent error of only 1.6%.

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Current Sensor - Input Vs. Output

1 0.9 y = 0.0984x - 0.0137 0.8 0.7 Sensor Output (V) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 Se ns or Input (A) 6 7 8 9 10

Figure 8- Plot of current sensor input vs. output

4.3 Solar Array Simulator

Testing was done on the solar array simulator that NASA provided. The simulator allows you to set the maximum current and voltage outputs of the device, and simulates different output scenarios. These scenarios would represent the output capability based on how much sunlight the array was receiving. Several tests were done at different maximum current settings. For each test, the voltage and current were set to a constant value. Then the load was changed and the output voltage and current of the simulator was recorded. The plot of the results is shown in Figure 9. The numerical values of for the graph are shown in Appendix A. From the plots it can be clearly seen that the device did indeed simulate the characteristics of a solar array.

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Power Curve for Solar Array Simulator at Various Loads

350 300 250 Power (W) 200 150 100 50 0 0 10 20 Voltage (V) 30 40 Imax=5A Imax=7.5A Imax=12.5A

Figure 9 - Plot of solar array simulator test results These results confirm that the solar array simulator does indeed have a maximum power point for different load settings.

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5.0 Project Information

5.1 Gantt Timeline

Our timeline was developed using due dates provided for our group, as well as experiences of past senior design projects. The schedule reflects milestones we achieved in the previous quarters (Figure 3). Ideally the system would have been working condition by the end of the winter quarter. This would have allowed for extra time that we needed to devote to unforeseen issues. However, difficulty in creating a working program inhibited our groups ability to move further in the design process. It is our desire to present NASA with accurate records and problems encountered in this design process. Our Gantt chart designed to achieve this is seen in Figure 4.

Figure 10- Main tasks for project

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Figure 11- Gantt timeline for project

5.2 Budget
Cost was not a major issue for the project since the goal was to develop a proof-of-concept using off-the-shelf parts. Most of the more expensive components of the system were provided by NASA and are not be included in the budget. These items included the solar array simulator, the load bank, the Vicor DC-DC converter chip, and Hall Effect current sensor. Equipment borrowed from ONU, such as the MC68HC12 microcontroller, oscilloscopes, and multimeters, also are not included. Hardware costs and labor costs were included in the budget. Hardware costs consisted of a D/A converter, resistors, and miscellaneous parts. Labor costs were $25 per hour and total hours spent on the project were 350 hours. A summary of the costs associated with the project are shown in Table 8. Table 8 - Estimated project budget Part Quantity Cost per item D/A Converter 1 $30 Resistors Misc Parts Labor 350 hrs $25/hr Total Cost

Cost $30 $30 $20 $8750 $8830

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6.0 Conclusions

The objective of this project was to develop a solar array peak power tracker that would be able to provide a load with maximum power. It was our teams desire to design a stand-alone digital solution. This project uses several pieces of equipment borrowed from NASA. These include the solar array simulator, Vicor DC-DC converter chip and a load bank, which acts as the satellite load. The basic design of the peak power tracker is to read the voltage and current levels at the solar array simulator output, process these values using the IncCond algorithm, and then adjust the voltage in order to obtain maximum power. This program is developed on an MC68HC12 microcontroller. It is concluded that the objectives of this project were not met. A running program was necessary for further work involving this system. Further analysis and testing would be needed to overcome these issues. With a working program, the software and hardware could be combined to create a complete system. Future considerations for this project would include using a higher level language for the implementation of the algorithm. With this higher level language, logical and syntax errors would be easier to debug. Such languages could include C or C++. With more time and properly functioning software, the entire system could be tested to verify it is working in all aspects.

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7.0 References

[1] [2] [3] [4] [5]

[6] [7] [8] [9]

Cho, Bo H., and Phuong T. Huynh. "Design and Analysis of a Regulated Peak-Power Tracking System." IEEE Transactions on Aerospace and Electronic Systems 35 (1999): 84-92. Button, Robert M., Theodore W. Iler, and Mark E. Liffring. A Modular, Peak Power Tracking Solar Array Regulator. Society of Automotive Engineers, Inc. 1998. Button, Robert M. An Advanced Photovoltaic Array Regulator Module. NASA Technical Memorandum. August 1996. Lewis Research Center. VI-200, DC-DC Converters. Vicor Corporation. 1 Nov. 2005. <http://www.vicorpower.com/documents/datasheets/ds_vi-200.pdf> Artesyn Technologies DC/DC Converters Isolated: BXB100-24S12FLT. Mouser Electronics. 3 Nov. 2005. <http://www.mouser.com/index.cfm?handler=displayproduct&lstdispproductid=628125&e_categ oryid=100&e_pcodeid=82602> VKA100xS DC-DC Converters. C&D Power Electronics, Inc. 3 Nov. 2005. <http://www.cd4power.com/data/power/ncl/pdc_vka100.pdf> Wu, Wenkai, N. Pongratananukul, Weihong. Qiu, K. Rustom, T. Kasparis, and I. Batareh. DSP-based Multiple Peak Power Tracking for Expandable Power System. IEEE (2003): 525-530. "microMODUL-8051." Phytec America, LLC. 3 Nov. 2005. <http://www.phytec.com/sbc/8bit/um8051.htm> M69EVB912 Evaluation Board. Freescale Semiconductor M68MC68HC12 Development Tools. 2 Nov. 2005. < http://www.newark.com/product-details/text/catalog/52973.html>

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8.0 Biographical Information

CHAD ALBERTS - Chad Alberts is currently a senior Computer Engineering major at Ohio Northern University, Ada, OH. He currently looking for a temporary job for the summer and a permanent job after November of 2006.

JUSTIN BRAUN - Justin Braun is currently a senior Electrical Engineering major at Ohio Northern University, Ada, OH. Following graduation he plans on working at Wright Patterson Air Force Base in Dayton, OH for the Air Force Research Laboratory.

ANNA FOWLER - Anna Fowler is currently a senior Electrical Engineering major at Ohio Northern University, Ada, OH. She is also a member of Society of Women Engineers. Following graduation she plans to work for WD Partners, Inc., a consulting firm located in Dublin, OH.

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Appendices Appendix A Solar Array Simulator Test Results

Vmax = 35 & Imax = 5 Load Voltage Current ( ) (V) (A) 0.5 1 1.5 2 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 10 15 20 25 30 35 40 45 50 2.6 5.11 7.61 10.1 15 17.7 19.99 22.44 24.48 26.02 27.03 27.87 28.28 28.65 28.91 29.92 31.41 32.21 32.71 33.02 33.29 33.47 33.61 33.73 5 5 5 5 5 5 5 5 4.91 4.71 4.49 4.28 4.05 3.82 3.64 3 2.13 1.66 1.35 1.16 1 0.88 0.79 0.72 Power (W) 12.99 25.55 38.06 50.53 75.03 88.55 100 112.14 120.17 122.56 121.41 119.4 114.44 109.47 105.28 89.76 67 53.49 44.2 38.17 33.39 29.42 26.69 24.35 Vmax = 35 & Imax = =7.5 Load Voltage Current ( ) (V) (A) 0.5 1 1.5 2 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 10 15 20 25 30 35 40 45 50 3.92 7.68 11.42 15.15 22.53 25.24 26.87 28.11 28.68 29.17 29.61 29.98 30.31 30.59 30.83 31.61 32.71 33.27 33.64 33.87 34.05 34.19 34.28 34.37 7.5 7.5 7.5 7.5 7.49 7.2 6.72 6.26 5.76 5.33 4.96 4.64 4.36 4.11 3.89 3.2 2.22 1.73 1.39 1.19 1.02 0.9 0.81 0.74 Power (W) 29.4 57.59 85.7 113.68 168.82 181.7 180.51 175.98 165.04 155.31 146.85 139.02 132.02 125.59 119.91 101.15 72.69 57.39 46.89 40.14 34.73 30.8 27.8 25.26 Vmax = 35 & Imax = 12.5 Load Voltage Current ( ) (V) (A) 0.5 1 1.5 1.7 2 2.2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 10 15 20 25 30 35 40 45 50 6.54 12.79 19.04 21.52 24.71 26 27.5 28.76 29.59 30.22 30.72 31.14 31.49 31.78 32.04 32.26 32.45 32.63 33.14 33.87 34.24 34.48 34.62 34.71 34.79 34.88 34.94 12.5 12.5 12.5 12.5 12.25 11.74 10.94 9.55 8.44 7.56 6.85 6.25 5.75 5.33 4.96 4.64 4.36 4.12 3.36 2.3 1.77 1.43 1.21 1.05 0.92 0.82 0.75 Power (W) 81.73 159.86 238.13 268.96 302.56 305.15 300.83 274.81 249.75 228.5 210.33 194.69 181.04 169.24 158.8 149.73 141.37 134.35 111.43 78.01 60.67 49.37 41.92 36.41 32.08 28.6 26.27

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