SCALING

As transistors become smaller, they switch faster, dissipate less power, and are cheaper to manufacture.

By scaling, the reliability issues occur, introduces new problems.

complexity increases and

Figure showed the unrelenting march of technology, in which feature size has reduced by 30% every two to three years.

TRANSISTOR SCALING
Dennards Scaling Law predicts that the basic operational characteristics of a MOS transistor can be preserved and the performance improved if the critical parameters of a device are scaled by a dimensionless factor S.

These parameters include the following: All dimensions (in the x, y, and z directions) Device voltages Doping concentration densities This approach is also called constant field scaling

Another approach is lateral scaling, in which only the gate length is scaled. This is commonly called a gate shrink.

The industry generally scales process generations with 6m. This is also called a 30% shrink. It reduces the cost (area) of a transistor by a factor of two.

Feature sizes were shrunk from 6m to 1m while maintaining a 5 V supply voltage. This constant voltage scaling offered quadratic delay improvement as well as cost reduction.

INTERCONNECT SCALING
Wires also tend to be scaled equally in width and thickness to maintain an aspect ratio close to 2. Local wires : Run within functional units - bottom layers of metal. Scale with feature size. Most local wires are short enough that their resistance does not matter.Their delay is improving just like gates. Semiglobal (or scaled ) wires: Run across larger blocks or cores, - middle layers of metal. Scale with feature size. Semiglobal wires long enough to require repeaters are speeding up, but not as fast as gates. Global wires: Run across the entire chip -upper levels of metal. Global wires do not scale with feature size; indeed, they may get longer (by a factor of Dc ,) because die size has been gradually increasing. Global wires, even with optimal repeaters, are getting slower as technology scales. The time to cross a chip in a nanometer process can be multiple cycles, and this delay must be accounted for in the microarchitecture.

Influence of scaling on interconnect characteristics

To future challenges before they hold up production, cooperation among many companies and researchers is required.

International Technology Roadmap for Semiconductors (ITRS) develop compatible process steps and to anticipate and address

The Semiconductor Industry Association (SIA) develops and updates the ITRS so that development efforts are not wasted on incompatible technologies and to predict future needs and direct research efforts.

Such an effort to predict the future leads to error, and the industry has scaled feature sizes and clock frequencies more rapidly than the roadmap predicted in the late 1990s.

The roadmap offers a more coherent vision by simply interpolating straight lines through historical scaling data.

The ITRS forecasts a major new technology generation, also called technology node, approximately every three years.

wrong impression of being able to scale proportionally to zero dimensions and zero voltage. i)Improved Performance and Cost: The most positive impact of scaling is that performance and cost are steadily improving. Because transistors are becoming cheaper each year, architects particularly need creative ideas of how to exploit growing numbers of transistors to deliver more or better functions.

Impacts on One of the limitations of first-order scaling is that it gives the Design

Figure plots the number of transistors and average price per transistor shipped by the semiconductor industry over the past three decades

ii)Interconnect: Scaled transistors are steadily improving in delay, but scaled global wires are getting worse. In practice, for short wires, such as those inside a logic gate, the wire RC delay is negligible. However, the long wires present a considerable challenge. It is no longer possible to send a signal from one side of a large, high-performance chip to another in a single cycle.

Also, the reachable radius that a signal can travel in a cycle is steadily getting smaller, as shown in Figure

This requires that microarchitects understand the floorplan and budget multiple pipeline stages for data to travel long distances across the die. Repeaters help somewhat, but the repeater farms must be allocated space in the floorplan. As scaled gates become faster, the delay of a repeater goes down and hence,it will be better to use more repeaters. This means a greater number of repeater farms are required. One technique to alleviate the interconnect problem is to use more layers of interconnect. Fig shows the number of layers of interconnect increasing with each generation in TSMC processes. The lower layers of interconnect are classically scaled to provide high-density short connections. The higher layers are scaled less aggressively, or possibly even reverse-scaled to be thicker and wider to provide low-resistance, highspeed interconnect, good clock distribution networks, and a stiff power grid. Copper and low-k dielectrics were also introduced to reduce resistance and capacitance.

In microprocessor, power density is increased because extensive pipelining increased clock frequencies much faster than classical scaling would predict. High-performance microprocessors has the limit of about 150 W that a lowcost fan and heat sink can dissipate. Now designers aim for the maximum performance under a power envelope rather than for the maximum clock rate. Static power is a more serious limitation. Subthreshold leakage power increased exponentially as threshold voltages decreased. Gate leakage current is also important for oxides of less than 1520 A. If oxides thickness does not scale with the other dimensions, the ratio of ON to OFF current degrades. Even if power remains constant, lower supply voltage leads to higher current density. This in turn causes higher IR drops and di/dt noise in the supply network. All considered, scaling is being squeezed from many directions by power limitations. Some manufacturers are finding that conventional scaling can offer performance or power benefits, but not both. Intel is aggressively introducing new materials such as high-k metal gates and strained silicon to continue to see both performance and power benefits.

iii)Power:

iv)Variability:

As transistors shrink, the spread in parameters such as channel length and threshold voltage increases. Variability, became a key factor in mainstream digital circuits. To ensure that an acceptable fraction of chips meet specifications, designers are forced to employ wider guard bands .

v)Productivity:

The number of transistors that fit on a chip is increasing faster than designer productivity . This leads to design teams of increasing size, difficulty recruiting enough experienced engineers when the economy is good, and a trend to outsource to locations such as India where more engineering graduates are available. It has driven a search for design methodologies that maximize productivity, even at the expense of performance and area. Now most chips are designed using synthesis and place& route. The number of 50100 Kgate blocks is growing, even in relatively low-end systems.This demands greater attention to floorplanning and placement of the blocks. One of the key tools to solve the productivity gap is design reuse.

vi)Physical Limits:
A minimum-sized transistor in a 32 nm process has an effective channel length of less than 100 Si atoms. The gate oxide is only 4 atoms thick.

Scaling cannot continue indefinitely as dimensions reach the atomic scale. To overcome this, there are many issues that include:

Subthreshold leakage at low VDD and Vt Tunneling current through thin oxides Poor I-V characteristics due to DIBL and other short channel effects Dynamic power dissipation Lithography limitations Exponentially increasing costs of fabrication facilities and mask sets Electromigration Interconnect delay Variability

At the 32 nm node and beyond, the performance and power benefits of geometrical scaling are starting to diminish as the engineering costs continue to increase.

Nevertheless, scaling still provides a competitive advantage in a cutthroat industry. Improved structures such as copper wires, low-k dielectrics, strained silicon, high-k metal gates, and 3D integration provide benefits independent of reduced feature size.