Transistor 2

VI.
Transistor ampliers: Biasing and Small Signal Model

6.1 Introduction
Transistor ampliers utilizing BJT or FET are similar in design and analysis. Accordingly
we will discuss BJT ampliers thoroughly. Then, similar FET circuits are briey reviewed.
Consider the circuit below. The operating point of the BJT is shown in the i
C
v
CE
space.
v
CE
B
R
V
BB
V
CC
R
C
i
C
i
B
v
BE
+
_
+
_
i
E
Let us add a sinusoidal source with an amplitude of V
BB
in series with V
BB
. In response to
this additional source, the base current will become i
B
+i
B
leading to the collector current
of i
C
+ i
C
and CE voltage of v
CE
+ v
CE
.
v
CE
B
R
V
BB
V
CC
R
C
v
CE
i
B
i
C
i
C
i
B
V
BB
v
BE
v
BE
+
_
+
_
+
+
+
+
~
+
For example, assume without the sinusoidal source, the base current is 150 A, i
C
= 22 mA,
and v
CE
= 7 V (the Q point). If the amplitude of i
B
is 40 A, then with the addition of
the sinusoidal source i
B
+ i
B
= 150 + 40 cos(t) and varies from 110 to 190 A. The BJT
operating point should remain on the load line and collector current and CE voltage change
with changing base current while remaining on the load line. For example when base current
is 190 A, the collector current is 28.6 mA and CE voltage is about 4.5 V. As can be seen
from the gure above, the collector current will approximately be i
C
+i
C
= 22+6.6 cos(t)
and CE voltage is v
CE
+ v
CE
= 7 2.5 cos(t).
The above example shows that the signal from the sinusoidal source V
BB
is greatly amplied
and appears as signals in collector current and CE voltage. It is clear from the gure that
this happens as long as the BJT stays in the active-linear state. As the amplitude of i
B
ECE65 Lecture Notes (F. Najmabadi), Winter 2006 158
is increased, the swings of BJT operating point along the load line become larger and larger
and, at some value of i
B
, BJT will enter either the cut-o or saturation state and the
output signals will not be a sinusoidal function. Note: An important observation is that
one should locate the Q point in the middle of the load line if we want to have the largest
output signal.
The above circuit, however, has two major problems: 1) The input signal, V
BB
, is in
series with the V
BB
DC voltage making design of previous two-port network dicult, and
2) The output signal is usually taken across R
C
as R
C
i
C
. This output voltage has a DC
component which is of no interest and can cause problems in the design of the next-stage,
two-port network.
The DC voltage needed to bias the BJT (establish the Q point) and the AC signal of
interest can be added together or separated using capacitor coupling as dis iscussed below.
6.1.1 Capacitive Coupling
For DC voltages ( = 0), the capacitor is an open circuit (innite impedance). For AC
voltages, the impedance of a capacitor, Z = j/(C), can be made suciently small by
choosing an appropriately large value for C (the higher the frequency, the lower the C value
that one needs). This property of capacitors can be used to add and separate AC and DC
signals. Example below highlights this eect.
C
1
1
2
R
B
+15 V
A
v
i
+
R
Consider the circuit below which includes a DC source of
15 V and an AC source of v
i
= V
i
cos(t). We are inter-
ested to calculate voltages v
A
and v
B
. The best method
to solve this circuit is superposition. The circuit is bro-
ken into two circuits. In circuit 1, we kill the AC source
and keep the DC source. In circuit 2, we kill the DC
source and keep the AC source. Superposition principle
states that v
A
= v
A1
+ v
A2
and v
B
= v
B1
+ v
B2
.
C
1
2
R
A
B
1
+15 V +15 V
C
1
2
R
A
B
1
C
1
2
R
A
B
1
v
i
v
v
v
v
+
v
i
v
v
1
1
2
2
+
R
+
R
+
R
Consider the rst circuit. It is driven by a DC source and, therefore, the capacitor will act
as open circuit. The voltage v
A1
= 0 as it is connected to ground and v
B1
can be found by
voltage divider formula: v
B1
= 15R
1
/(R
1
+ R
2
). As can be seen both v
A1
and v
B1
are DC
voltages.
In the second circuit, resistors R
1
and R
2
are in parallel. Let R
B
= R
1
R
2
. The circuit
is a high-pass lter: V
A2
= V
i
and V
B2
= V
i
(R
B
)/(R
B
+ 1/jC). If we operate the circuit
at frequency above the cut-o frequency of the lter, i.e., R
B
1/C, we will have V
B2

V
A2
= V
i
and v
B2
v
A2
= V
i
cos(t). Therefore, for 1/R
B
C
v
A
= v
A1
+ v
A2
= V
i
cos(t)
v
B
= v
B1
+ v
B2
=
R
1
R
1
+ R
2
15 + V
i
cos(t)
Obviously, the capacitor is preventing the DC voltage to appear at point A, while the voltage
at point B is the sum of DC signal from 15-V supply and the AC signal.
Using capacitive coupling, we can recongure our previous amplier circuit as is shown in
the gure below. Capacitive coupling is used extensively in transistor ampliers.
B
R
V
CC
R
C
i
B
i
C
i
C
i
B
v
BE
v
BE
V
BB
V
BB
v
CE
v
CE
v
CE
v
CE
v
CE
+
_
+
_
+
~
+
+
+
+
+
BJT amplier circuits are analyzed using superposition, similar to the example above:
1) DC Biasing: The input AC signal is set to zero and capacitors act as open circuit. This
analysis establishes the Q point in the active-linear state.
2) AC Response: DC bias voltages are set to zero. The response of the circuit to an AC
input is calculated and the transfer function, input and output impedances, etc. are found.
The break up of the problem into these two parts have an additional advantage as the
requirement for accuracy are dierent in the two cases. For DC biasing, we are interested in
locating the Q point roughly in the middle of active-linear state. The exact location of the
Q point is not important. Thus, a simple model, such as large-signal model of page 114 is
quite adequate. We are, however, interested to compute the transfer function for AC signals
more accurately. We will develop a model which is more accurate for small AC signals in
this section.
FET-based ampliers are similar. FET should be biased similar to BJT and the analysis
method is broken into the DC biasing and the AC response.
6.2 BJT Biasing
v
CE
i
C
i
B
v
BE
R
C
R
B
V
CC
+
_
+
_
This simple bias circuit is usually referred to as xed bias as a
xed voltage is applied to the BJT base. As we like to have only one
power supply, the base circuit is also powered by V
CC
. (To avoid
confusion, we will use capital letters to denote DC bias values e.g.,
I
C
.) Assuming that BJT is in active-linear state, we have:
BE-KVL: V
CC
= I
B
R
B
+ V
BE
I
B
=
V
CC
V
BE
R
B
I
C
= I
B
=
V
CC
V
BE
R
B
CE-KVL: V
CC
= I
C
R
C
+ V
CE
V
CE
= V
CC
I
C
R
C
V
CE
= V
CC
R
C
R
B
(V
CC
V
BE
)
For a given circuit (known R
C
, R
B
, V
CC
, and BJT ) the above equations can be solved to
nd the Q-point (I
B
, I
C
, and V
CE
). Alternatively, one can use the above equations to design
a BJT circuit to operate at a certain Q point. (Note: Do not memorize the above equations
or use them as formulas, they can be easily derived from simple KVLs).
Example 1: Find values of R
C
, R
B
in the above circuit with = 100 and V
CC
= 15 V so
that the Q-point is I
C
= 25 mA and V
CE
= 7.5 V.
Since the BJT is in the active-linear state (V
CE
= 7.5 > V
), I
B
= I
C
/ = 0.25 mA. BE-KVL
and CE-KVL result in:
BE-KVL: V
CC
+ R
B
I
B
+ V
BE
= 0 R
B
=
15 0.7
0.250
= 57.2 k
CE-KVL: V
CC
= I
C
R
C
+ V
CE
15 = 25 10
3
R
C
+ 7.5 R
C
= 300
Example 2: Consider the circuit designed in example 1. What is the Q point if = 200.
We have R
B
= 57.2 k, R
C
= 300 , and V
CC
= 15 V but I
B
, I
C
, and V
CE
are unknown.
Assuming that the BJT is in the active-linear state:
BE-KVL: V
CC
+ R
B
I
B
+ V
BE
= 0 I
B
=
V
CC
V
BE
R
B
= 0.25 mA
I
C
= I
B
= 50 mA
CE-KVL: V
CC
= I
C
R
C
+ V
CE
V
CE
= 15 300 50 10
3
= 0
As V
CE
< v
the BJT is not in the active-linear state (since I

C
> 0, the BJT should be in
saturation).
The above examples show the problem with our simple xed-bias circuit as the of a
commercial BJT can depart by a factor of 2 from its average value given in the manufacturers
spec sheet. More importantly, environmental conditions (mainly temperature) can play an
important role. In a given BJT, I
C
increases by 9% per

C for a xed V
BE
(because of the
change in ). Consider a circuit which is tested to operate perfectly at 25
C. At 35
C,
and I
C
will be roughly doubled and the BJT can be in saturation! In fact, the circuit has a
build-in positive feedback. If the temperature rises slightly, the corresponding increase in
makes I
C
larger. Since the power dissipation in the transistor is V
CE
I
C
, the transistor may
get hotter which increases transistor and I
C
further and can cause a thermal runaway.
The problem is that our biasing circuit xes the value of I
B
(independent of BJT parameters)
and, as a result, both I
C
and V
CE
are directly proportional to BJT (see formulas in the
previous page). A biasing scheme should be found that make the Q-point (I
C
and V
CE
)
independent of transistor and insensitive to the above problems Use negative feedback!
6.2.1 Voltage-Divider Biasing
v
CE
i
C
i
B
v
BE
R
C
V
CC
R
1
R
E
R
2
+
_
+
_
v
CE
i
C
i
B
v
BE
R
C
R
E
V
CC
V
BB
R
B
+
_
+
_
+
Thevenin
Equivalent
{
This biasing scheme can be best analyzed and understood if we re-
place R
1
and R
2
of the voltage divider with its Thevenin equivalent:
V
BB
=
R
2
R
1
+ R
2
V
CC
and R
B
= R
1
R
2
The emitter resistor, R
E
, provides the negative feedback. Suppose
I
C
becomes larger than the designed value (e.g., larger due to an
increase in temperature). Then, V
E
= R
E
I
E
will increase. Since
V
BB
and R
B
do not change, KVL in the BE loop shows that I
B
should decrease which will reduce I
C
back towards its design value.
If I
C
becomes smaller than its design value opposite happens, I
B
has to increase which will increase and stabilize I
C
.
Analysis below also shows that the Q point is independent of BJT
parameters:
I
E
I
C
= I
B
BE-KVL: V
BB
= R
B
I
B
+ V
BE
+ I
E
R
E
I
B
=
V
BB
V
BE
R
B
+ R
E
CE-KVL: V
CC
= R
C
I
C
+ V
CE
+ I
E
R
E
V
CE
= V
CC
I
C
(R
C
+ R
E
)
Choose R
B
such that R
B
R
E
(this is the condition for the feedback to be eective):
I
C
I
E

V
BB
V
BE
R
E
and I
B

V
BB
V
BE
R
E
V
CE
= V
CC
I
C
(R
C
+ R
E
) V
CC
R
C
+ R
E
R
E
(V
BB
V
BE
)
Note that now both I
C
and V
CE
are independent of .
Another way to see how the circuit works is to consider BE-KVL: V
BB
= R
B
I
B
+V
BE
+I
E
R
E
.
If we choose R
B
R
E
(I
E
/I
B
)R
E
or R
B
I
B
I
E
R
E
(rhe feedback condition above),
the KVL reduces to V
BB
V
BE
+ I
E
R
E
, forcing a constant I
E
independent of the BJT .
As I
C
I
E
this will also xes the Q point of BJT. If the BJT parameters change (dierent
due to a change in temperature), the circuit forces I
E
to remain xed and changes I
B
accordingly. This biasing scheme is one of several methods which x I
C
(and V
CE
) and allow
the BJT to adjust I
B
(through negative feedback) to achieve the proper bias. This class of
biasing methods is usually called self-bias schemes.
Another important point follows from V
BB
V
BE
+ I
E
R
E
. As V
BE
is not a constant and
can change slightly (can drop to 0.6 or increase to 0.8 V for a Si BJT), we need to ensure
that I
E
R
E
is much larger than possible changes in V
BE
. As changes in V
BE
= v
is about
0.1 V, we need to ensure that V
E
= I
E
R
E
0.1 or V
E
> 10 0.1 = 1 V.
Example: Design a stable bias circuit with a Q point of I
C
= 2.5 mA and V
CE
= 7.5 V.
Transistor ranges from 50 to 200.
Step 1: Find V
CC
: As we like to have the Q-point to be located in the middle of the load
line, we set V
CC
= 2V
CE
= 2 7.5 = 15 V.
Step 2: Find R
C
and R
E
:
V
CE
= V
CC
I
C
(R
C
+ R
E
) R
C
+ R
E
=
7.5
2.5 10
3
= 3 k
We are free to choose R
C
and R
E
(usually the AC response sets the values of R
C
and R
E
as is
discussed later). We have to ensure, however, that V
E
= I
E
R
E
> 1 V or R
E
> 1/I
E
= 400 .
Lets choose R
E
= 1 k which gives R
C
= 3 R
E
= 2 k (both commercial values).
Step 3: Find R
B
and V
BB
: We need to set R
B
R
E
. As any commercial BJT has a range
of values and we want to ensure that the above inequality is always satised, we should
use the minimum value:
R
B

min
R
E
R
B
= 0.1
min
R
E
= 0.1 50 1, 000 = 5 k
V
BB
V
BE
+ I
E
R
E
= 0.7 + 2.5 10
3
10
3
= 3.2 V
Step 4: Find R
1
and R
2
R
B
= R
1
R
2
=
R
1
R
2
R
1
+ R
2
= 5 k
V
BB
V
CC
=
R
2
R
1
+ R
2
=
3.2
15
= 0.21
The above are two equations in two unknowns (R
1
and R
2
). The easiest way to solve these
equations are to divide the two equations to nd R
1
and use that in the equation for V
BB
:
R
1
=
5 k
0.21
= 24 k
R
2
R
1
+ R
2
= 0.21 0.79R
2
= 0.21R
1
R
2
= 6.4 k
Reasonable commercial values for R
1
and R
2
are and 24 k and 6.2 k, respectively.
The voltage divider biasing scheme is used frequently in BJT ampliers. There are two
drawbacks to this biasing scheme that may make it unsuitable for some applications:
1) Because V
B
> 0, a coupling capacitor is needed to attach the input signal to the amplier
circuit. As a result, this biasing scheme leads to an AC amplier (cannot amplify DC
signals). In some applications, we need DC ampliers. Biasing with two voltage sources,
discussed below, can solve this problem.
2) The voltage divider biasing requires 3 resistors (R
1
, R
2
, and R
E
), and a coupling capacitor.
In ICs, resistors and large capacitors take too much space compared to transistors. It is
preferable to reduce their numbers as much as possible. For IC applications, current-
mirrors are usually used to bias BJT ampliers as is discussed below.
6.2.2 Biasing with 2 Voltage Sources
v
CE
i
C
i
B
v
BE
R
C
R
E
V
CC
R
B
V
EE
+
_
+
_
This biasing scheme is also a self-bias method and is similar
to the voltage-divider biasing. Basically, we have assigned a
voltage of V
EE
to the ground (reference voltage) and chosen
V
EE
= V
BB
. As such, all of the currents and voltages in the
circuit should be identical to the voltage-divider biasing. We
should nd that this is a stable bias point as long as R
B
R
E
.
BE-KVL: R
B
I
B
+ V
BE
+ R
E
I
E
V
EE
= 0
R
B
I
E
+ R
E
I
E
= V
EE
V
BE
I
E
=
V
EE
V
BE
R
E
+ R
B
/
Similar to the bias with one power supply, if we choose R
B
such that, R
B
R
E
, we get:
I
C
I
E

V
EE
V
BE
R
E
= const
CE-KVL: V
CC
= R
C
I
C
+ V
CE
+ R
E
I
E
V
EE
V
CE
= V
CC
+ V
EE
I
C
(R
C
+ R
E
) = const
Therefore, I
C
, and V
CE
are independent and bias point is stable. Similar to the voltage-
divider bias, we need to ensure that R
E
I
E
1 V to account for possible variation in V
BE
.
Bias with two power supplies has certain advantages over biasing with one power supply, it
has two resistors, R
B
and R
E
(as opposed to three), and in fact, in most applications, we can
remove R
B
altogether and directly couple the input signal (without a coupling capacitor) to
the BJT). As such, such a conguration can also amplify DC signals.
6.2.3 Biasing in ICs: Current Mirrors
v
CE
i
C
i
B
v
BE
R
C
R
E
V
CC
R
B
V
EE
+
_
+
_
I
The self-bias schemes above, voltage-divider and bias with 2 voltage
sources, essentially operate the same way: They force I
E
to have
a given value independent of the BJT parameters. In principle, the
same objective can be achieved if we could bias the BJT with a current
source as is shown. In this case, no bias resistor is needed and we only
need to include resistors necessary for AC operation. As such, biasing
with a current source is the preferred way in most integrated circuits.
Such a biasing can be achieved with a current mirror circuit.
i
C
v
BE1
v
BE2
V
EE
i
C
i
E
i
E
E
2i
+
_
+
_
ref
I
+1
I
o
1
Q Q
2
Consider the circuit shown with two identical transistors, Q
1
and Q
2
. Because both bases and emitters of the transistors
are connected together, KVL leads to v
BE1
= v
BE2
. As BJTs
are identical, they should have similar i
B
(i
B1
= i
B2
= i
B
)
and, therefore, similar i
E
= i
E1
= i
E2
and i
C
= i
C1
= i
C2
i
B
=
i
E
+ 1
I
o
= i
C
=
i
E
+ 1
KCL: I
ref
= i
C
+
2i
E
+ 1
=
i
E
+ 1
+
2i
E
+ 1
=
+ 2
+ 1
i
E
I
o
I
ref
=

+ 2
=
1
1 + 2/
We have explicitly used i
C
= i
B
and i
E
= ( + 1)i
B
to illustrate the impact of .
For 1, I
o
I
ref
(with an accuracy of 2/). This circuit is called a current mirror
as the two transistors work in tandem to ensure that current I
o
remains the same as I
ref
no matter what circuit is attached to the collector of Q
2
. As such, the circuit behaves as
a current source and can be used to bias BJT circuits, i.e., Q
2
collector is attached to the
emitter circuit of the BJT amplier to be biased.
i
C
v
BE1
v
BE2
V
EE
i
E
i
E
V
CC
R
C
+
_
+
_
Io ref
1
Q Q
2
I
Value of I
ref
can be set in many ways. The simplest is by using
a resistor R
c
as is shown. By KVL, we have:
V
CC
= R
C
I
ref
+ v
BE1
V
EE
I
ref
=
V
CC
+ V
EE
v
BE1
R
C
= const
Current mirror circuits are widely used for biasing BJTs. In the simple current mirror circuit
above, I
o
= I
ref
with a relative accuracy of 2/ and I
ref
is constant with an accuracy of
small changes in v
BE1
. Variations of the above simple current mirror, such as Wilson current
mirror and Widlar current mirror, have I
o
= I
ref
even with a higher accuracy and also
compensate for the small changes in v
BE
. Wilson mirror is especially popular because it
replace R
c
with a transistor.
The right hand part of the current mirror circuit can be duplicated such that one current
mirror circuit can bias several BJT circuits as is shown. In fact, by coupling output of two
or more of the right hand BJTs, integer multiples of I
ref
can be made for biasing circuits
which require a higher bias current.
V
EE
V
CC
R
C
ref
I Io Io
2I
o
A large family of BJT circuit, including current mirrors, dierential ampliers, and emitter-
coupled logic circuits include identical BJT pairs. These circuits are rarely made of discrete
transistors because if one chooses two commercial BJTs, e.g., two 2N3904, there is no guar-
anty that
1
=
2
. However, if two identical BJTs are manufactured together on one chip
next to each other,
1

2
within a couple of percent.
6.3 Biasing FETs
Field-eect transistors can also be used in amplier circuits by operating the FET in the
active state. Similar to BJT ampliers, we need to apply a DC bias (in addition to the input
AC signal) so that the FET remains in the active state for the entire period of the AC signal.
V
DD
R
R
D
V
GG
G
The xed-bias scheme for FETs is shown. Note that R
G
is not necessary
for biasing but is necessary for AC operation as without R
G
the input
AC signal will be grounded through V
GG
.
GS-KVL: V
GG
= V
GS
I
D
= K(V
GS
V
t
)
2
= K(V
GG
V
t
)
2
DS-KVL: V
DD
= I
D
R
D
+ V
DS
V
DS
= V
DD
KR
D
(V
GG
V
t
)
2
Similar to the BJT , both V
t
and K vary due to the manufacturing and environmental
conditions. For example, as temperture is increased, both V
t
and K decrease: decreasing
K decreases I
D
while decreasing V
t
raises I
D
. The net eect (usually) is that I
D
decreases.
While the thermal runaway is not a problem in FETs, the bias point is not stable.
Similar to the BJT bias circuits, addition of a resistor R
S
provides the negative feedback
necessary to stabilize the bias point. For the voltage divider self bias, V
G
is set by R
1
and R
2
.
Since V
GS
= V
G
R
S
I
D
, any decrease in I
D
would increase V
GS
and increases I
D
. Similarly,
any increase in I
D
would decrease V
GS
and decreases I
D
. As a result, I
D
will stay nearly
constant (because I
D
= K(V
GS
V
t
)
2
, I
D
does not remain constant like I
C
in a BJT, rather
it variation become much smaller by the negative feedback). Another dierence between
voltage-divider self-bias for FET with that of BJT si that in the case of BJT, we have to
ensure that R
B
R
E
for negative feedback to be eective. THis generally limits the value
of R
1
and R
2
. In a FET, I
G
= 0 and no such limitaion exists. Therefore, R
1
and R
2
can be
taken to be large (M) which is important in the AC response as is discussed later.
Self bias with 2 power supplies and FET current mirror bias are also shown below.
V
R
R
R
R
D
S
1
2
i
D
DD
R
R
R
DD
V
i
D
D
S
1
V
SS
R
ref
I I
o
V
DD
Voltage-divider (Self Bias) Bias with 2 power supplies FET Current Mirror
6.4 BJT Small Signal Model
B
v
BE
v
v
sat
i i
C
v
CE
We calculated the DC behavior
of the BJT (DC biasing) with a
simple large-signal model. In the
active-linear state, this model is
simply: v
BE
= 0.7 V, i
C
= i
B
.
This model is sucient for calcu-
lating the Q point as we are only
interested in ensuring sucient de-
sign space for the amplier, i.e.,
Q point should be in the middle
of the load line in the active-linear
state. In fact, for our good bias-
ing scheme with negative feedback,
the Q point location is independent
of BJT parameters (and, therefore,
independent of model used!).
A comparison of the simple large-
signal model with the iv character-
istics of the BJT shows that our
simple large-signal model is crude.
For example, the input AC signal results in small changes in v
BE
around 0.7 V (Q point) and
corresponding changes in i
B
. The simple model cannot be used to calculate these changes
(It assumes v
BE
is constant!). Also for a xed i
B
, i
C
is not exactly constant as is assumed
in the simple model (see i
C
vs v
CE
graphs). As a whole, the simple large signal model is not
sucient to describe the AC behavior of BJT ampliers where more accurate representations
of the amplier gain, input and output resistance, etc. are needed.
A more accurate, but still linear, model can be developed by assuming that the changes in
transistor voltages and currents due to the AC signal are small compared to corresponding
Q-point values and using a Taylor series expansion. Consider function f(x). Suppose we
know the value of the function and all of its derivative at some known point x
0
. Then,
the value of the function in the neighborhood of x
0
can be found from the Taylor Series
expansion as:
f(x
0
+ x) = f(x
0
) + x
df
dx
x=x
0
+
(x)
2
2
d
2
f
dx
2
x=x
0
+ ...
Close to our original point of x
0
, x is small and the high order terms of this expansion
(terms with (x)
n
, n = 2, 3, ...) usually become very small. Typically, we consider only the
rst order term, i.e.,
f(x
0
+ x) f(x
0
) + x
df
dx
x=x
0
The Taylor series expansion can be similarly applied to function of two or more variables
such as f(x, y):
f(x
0
+ x, y
0
+ y) f(x
0
, y
0
) + x
f
x
x
0
,y
0
+ y
f
y
x
0
,y
0
In a BJT, there are four parameters of interest: i
B
, i
C
, v
BE
, and v
CE
. The BJT iv charac-
teristics plots, specify two of the above parameters, v
BE
and i
C
in terms of the other two,
i
B
and v
CE
, i.e., v
BE
is a function of i
B
and v
CE
(written as v
BE
(i
B
, v
CE
) similar to f(x, y))
and i
C
is a function of i
B
and v
CE
, i
C
(i
B
, v
CE
).
Lets assume that BJT is biased and the Q point parameters are I
B
, I
C
, V
BE
and V
CE
. We
now apply a small AC signal to the BJT. This small AC signal changes v
CE
and i
B
by small
values around the Q point:
i
B
= I
B
+ i
B
v
CE
= V
CE
+ v
CE
The AC changes, i
B
and v
CE
results in AC changes in v
BE
and i
C
that can be found
from Taylor series expansion in the neighborhood of the Q point, similar to expansion of
f(x
0
+ x, y
0
+ y) above:
v
BE
(I
B
+ i
B
, V
CE
+ v
CE
) = V
BE
+
v
BE
i
B
Q
i
B
+
v
BE
v
CE
Q
v
CE
i
C
(I
B
+ i
B
, V
CE
+ v
CE
) = I
C
+
i
C
i
B
Q
i
B
+
i
C
v
CE
Q
v
CE
where all partial derivatives are calculated at the Q point and we have noted that at the Q
point, v
BE
(I
B
, V
CE
) = V
BE
and i
C
(I
B
, V
CE
) = I
C
. We denote the AC changes in v
BE
and i
C
as v
BE
and i
C
, respectively:
v
BE
(I
B
+ i
B
, V
CE
+ v
CE
) = V
BE
+ v
BE
i
C
(I
B
+ i
B
, V
CE
+ v
CE
) = I
C
+ i
C
So, by applying a small AC signal, we have changed i
B
and v
CE
by small amounts, i
B
and
v
CE
, and BJT has responded by changing , v
BE
and i
C
by small AC amounts, v
BE
and
i
C
. From the above two sets of equations we can nd the BJT response to AC signals:
v
BE
=
v
BE
i
B
i
B
+
v
BE
v
CE
v
CE
, i
C
=
i
C
i
B
i
B
+
i
C
v
CE
v
CE
where the partial derivatives are the slope of the iv curves near the Q point. We dene
h
ie

v
BE
i
B
, h
re

v
BE
v
CE
, h
fe

i
C
i
B
, h
oe

i
C
v
CE
Thus, response of BJT to small signals can be written as:
v
BE
= h
ie
i
B
+ h
re
v
CE
i
C
= h
fe
i
B
+ h
oe
v
CE
which is our small-signal model for BJT.
We now need to relate the above analytical model to circuit elements so that we can solve
BJT circuits. Consider the expression for v
BE
v
BE
= h
ie
i
B
+ h
re
v
CE
Each term on the right hand side should have units of Volts. Thus, h
ie
should have units of
resistance and h
re
should have no units (these are consistent with the denitions of h
ie
and
h
re
). Furthermore, the above equation is like a KVL: the voltage drop between the base and
emitter (v
BE
) is equal to the sum of voltage drops across two elements. The voltage drop
across the rst element is h
ie
i
B
. So, it is a resistor with a value of h
ie
. The voltage drop
across the second element is h
re
v
CE
. Thus, it is a dependent voltage source.
ie
V = h i
B 1
i
v
re 2 CE
V = h v
+
i
re CE
h v
v
ie
h
E
B
+
+
+
E
B
Now consider the expression for i
C
:
i
C
= h
fe
i
B
+ h
oe
v
CE
Each term on the right hand side should have units of Amperes. Thus, h
fe
should have no
units and h
oe
should have units of conductance (these are consistent with the denitions of
h
oe
and h
fe
.) Furthermore, the above equation is like a KCL: the collector current (i
C
)
is equal to the sum of two currents. The current in rst element is h
fe
i
B
. So, it is a
dependent current source. The current in the second element is proportional to h
oe
/v
CE
.
So it is a resistor with the value of 1/h
oe
.
i
C
i = h i
1 fe B
CE
v
2
i = h
oe
CE
v
B fe
h i
1/h
oe
i
C
CE
v
E
C
+
E
C
+
Now, if put the models for BE and CE terminals together we arrive at the small signal
hybrid model for BJT. It is similar to the hybrid model for a two-port network.
B fe
h i
1/h
oe
i
C
-
+
CE
v
BE
v
re
h v
CE
_
+
B
E
C
-
+
E
B
ie
h
i
The small-signal model is mathematically valid only for signals with small amplitudes. But
this model is so useful that is often used for signals with amplitudes approaching those of
Q-point parameters by using average values of h parameters. h parameters are given in
the manufacturers spec sheets for each BJT. It should not be surprising to note that even in
a given BJT, h parameter can vary substantially depending on manufacturing statistics,
operating temperature, etc. Manufacturers spec sheets list these h parameters and give
the minimum and maximum values. Traditionally, the geometric mean of the minimum and
maximum values are used as the average value in design (see the table below).
Since h
fe
= i
C
/i
B
and BJT = i
C
/i
B
, is sometimes called h
FE
in manufacturers spec
sheets and has a value quite close to h
fe
. In most electronic text books, , h
FE
and h
fe
are
used interchangeably.
Typical hybrid parameters of a general-purpose 2N3904 NPN BJT
Minimum Maximum Average*
r
= h
ie
(k) 1 10 3
h
re
0.5 10
4
8 10
4
2 10
4
h
fe
100 400 200
h
oe
(S) 1 40 6
r
o
= 1/h
oe
(k) 25 1,000 150
r
e
= h
ie
/h
fe
() 10 25 15
* Geometric mean.
As h
re
is small, it is usually ignored in analytical calculations as it makes analysis much
simpler. This model, called the hybrid- model, is most often used in analyzing BJT circuits.
In order to distinguish this model from the hybrid model, most electronic text books use a
dierent notation for various elements of the hybrid- model:
r
= h
ie
r
o
=
1
h
oe
= h
fe
B fe
h i
1/h
oe
i
C
i
B
ie
h
BE
v
C B
+
_
E
i
C
i
B
C B
+
_
E
v
B
i
r
o
r
BE
=
The above hybrid- model includes a current-controlled current source. A variant of the
hybrid- model can be developed which includes a voltage-controlled current source by noting
(v
BE
= r
i
B
:
i
C
i
B
r
o
m BE
g v
BE
v
C B
E
+
_
i
B
=
v
BE
r
= g
m
v
BE
g
m

r
Transfer conductance
r
e

1
g
m
=
r
Emitter resistance
6.5 FET Small Signal Model
Similar to the BJT, the simple large-signal model of FET (page 127) is sucient for nding
the bias point; but we need to develop a more accurate model for analysis of AC signals.
The main issue is that the FET large signal model indicates that i
D
only depends on v
GS
and is independent of v
DS
in the active state. In reality, i
D
increases slightly with v
DS
in
the active state.
We can develop a small signal model for FET in a manner similar to the procedure described
in detail for the BJT. The FET characteristics equations specify two of the FET parameters,
i
G
and i
D
, in terms of the other two, v
GS
and v
DS
. (Actually FET is simpler than BJT as
i
G
= 0 at all times.) As before, we write the FET parameters as a sum of DC bias value
and a small AC signal, e.g., i
D
= I
D
+ i
D
. Performing a Taylor series expansion, similar
to pages 169 and 170, we get:
i
G
(V
GS
+ v
GS
, V
DS
+ v
DS
) = 0
i
D
(V
GS
+ v
GS
, V
DS
+ v
DS
) = i
D
(V
GS
, V
DS
) +
i
D
v
GS
Q
v
GS
+
i
D
v
DS
Q
v
DS
Since i
G
(V
GS
+v
GS
, V
DS
+v
DS
) = I
G
+i
G
and i
D
(V
GS
+v
GS
, V
DS
+v
DS
) = I
D
+i
D
,
we nd the AC components to be:
i
G
= 0 and i
D
=
i
D
v
GS
Q
v
GS
+
i
D
v
DS
Q
v
DS
Dening
g
m

i
D
v
GS
and r
o

i
D
v
DS
We get:
i
G
= 0 and i
D
= g
m
v
GS
+ r
o
v
DS
v
GS
m
g v
GS
G
i = 0
r
o
i
D
_
+
G D
S
This results in the hybrid- model for
the FET as is shown. Note that the
FET hybrid- model is similar to the BJT
hybrid- model with r
.
6.6 BJT Amplier Circuits
As we have developed dierent models for DC signals (simple large-signal model) and AC
signals (small-signal model), analysis of BJT circuits follows these steps:
DC biasing analysis: Assume all capacitors are open circuit. Analyze the transistor circuit
using the simple large signal mode as described in page 114.
AC analysis:
1) Kill all DC sources
2) Assume coupling capacitors are short circuit. The eect of these capacitors is to set a
lower cut-o frequency for the circuit. This is analyzed in the last step.
3) Inspect the circuit. If you identify the circuit as a prototype circuit, you can directly use
the formulas for that circuit. Otherwise go to step 4.
4) Replace the BJT with its small signal model.
5) Solve for voltage and current transfer functions and input and output impedances (node-
voltage method is the best).
6) Compute the cut-o frequency of the amplier circuit.
Several standard BJT amplier congurations are discussed below and are analyzed. For
completeness, circuits include standard bias resistors R
1
and R
2
. For bias congurations
that do not utilize these resistors (e.g., current mirror), simply set R
B
= R
1
R
2
.
6.6.1 Common Collector Amplier (Emitter Follower)
R
E
R
2
V
CC
v
i
v
o
R
1
c
C
DC analysis: With the capacitors open circuit, this circuit is the
same as our good biasing circuit of page 162 with R
C
= 0. The
bias point currents and voltages can be found using procedure
of pages 162-164.
AC analysis: To start the analysis, we kill all DC sources:
R
E
v
o
R
1
R
2
v
i
R
E
R
2
v
i
v
o
R
1
CC
V = 0
c
C C
E
c
C
B
We can combine R
1
and R
2
into R
B
(same resistance that we encountered in the biasing
analysis) and replace the BJT with its small signal model:
v
i
R
B
R
E
i
B
o
v
v
i
i
C
i
B
v
o
R
E
C
c
BE
v
C
c
r
r
o
r
o

B

B
B
C
E
R
B
C
+
_
B
E
i
i
The gure above shows why this is a common collector conguration: the collector is common
between the input and output AC signals. We can now proceed with the analysis. Node
voltage method is usually the best approach to solve these circuits. For example, the above
circuit has only one node equation for node at point E with a voltage v
o
:
v
o
v
i
r
+
v
o
0
r
o
i
B
+
v
o
0
R
E
= 0
Because of the controlled source, we need to write an auxiliary equation relating the control
current (i
B
) to node voltages:
i
B
=
v
i
v
o
r
Substituting the expression for i

B
in our node equation, multiplying both sides by r
, and
collecting terms, we get:
v
i
(1 + ) = v
o
_
1 + + r
_
1
r
o
+
1
R
E
__
= v
o
_
1 + +
r
r
o
R
E
_
Amplier Gain can now be directly calculated:
A
v

v
o
v
i
=
1
1 +
r
(1 + )(r
o
R
E
)
Unless R
E
is very small (tens of ), the fraction in the denominator is quite small compared
to 1 and A
v
1.
To nd the input impedance, we calculate i
i
by KCL:
i
i
= i
1
+ i
B
=
v
i
R
B
+
v
i
v
o
r

Since v
o
v
i
, we have i
i
= v
i
/R
B
or
R
i

v
i
i
i
= R
B
Note that R
B
is the combination of our biasing resistors R
1
and R
2
. With alternative biasing
schemes which do not require R
1
and R
2
(and, therefore, R
B
), the input resistance of
the emitter follower circuit will become large. In this case, we cannot use v
o
v
i
. Using the
full expression for v
o
from above, the input resistance of the emitter follower circuit becomes:
R
i

v
i
i
i
= R
B
[r
+ (R
E
r
o
)(1 + )]
which is quite large (hundreds of k to several M) for R
B
. Such a circuit is in fact
the rst stage of the 741 OpAmp.
The output resistance of the common collector amplier (in fact for all transistor ampliers)
is somewhat complicated because the load can be congured in two ways (see gure): First,
R
E
, itself, is the load. This is the case when the common collector is used as a current
amplier to raise the power level and to drive the load. The output resistance of the circuit
is R
o
as is shown in the circuit model. This is usually the case when values of R
o
and A
i
(current gain) is quoted in electronic text books.
R
2
V
CC
v
i
v
o
R
L
R
1
C
c
E
= R
E
R is the Load
R
E
R
2
V
CC
v
i
v
o
R
1
C
c
R
L
Separate Load
v
i
R
B
i
B
o
v
R
E
R
o
C
c B
C
E
r
r
o
B
i
v
i
R
B
i
B
C
c
R
E
o
R
B
C
E
r
r
o
B
o
v
R
L
i
Alternatively, the load can be placed in parallel to R
E
. This is done when the common
collector amplier is used as a buer (A
v
1, R
i
large). In this case, the output resistance
is denoted by R
o
(see gure). For this circuit, BJT sees a resistance of R
E
R
L
. Obviously,
if we want the load not to aect the emitter follower circuit, we should use R
L
to be much
larger than R
E
. In this case, little current ows in R
L
which is ne because we are using
this conguration as a buer and not to amplify the current and power. As such, value of
R
o
or A
i
does not have much use.
v
i
R
B
i
B
i
T
v
T
C
c
B
R
o
r
o
B
r
E
C
i
+
When R
E
is the load, the output resistance can
be found by killing the source (short v
i
) and nd-
ing the Thevenin resistance of the two-terminal
network (using a test voltage source).
KCL: i
T
= i
B
+
v
T
r
o
i
B
KVL (outside loop): r
i
B
= v
T
Substituting for i
B
from the 2nd equation in the rst and rearranging terms we get:
R
o

v
T
i
T
=
(r
o
) r
(1 + )(r
o
) + r
Since, (1 + )(r
o
) r
, the expression for R

o
simplies to
R
o

(r
o
) r
(1 + )(r
o
)
=
r
(1 + )

r
= r
e
As mentioned above, when R
E
is the load the common collector is used as a current ampli-
er to raise the current and power levels . This can be seen by checking the current gain
in this amplier: i
o
= v
o
/R
E
, i
i
v
i
/R
B
and
A
i

i
o
i
i
=
R
B
R
E
v
i
R
B
i
B
C
c
B
r
o
R
E
i
T
v
T
R
o
B
r
E
C
i
+
v
i
R
B
i
B
i
T
v
T
C
c
B
r
o
R
o
B
r
E
C
i
+
We can calculate R
o
, the output resistance
when an additional load is attached to the cir-
cuit (i.e., R
E
is not the load) with a similar
procedure: we need to nd the Thevenin re-
sistance of the two-terminal network (using a
test voltage source).
We can use our previous results by noting that
we can replace r
o
and R
E
with r
o
= r
o
R
E
which results in a circuit similar to the case
with no R
L
. Therefore, R
o
has a similar ex-
pression as R
o
if we replace r
o
with r
o
:
R
o

v
T
i
T
=
(r
o
) r
(1 + )(r
o
) + r
In most circuits, (1 + )(r
o
) r
(unless we choose a small value for R

E
) and R
o
r
e
In summary, the general properties of the common collector amplier (emitter follower)
include a voltage gain of unity (A
v
1), a very large input resistance R
i
R
B
(and can
be made much larger with alternate biasing schemes). This circuit can be used as buer for
matching impedance, at the rst stage of an amplier to provide very large input resistance
(such in 741 OpAmp). The common collector amplier can be also used as the last stage
of some amplier system to amplify the current (and thus, power) and drive a load. In this
case, R
E
is the load, R
o
is small: R
o
= r
e
and current gain can be substantial: A
i
= R
B
/R
E
.
Impact of Coupling Capacitor:
Up to now, we have neglected the impact of the coupling capacitor in the circuit (assumed
it was a short circuit). This is not a correct assumption at low frequencies. The coupling
capacitor results in a lower cut-o frequency for the transistor ampliers. In order to nd the
cut-o frequency, we need to repeat the above analysis and include the coupling capacitor
impedance in the calculation. In most cases, however, the impact of the coupling capacitor
and the lower cut-o frequency can be deduced be examining the amplier circuit model.
+
V L
o
I
o
+
i
i
+
o
AV
i
i
V
c
Voltage Amplifier Model
C
Z
R
+
V
R Consider our general model for any
amplier circuit. If we assume that
coupling capacitor is short circuit
(similar to our AC analysis of BJT
amplier), v
i
= v
i
.
When we account for impedance of the capacitor, we have set up a high pass lter in the
input part of the circuit (combination of the coupling capacitor and the input resistance of
the amplier). This combination introduces a lower cut-o frequency for our amplier which
is the same as the cut-o frequency of the high-pass lter:
l
= 2 f
l
=
1
R
i
C
c
Lastly, our small signal model is a low-frequency model. As such, our analysis indicates
that the amplier has no upper cut-o frequency (which is not true). At high frequencies,
the capacitance between BE , BC, CE layers become important and a high-frequency small-
signal model for BJT should be used for analysis. You will see these models in upper division
courses. Basically, these capacitances results in amplier gain to drop at high frequencies.
PSpice includes a high-frequency model for BJT, so your simulation should show the upper
cut-o frequency for BJT ampliers.
6.6.2 Common Emitter Amplier
R
C
V
CC
R
1
v
o
v
i
C
c
R
2
R
C
V
CC
R
1
v
o
v
i
C
c
C
b R
E
R
2
Good Bias using a
bypass capacitor
Poor Bias
DC analysis: Recall that an emitter resis-
tor is necessary to provide stability of the
bias point. As such, the circuit congura-
tion as is shown has as a poor bias. We
need to include R
E
for good biasing (DC
signals) and eliminate it for the AC sig-
nals. The solution is to include an emitter
resistance and use a bypass capacitor to
short it out for AC signals as is shown.
For this new circuit and with the capacitors open circuit, this circuit is the same as our
good biasing circuit of page 162. The bias point currents and voltages can be found using
procedure of pages 162-164.
AC analysis: To start the analysis, we kill all DC sources, short out C
b
(which shorts out
R
E
), combine R
1
and R
2
into R
B
, and replace the BJT with its small signal model. We
see that the emitter is now common between the input and output AC signals (thus, the
common emitter amplier). Examination of the circuit shows that:
v
i
R
B
i
B
o
v
C
c
R
o
R
C
R
o
B
E
C
r
B
o
r
i
v
i
= r
i
B
v
o
= (R
C
r
o
) i
B
A
v

v
o
v
i
=

r
(R
C
r
o
)

r
R
C
=
R
C
r
e
R
i
= R
B
r
The negative sign in A

v
indicates a 180
phase shift between the input and output signals.

This circuit has a large voltage gain but has a medium value for the input resistance.
As with the emitter follower circuit, the load can be congured in two ways: 1) R
C
is the
load; or 2) the load is placed in parallel to R
C
. The output resistance can be found by killing
the source (short v
i
) and nding the Thevenin resistance of the two-terminal network. For
this circuit, we see that if v
i
= 0 (killing the source), i
B
= 0. In this case, the strength of
the dependent current source would be zero and this element would become an open circuit.
Therefore,
R
o
= r
o
R
o
= R
C
r
o
Lower cut-o frequency: Both the coupling and bypass capacitors contribute to setting
the lower cut-o frequency for this amplier, both act as a high-pass lter with:
l
(coupling) = 2 f
l
=
1
R
i
C
c
l
(bypass) = 2 f
l
=
1
R
E
C
b
where R
E
R
E
r
e
Note that usually R
E
r
e
and, therefore, R
E
r
e
.
In the case when these two frequencies are far apart, the cut-o frequency of the amplier
is set by the larger cut-o frequency. i.e.,
l
(bypass)
l
(coupling)
l
= 2 f
l
=
1
R
i
C
c
l
(coupling)
l
(bypass)
l
= 2 f
l
=
1
R
E
C
b
When the two frequencies are close to each other, there is no exact analytical formulas, the
cut-o frequency should be found from simulations. An approximate formula for the cut-o
frequency (accurate within a factor of two and exact at the limits) is:
l
= 2 f
l

1
R
i
C
c
+
1
R
E
C
b
6.6.3 Common Emitter Amplier with Emitter resistance
R
1
R
C
R
2
C
c
v
i
R
E
v
o
V
CC
A problem with the common emitter amplier is that its gain
depend on BJT parameters: A
v
(/r
)R
C
. Some form of
feedback is necessary to ensure stable gain for this amplier.
One way to achieve this is to add an emitter resistance. Recall
impact of negative feedback on OpAmp circuits: we traded gain
for stability of the output. Same principles apply here.
DC analysis: With the capacitors open circuit, this circuit is the
same as our good biasing circuit of page 162. The bias point
currents and voltages can be found using procedure of pages
162-164.
AC analysis: To start the analysis, we kill all DC sources, combine R
1
and R
2
into R
B
and
replace the BJT with its small signal model. Analysis is straight forward using node-voltage
method.
1
C
v
i
i
C
i
B v
o
BE
v
R
E
R
C
R
B
+
_
B
E
C
B
r
o
i
v
E
v
i
r
+
v
E
R
E
i
B
+
v
E
v
o
r
o
= 0
v
o
R
C
+
v
o
v
E
r
o
+ i
B
= 0
i
B
=
v
i
v
E
r
(Controlled source aux. Eq.)

Substituting for i
B
in the node equations and noting 1 + , we get :
v
E
R
E
+
v
E
v
i
r
+
v
E
v
o
r
o
= 0
v
o
R
C
+
v
o
v
E
r
o
v
E
v
i
r
= 0
Above are two equations in two unknowns (v
E
and v
o
). Adding the two equation together
we get v
E
= (R
E
/R
C
)v
o
and substituting that in either equations we can nd v
o
. Using
r
/ = r
e
, we get:
A
v
=
v
o
v
i
=
R
C
r
e
(1 + R
C
/r
o
) + R
E
(1 + r
e
/r
o
)

R
C
r
e
(1 + R
C
/r
o
) + R
E
where we have simplied the equation noting r
e
r
o
. For most circuits, R
C
r
o
and
r
e
R
E
. In this case, the voltage gain is simply A
v
= R
C
/R
E
.
The input resistance of the circuit can be found from (prove it!)
R
i
= R
B

v
i
i
B
Noting that i
B
= (v
i
v
E
)/r
and v
E
= (R
E
/R
C
)v
o
= (R
E
/R
C
)A
v
v
i
, we get:
R
i
= R
B

r
1 + A
v
R
C
/R
E
Substituting for A
v
from above (complete expression for A
v
with r
e
/r
o
1), we get:
R
i
= R
B

_
_
R
E
1 + R
C
/r
o
+ r
e
__
For most circuits, R
C
r
o
and r
e
R
E
. In this case, the input resistance is simply
R
i
= R
B
(R
E
).
As before the minus sign in A
v
indicates a 180
phase shift between input and output

signals. Note the impact of negative feedback introduced by the emitter resistance: The
voltage gain is independent of BJT parameters and is set by R
C
and R
E
(recall OpAmp
inverting amplier!). The input resistance is also increased dramatically.
i
B
R
E
v
T
i
T
i
1
i
2
R
o
B
E
B
r
o
C
i
+
i
B
R
E
R
C
v
T
i
T
R
o
i
1
i
2
B
E
B
r
o
C
i
+
As with the emitter follower circuit, the load can

be congured in two ways: 1) R
C
is the load. 2)
Load is placed in parallel to R
C
. The output re-
sistance can be found by killing the source (short
v
i
) and nding the Thevenin resistance of the
two-terminal network (by attaching a test voltage
source to the circuit).
Resistor R
B
drops out of the circuit because it is
shorted out. Resistors r
and R
E
are in parallel.
Therefore, i
1
= (r
/R
E
)i
B
and by KCL, i
2
=
( + 1 + r
/R
E
)i
B
. Then:
i
T
= i
B
i
1
= i
B
_
1 +
r
R
E
_
v
T
= i
B
r
i
2
r
o
= i
B
_
r
o
_
+ 1 +
r
R
E
_
+ r
_
Then:
R
o
=
v
T
i
T
= r
o
+ R
E
1 + r
o
/r
e
1 + R
E
/r

where we have used r
/ = r
e
. Generally r
o
r
e
(rst approximation below) and for most
circuit, R
E
r
(second approximation) leading to

R
o
r
o
+ r
o
R
E
/r
e
1 + R
E
/r
r
o
+
R
E
r
o
r
e
= r
o
_
R
E
r
e
+ 1
_
Value of R
o
can be found by a similar procedure. Alternatively, examination of the circuit
shows that
R
o
= R
C
R
o
R
C
Lower cut-o frequency: The coupling capacitor together with the input resistance of
the amplier lead to a lower cut-o frequency for this amplier (similar to emitter follower).
The lower cut-o frequency is given by:
l
= 2 f
l
=
1
R
i
C
c
R
1
R
C
C
c
v
i
v
o
V
CC
R
2
R
E1
C
b
R
E2
A Possible Biasing Problem: The gain of the common
emitter amplier with the emitter resistance is approximately
R
C
/R
E
. For cases when a high gain (gains larger than 5-10) is
needed, R
E
may be become so small that the necessary good
biasing condition, V
E
= R
E
I
E
> 1 V cannot be fullled. The
solution is to use a by-pass capacitor as is shown. The AC signal
sees an emitter resistance of R
E1
while for DC signal the emitter
resistance is the larger value of R
E
= R
E1
+R
E2
. Obviously for-
mulas for common emitter amplier with emitter resistance can
be applied here by replacing R
E
with R
E1
as in deriving the am-
plier gain, and input and output impedances, we short the
bypass capacitor so R
E2
is eectively removed from the circuit.
The addition of by-pass capacitor, however, modies the lower cut-o frequency of the circuit.
Similar to a regular common emitter amplier with no emitter resistance, both the coupling
and bypass capacitors contribute to setting the lower cut-o frequency for this amplier.
Similarly we nd that an approximate formula for the cut-o frequency (accurate within a
factor of two and exact at the limits) is:
l
= 2 f
l
=
1
R
i
C
c
+
1
R
E
C
b
where R
E
R
E2
(R
E1
+ r
e
)
6.6.4 Common Base Amplier
R
C
V
CC
R
E
V
EE
C
c
v
i
v
o
By setting the signal ground at the base of the BJT, one arrives
at the common base amplier (the input sginal is still applied
between the base and the emitter). While it is possible to bias
this conguration with a voltage divider self-bias, the preferred
method is to bias this amplier with two power supplies (or a
current mirror). The bias point currents and voltages can be
found using procedure of pages 164-165.
AC analysis: To start the analysis, we kill all DC sources and
replace the BJT with its small signal model. We see that base
is now common between the input and output AC signals (thus,
the common base amplier).
i
B
B
R
C
R
E
v
i
c
C
v
o
B
E
C
r
i
r
o
v
i
c
C
B
v
o
R
C
R
E
i
B
E C
B
i
i
i
r
o
r
=
Using node voltage method and noting i
B
= v
i
/r
:
v
o
R
C
+ i
B
+
v
o
v
i
r
o
= 0
v
o
_
1
R
C
+
1
r
o
_
+ v
i
_
1
r
o
_
= 0
v
o
1
R
C
r
o
v
i
A
v

v
o
v
i
=

r
(R
C
r
o
)

r
R
C
=
R
C
r
e
which is exactly the gain of the common emitter amplier (with no emitter resistor) except
for the positive sign. This should not be surprising as compared to a common emitter, we
have switched the terminals of the input signal (leading to the change in the sign of A
v
) and
the output voltage is v
CB
= v
CE
v
BE
v
CE
because of the high gain of the amplier.
The input resistance of the circuit can be found by nding i
i
from the circuit above and
computing v
i
/i
i
to be
R
i
=
r
(r
o
+ R
C
)
r
+ R
C
+ r
o
(1 + )

r
(r
o
+ R
C
)
r
o
(1 + )

r
1 +

r
= r
e
In the approximation, we rst used the fact that r
+ R
C
r
o
(1 + ) and then R
C
r
o
.
Note that the input resistance is quite small.
As before, the load can be congured in two ways: 1) R
C
is the load; or 2) load is placed
in parallel to R
C
. The output resistance can be found by killing the source (short v
i
) and
nding the Thevenin resistance of the two-terminal network. For this circuit, we see that
if v
i
= 0 (killing the source), i
B
= 0. In this case, the strength of the dependent current
source would be zero and this element would become an open circuit. In addition, emitter
would be eectively grounded and resistors R
E
and r
are eectively shorted out of the

circuit. Therefore,
R
o
= r
o
R
o
= R
C
r
o
R
C
which are similar to the common amplier with no emitter resistor.
As a whole, this circuit is similar to common emitter amplier with no resistor (large voltage
gain, medium output resistance) but has a very low input resistance (r
e
). As such, it is
rarely used as a voltage amplier (except for very specialized cases).
Following the formula in page 13, the short circuit current-gain of this amplier is:
A
i
=
Z
I
Z
L
+ Z
o
A
v
=
r
e
0 + R
c
R
C
r
e
= 1
Therefore, this circuit has a low input resistance, a medium output resistance and current-
gain of unity and, therefore, is a current buer: It accepts an input signal current with
a low input resistance and deliver nearly equal current to a much higher output resistance.
Common-base ampliers are mostly used as a current buer, typically forming circuits in-
cluding two BJTs (cascode amplier) which are utilized specially in integrated circuits.
6.7 FET Amplier Circuits
As expected, FET ampliers are very similar to the BJT ampliers. There are four basic
FET ampliers: 1) common-drain or source follower (similar to common collector or emitter
follower), 2) common-source (similar to common emitter), 3) common source with a source
resistor (similar to common emitter with an emitter resistor) and common gate (similar to
common base).
The analysis technique are exactly the same: 1) DC-biasing analysis, and 2) AC analysis in
which we replace FET with its small signal model. In fact, by comparing the small signal
model for an FET that that of a BJT, we should be able to nd the answer immediately by
replacing /r
= g
m
in the formulas of the equivalent BJT circuits and then let r
(and
of course, replace R
C
R
D
, R
E
R
S
, and R
B
= R
1
R
2
R
G
= R
1
R
2
). Therefore,
we will only solve the common-source amplier in detail and summarize the results for the
other congurations.
6.7.1 Common Source Amplier
R
1
v
o
v
i
C
c
R
2
R
1
v
o
v
i
C
c
C
b
R
2
R
D
R
D
R
S
V
DD
V
DD
Good Bias using a
bypass capacitor
Poor Bias
DC analysis: Recall that a source resistor
is necessary to provide stability for the bias
point. As such, the circuit conguration as
is shown has a poor bias. We need to in-
clude R
S
for good biasing (DC signals) and
eliminate it for AC signals. The solution
is to include a source resistance and use a
bypass capacitor to short it out for AC
signals similar to the BJT common-emitter
amplier.
AC analysis: To start the analysis, we kill all DC sources, short out C
b
(which shorts out
R
S
), combine R
1
and R
2
into R
G
, and replace the FET with its small signal model. We see
that the source is now common between the input and output AC signals (thus, the common
source amplier). Examination of the circuit shows that:
G
i = 0
v
GS
m
g v
GS
r
o
v
i
R
G
R
o
R
o
v
o
C
c
R
D
_
+
S
D G
v
i
= v
GS
v
o
= (R
D
r
o
) g
m
v
GS
A
v

v
o
v
i
= g
m
(R
D
r
o
) g
m
R
D
R
i
= R
G
R
o
= r
o
R
o
= R
D
r
o
which are exactly the same as formulas for a BJT common emitter amplier if we let /r
=
g
m
and r
. Note that as an FET can be biased with large (M) R

1
and R
2
(see
page 167), the input resistance of this amplier is considerably larger than that of a common
emitter amplier and can even be made to be innitely large (resistance of the Gate insulator)
by removing R
G
and biasing the circuit with two voltage supplies or a current mirror.
Lower cut-o frequency: As R
i
is very large, the lower cut-o frequency is set by the
bypass capacitor (unless C
c
is chosen to be very small) .
l
=
l
(bypass) = 2 f
l
=
1
R
S
C
b
where R
S
R
S

1
g
m
Note that usually R
S
1/g
m
and, therefore, R
S
1/g
m
.
6.7.2 Common Source Amplier with Source resistance
R
1
v
o
v
i
C
c
R
D
V
DD
R
S
R
2
Similar to common-emitter amplier, the common source am-
plier gain depends on the FET parameters (g
m
). Addition of
a source resistance will remove this dependency (similar to the
common emitter amplier with an emitter resistor). Details of
the AC analysis is left as an exercise. The parameters of this
amplier are:
A
v
=
g
m
R
D
1 + g
m
R
S

R
D
R
S
R
i
= R
G
R
o
= 1/g
m
r
o
R
o
= R
D
R
o
R
D
l
= 2 f
l
=
1
R
i
C
c
Similar to the common-emitter amplier, the gain is set by R
D
and R
S
and is independent of
the FET parameters. The input resistance of the circuit is large (much larger than common
emitter amplier because R
1
and R
2
can be large).
6.7.3 Common Drain Amplier
R
1
v
i
C
c
R
2
R
S
v
o
V
DD
This circuit is similar to the common-collector amplier (or the
emitter follower). Details of the AC analysis is left as an exercise.
The parameters of this amplier are:
A
v
=
g
m
r
o
R
S
r
o
+ (1 + g
m
r
o
)R
S
1
R
i
= R
G
R
o
= 1/g
m
r
o
R
o
= R
S
R
o
R
S
l
= 2 f
l
=
1
R
i
C
c
Similar to the emitter follower, the source follower is a voltage buer. It is superior to the
emitter follower because of its very large input resistance.
6.7.4 Common Gate Amplier
C
c
v
i
v
o
R
D
R
S
V
DD
V
SS
This circuit is similar to the BJT common-base amplier. De-
tails of the AC analysis is left as an exercise. The parameters of
this amplier are:
A
v
= g
m
(R
D
r
o
) g
m
R
D
R
i
=
R
S
(r
o
+ R
D
)
r
o
+ R
D
+ (1 + g
m
r
o
)R
S
R
S
(r
o
+ R
D
)
(1 + g
m
r
o
)R
S
r
o
g
m
r
o
=
1
g
m
R
o
= r
o
R
o
= R
D
r
o
R
D
l
= 2 f
l
=
1
R
i
C
c
Note that in the approximation for R
i
, we rst used the fact that r
o
+ R
D
(1 + g
m
r
o
)R
S
and then R
D
r
o
.
Similar to the common-base amplier, this is a poor voltage amplier because of its low input
resistance but has a short-circuit current gain of unity, low input impedance, and medium
output impedance and can be used as a current buer.
Summary of Transistor Ampliers
R
E
R
2
V
CC
v
i
v
o
R
1
c
C
Common Collector (Emitter Follower):
A
v
=
(R
E
r
o
)(1 + )
r
+ (R
E
r
o
)(1 + )
1
R
i
= R
B
[r
+ (R
E
r
o
)(1 + )] R
B
R
o
=
(r
o
) r
(1 + )(r
o
) + r
= r
e
2 f
l
=
1
R
i
C
c
R
o
=
(r
o
) r
(1 + )(r
o
) + r
where r
o
= r
o
R
C
C
V
CC
R
1
R
2
v
o
v
i
C
c
C
b
R
R
E
Common Emitter:
A
v
=

r
(R
C
r
o
)

r
R
C
=
R
C
r
e
R
i
= R
B
r
R
o
= r
o
R
o
= R
C
r
o
R
C
2 f
l
=
1
R
i
C
c
+
1
R
E
C
b
where R
E
R
E
r
e
Common Emitter with Emitter Resistance:
R
1
R
C
R
2
C
c
v
i
R
E
v
o
V
CC
A
v
=
R
C
r
e
(1 + R
C
/r
o
) + R
E

R
C
r
e
+ R
E

R
C
R
E
R
i
= R
B

_
_
R
E
1 + R
C
/r
o
+ r
e
__
R
B
R
E
R
B
R
o
r
o
+ r
o
R
E
/r
e
1 + R
E
/r
r
o
_
R
E
r
e
+ 1
_
R
o
= R
C
R
o
R
C
and 2 f
l
=
1
R
i
C
c
Common Base Amplifer:
R
C
V
CC
R
E
V
EE
C
c
v
i
v
o
A
v
=

r
(R
C
r
o
)
R
C
r
e
R
i
=
r
(r
o
+ R
C
)
r
+ R
C
+ r
o
(1 + )
r
e
R
o
= r
o
R
o
= R
C
r
o
R
C
and 2 f
l
=
1
R
i
C
c
R
1
v
i
C
c
R
2
R
S
v
o
V
DD
Common Drain (Source Follower):
A
v
=
g
m
r
o
R
S
r
o
+ (1 + g
m
r
o
)R
S
1
R
i
= R
G
R
o
= 1/g
m
r
o
R
o
= R
S
R
o
R
S
l
= 2 f
l
=
1
R
i
C
c
R
1
v
o
v
i
C
c
C
b
R
2
R
D
R
S
V
DD
Common Source:
A
v
= g
m
(R
D
r
o
) g
m
R
D
R
i
= R
G
R
o
= r
o
R
o
= R
D
r
o
l
=
l
(bypass) = 2 f
l
=
1
R
S
C
b
where R
S
R
S

1
g
m
Common Source with Source Resistance:
R
1
v
o
v
i
C
c
R
D
V
DD
R
S
R
2
A
v
=
g
m
R
D
1 + g
m
R
S

R
D
R
S
R
i
= R
G
R
o
= 1/g
m
r
o
R
o
= R
D
R
o
R
D
l
= 2 f
l
=
1
R
i
C
c
Common Gate Amplifer:
C
c
v
i
v
o
R
D
R
S
V
DD
V
SS
A
v
= g
m
(R
D
r
o
) g
m
R
D
R
i
=
R
S
(r
o
+ R
D
)
r
o
+ R
D
+ (1 + g
m
r
o
)R
S
1
g
m
R
o
= r
o
R
o
= R
D
r
o
R
D
l
= 2 f
l
=
1
R
i
C
c
If bias resistors are not present (e.g., bias with current mirror), let R
B
or R
G
in the
full expression for R
i
.
6.8 Exercise Problems
In circuit design, use 5% commercial resistor and capacitor values (1, 1.1, 1.2, 1.3, 1.5, 1.6,
1.8, 2, 2.2, 2.4, 2.7, 3., 3.3, 3.6, 3.9, 4.3, 4.7, 5.1, 5.6, 6.2, 6.8, 7.5, 8.2, 9.1 10
n
where n is
an integer). Use Si BJTs, with = 200,
min
= 100, r
= 5 k, r
o
= 100 k.
Problem 1. Show that this circuit is a stable biasing scheme.
Problem 2 to 5. Compute I
o
assuming identical transistors.
Problem 6 to 8: Find the bias point and AC amplier parameters of these circuits (Man-
ufacturers spec sheets give: = 200, r
= 5 k, r
o
= 100 k).
C
I
R
B
R
C
V
CC
I
ref
I
o
Q1 Q2
Q3
V
CC
V
EE
I
o I
ref
Q1 Q2
V
SS
I
ref
I
o
Q1 Q2
Q3
V
EE
Problem 1 Problem 2 Problem 3 Problem 4
I
ref
I
o
Q1 Q2
Q3
V
SS
v
o
v
i
0.47 F
18k
22k 1k
9 V
v
i
v
o
47 F
4.7 F
270
240
15 V
34 k 1 k
5.9 k
v
o
v
i
16 V
1.5k
6.2k
510nF
30k
510
Problem 9: Design a BJT amplier with a gain of 4 and a lower cut-o frequency of 100 Hz.
The Q point parameters should be I
C
= 3 mA and V
CE
= 7.5 V.
Problem 10: Design a BJT amplier with a gain of 10 and a lower cut-o frequency of
100 Hz. The Q point parameters should be I
C
= 3 mA and V
CE
= 7.5 V. A power supply of
15 V is available.
Problem 11. Design a BJT amplier with a gain of 5 and a lower cut-o frequency of 10 Hz,
powered by a 16 V supply. Set the Q-point parameters to be V
CE
= 10 V and I
c
= 5 mA.
Problem 12. Consider the BJT circuit below with R
1
= 47 k, R
2
= 39 k, R
E
=
1.5 k, R
L
= 50 k, C
1
= 100 nF, C
2
= 0.47 F, and V
CC
= 15 V. An input signal with
v
i
= cos(5000t) is applied to the circuit. Calculate expressions for voltages v
B
, v
E
, and v
o
(include both AC and DC parts in the expression for each voltage). Manufacturers spec
sheets give: = 200, r
= 5 k, r
o
= 100 k.
Problems 13 to 16: Find the bias point and AC amplier parameters of these circuits
(Manufacturers spec sheets give: = 200, r
= 5 k, r
o
= 100 k).
Problems 17. Find the bias point and AC amplier parameters of these circuits (Manufac-
turers spec sheets give K = 0.25 mA/V
2
and V
t
= 1 V, g
m
= 0.25 mA/V, and r
o
= 100 k).
Problems 18. Find the bias point and AC amplier parameters of these circuits (Manufac-
2
and V
t
= 3 V, g
m
= 0.2 mA/V, and r
o
= 100 k).
Problem 19. Find the bias point and AC amplier parameters of these circuits (Manufac-
2
and V
t
= 4 V, g
m
= 0.2 mA/V, and r
o
= 100 k).
1
C
R
1
R
2 E
R
L
R
2
C
V
CC
i
v
B
E
v
o
v
v
v
i
v
o
47 F
0.33 F
15 V
2 k 39 k
510
6.2 k
510
v
o
v
i
0.47 F
18k
22k 1k
9 V
v
i v
o
0.47 F
18k
22k 1k
9 V
v
o
v
i
1k
4 V
5 V
v
i
v
o
C
c
1k
110k 2k
51k
12 V
v
i
v
o
C
c
C
b
1M
1k 1M
1k
20 V
v
i
v
o
C
c
500k
1.3M
10k
18 V
Problems 20 to 22: Find the bias point and AC amplier parameters of these circuits
= 5 k, r
o
= 100 k).
v
i
v
o
0.47 F
4.7 F
6.2k
Q1
33k
22k
18k
15 V
1k
Q2
2k
500
v
i
v
o
4.7 F
6.2k 500
15 V
1k
Q2
Q1
2k 33k
v
i
v
o
4.7 F
Q1
510 2.7k
18 V
510
Q2
1.5k 3.6k 15k
Problem 20 Problem 21 Problem 22
6.9 Solution to Selected Exercise Problems
Problem 1. Show that this is a stable biasing scheme.
This is another stable biasing scheme which eliminates R
B
thereby, greatly reducing the
input resistance and increasing the value of the coupling capacitor (or lowering the cut-o
frequency). This scheme uses R
c
as the feedback resistor.
R
B
C
I
R
C
1
I
V
CC
We assume that the BJT is in the active-linear state. Since I
B
I
C
,
by KCL I
1
= I
C
+ I
C
I
C
. Then:
BE-KVL: V
CC
= R
C
I
C
+ R
B
I
B
+ V
BE
= (R
C
+ R
B
/) I
C
+ V
BE
I
C
=
V
CC
V
BE
R
C
+ R
B
/
If, R
B
/ R
C
or R
B
R
C
, we will have (setting V
BE
= V
):
I
C
=
V
CC
V
R
C
Since I
C
is independent of , the bias point is stable. We still need to prove that the BJT
is in the active-linear state. We write a KVL through BE and CE terminals:
V
CE
= R
B
I
B
+ V
BE
= R
B
I
B
+ V
> V
Since V
CE
> V
, BJT is indeed in the active state.

To see the negative feedback eect, rewrite BE-KVL as:
I
B
=
V
CC
V
R
C
I
C
R
B
Suppose that the circuit is operating and BJT is increased (e.g., an increase in the tem-
perature). In this case I
C
will increase which raises the voltage across resistor R
C
(R
C
I
C
).
From the above equation, this will lead to a reduction in I
B
which, in turn, will decrease
I
C
= I
B
and compensate for any increase in . If BJT is decreased (e.g., a decrease
in the temperature), I
C
will decrease which reduces the voltage across resistor R
C
(R
C
I
C
).
From the above equation, this will lead to an increase in I
B
which, in turn, will increase
I
C
= I
B
and compensate for any decrease in .
Note: The drawback of this bias scheme is that the allowable AC signal on V
CE
is small.
Since V
CE
V
CE
> V
in order for the BJT to remain in active state, we nd the amplitude

of AC signal, V
CE
< R
B
I
B
= (R
B
/)I
C
. Since, R
B
/ R
C
for bias stability thus,
V
CE
R
C
I
C
. This is in contrast with the standard biasing with emitter resistor in which
V
CE
is comparable to R
C
I
C
. Also, there is a feedback for the AC signals.
Problem 2. Compute I
o
i
C
i
C
i
B
i
B
i
B3
2i
B
I
ref
I
o
Q1 Q2
Q3
V
V
CC
EE
Because both bases and emitters of the transistors Q1 and Q2
BE1
= v
BE2
. As BJTs
B
(i
B1
= i
B2
= i
B
)
E
= i
E1
= i
E2
and i
C
= i
C1
= i
C2
.
Using i
C
= i
B
and i
E
= ( + 1)i
B
to illustrate the impact
of :
i
B
=
i
E
+ 1
I
o
= i
C
=
i
E
+ 1
KCL: i
E3
= 2i
B
=
2i
E
+ 1
i
B3
=
i
E3
+ 1
=
2i
E
( + 1)
2
KCL: I
ref
= i
C
+ i
B3
=
i
E
+ 1
+
2i
E
( + 1)
2
I
o
I
ref
=

+ 2/( + 1)
=
1
1 + 2/( + 1)

1
1 + 2/
2
As can be seen, this is a better current mirror than our simple version as I
o
I
ref
with an
accuracy of 2/
2
. Similar to our simple current-mirror circuit, I
ref
can be set by using a
resistor R
c
.
o
I
o I
ref
Q1 Q2
V
SS
This is the MOS version of our simple current mirror. Be-
cause both gates and sources of the transistors Q1 and Q2
GS1
= v
GS2
. The
drain of Q1 is connected to its gate: v
DS1
= v
GS1
. Therefore,
v
DS1
= v
GS1
> v
GS1
V
t
, Q1 will be in the active state with
I
ref
= i
D1
= K(v
GS1
V
t
)
2
. If Q2 is also in active state, then
I
o
= i
D2
= K(v
GS2
V
t
)
2
. Since, v
GS1
= v
GS2
, then I
o
= I
ref
.
Note that as opposed to the BJT version, there is no 2/ eect here. However, a sucient
voltage should be applied to Q2 to ensure that it is in the active state.
o
i
C
i
E3
i
C
i
B
i
B
2i
B
i
B3
I
ref
I
o
Q1 Q2
Q3
V
EE
Because both bases and emitters of the transistors Q1 and Q2
BE1
= v
BE2
. As BJTs
B
(i
B1
= i
B2
= i
B
)
E
= i
E1
= i
E2
and i
C
= i
C1
= i
C2
.
Using i
C
= i
B
and i
E
= ( + 1)i
B
to illustrate the impact
of :
i
B
=
i
E
+ 1
KCL: i
E3
= 2i
B
+ i
c
=
2i
E
+ 1
+
i
E
+ 1
=
+ 2
+ 1
i
E
i
B3
=
i
E3
+ 1
=
+ 2
( + 1)
2
i
E
KCL: I
ref
= i
C
+ i
B3
=
i
E
+ 1
+
+ 2
( + 1)
2
i
E
=
( + 1) + + 2
( + 1)
2
i
E
I
o
= i
C3
=

+ 1
i
E3
=
( + 2)
( + 1)
2
i
E
I
o
I
ref
=
( + 2)
( + 1) + + 2
=
( + 2)
( + 2) + 2
==
1
1 +
2
( + 2)
1
1 + 2/
2
This circuit is called the Wilson current mirror after its inventor. It has a reduced depen-
dence compared to our simple current mirror and has a greater output impedance compared
to the current mirror of problem 2.
o
I
ref
I
o
Q1 Q2
Q3
V
SS
This is the MOS version of the Wilson current mirror. Solu-
tion is similar to those of Problems 3 and 4. The advantage of
this current mirror over the simple current mirror of Problem
3 is its much larger output resistance.
Problem 6. Find the bias point and AC amplier parameters of this circuit
= 5 k, r
o
= 100 k).
v
o
v
i
0.47 F
18k
22k 1k
9 V
V
CC
V
BB
R
B
R
E
DC analysis:
Replace R
1
and R
2
with their Thevenin equivalent and
proceed with DC analysis (all DC current and voltages
are denoted by capital letters):
R
B
= 18 k 22 k = 9.9 k
V
BB
=
22
18 + 22
9 = 4.95 V
KVL: V
BB
= R
B
I
B
+ V
BE
+ 10
3
I
E
I
B
=
I
E
1 +
=
I
E
201
4.95 0.7 = I
E
_
9.9 10
3
201
+ 10
3
_
I
E
= 4 mA I
C
, I
B
=
I
C
= 20 A
KVL: V
CC
= V
CE
+ 10
3
I
E
V
CE
= 9 10
3
4 10
3
= 5 V
DC Bias summary: I
E
I
C
= 4 mA, I
B
= 20 A, V
CE
= 5 V
AC analysis: The circuit is a common collector amplier. Using the formulas in page 189,
A
v
1
R
i
R
B
= 9.9 k
R
o

r
= 25
f
l
=

l
2
=
1
2R
i
C
c
=
1
2 9.9 10
3
0.47 10
6
= 36 Hz
Problem 7. Find the bias point and AC amplier parameters of this circuit
= 5 k, r
o
= 100 k).
v
i
v
o
47 F
4.7 F
270
240
15 V
34 k 1 k
5.9 k
V
CC
V
BB
R
B
R
C
R =
E
270 + 240 =
510
DC analysis: Replace R
1
and R
2
with their Thevenin equivalent
and proceed with DC analysis (all DC current and voltages are
denoted by capital letters). Since all capacitors are replaced with
open circuit, the emitter resistance for DC analysis is 270+240 =
510 .
R
B
= 5.9 k 34 k = 5.0 k
V
BB
=
5.9
5.9 + 34
15 = 2.22 V
KVL: V
BB
= R
B
I
B
+ V
BE
+ 510I
E
I
B
=
I
E
1 +
=
I
E
201
2.22 0.7 = I
E
_
5.0 10
3
201
+ 510
_
I
E
= 3 mA I
C
, I
B
=
I
C
= 15 A
KVL: V
CC
= 1000I
C
+ V
CE
+ 510I
E
V
CE
= 15 1, 510 3 10
3
= 10.5 V
DC Bias: I
E
I
C
= 3 mA, I
B
= 15 A, V
CE
= 10.5 V
AC analysis: The circuit is a common collector amplier with an emitter resistance. Note
that the 240 resistor is shorted out with the by-pass capacitor. It only enters the formula
for the lower cut-o frequency. Using the formulas in page 189 (with R
E
= 270 ) and
noting r
e
= r
/beta = 25 :
A
v
=
R
C
R
E
=
1, 000
270
= 3.70
R
i
R
B
= 5.0 k R
o
r
o
_
R
E
r
e
+ 1
_
= 1.2 M
The lower cut-o frequency can be found from formula on page 183:
R
E
= R
E2
(R
E1
+ r
e
) = 240 (270 + 25) = 132
f
l
=

l
2
=
1
2R
i
C
c
+
1
2R
E
C
b
=
1
2 5, 000 4.7 10
6
+
1
2 132 47 10
6
= 31.5 Hz
Problem 8. Find the bias point and AC amplier parameters of these circuits
= 5 k, r
o
= 100 k).
v
o
v
i
16 V
1.5k
6.2k
510nF
30k
510
R
2
R
1
V
CC
V
+
V
CC
V
BB
R
B
R
C
R
E
Because the forward bias voltage for BE junction, V
BE
= v
, changes
as the temperature changes, the bias point changes slightly even in
the presence of the R
E
. Although this change is small, in some cases
a diode is added to the the voltage divider self-bias to compensate
for this small changes. Assuming that the BJT is in active state, the
base voltage has to be large enough to forward bias the BE junction
and, therefore, the diode would also be forward biased.
We can nd the Thevenin equivalent of our bias circuit
(see circuit) by noting:
V
BB
= V
oc
=
R
2
R
1
+ R
2
(V
CC
v
) + v
= 2.74 + 0.83v
(V)
R
B
= R
T
= R
1
R
2
= 5.14 k
DC analysis:
BE-KVL: V
BB
= R
B
I
B
+ V
BE
+ 510I
E
2.74 + 0.83v
= 5.14 10
3
I
E
201
+ v
+ 510I
E
I
E
=
2.74 0.17v
536
= 4.9 mA I
C
, I
B
=
I
C
= 24 A
Note that the dependence of I
E
to v
is reduced by a factor of 6 .e.,

I
E
now scales as 2.74 0.17v
instead of 2.74 v
(the case with no

diode).
CE-KVL: V
CC
= 1, 500I
C
+ V
CE
+ 10
3
I
E
V
CE
= 16 2, 100 4.9 10
3
= 5.7 V
AC analysis: Since the diode is forward biased and can be represented by an independent
voltage source, it does not enter the AC analysis (because we short out the DC voltage
sources). As such, this is a common emitter amplier with an emitter resistor. Using the
formulas in page 189:
A
v
=
R
C
R
E
=
1, 500
510
= 2.94
R
i
R
B
= 5.1 k R
o
r
o
_
R
E
r
e
+ 1
_
= 2.14 M
f
l
=

l
2
=
1
2R
i
C
c
= 60.7 Hz
Problem 9: Design a BJT amplier with a gain of 4 and a lower cut-o frequency
of 100 Hz. The Q point parameters should be I
C
= 3 mA and V
CE
= 7.5 V.
R
1
R
C
R
2
C
c
v
i
R
E
v
o
V
CC
V
CC
V
BB
R
B
R
C
R
E
The prototype of this circuit is a common emitter amplier with an
emitter resistance. Using formulas of page 189
|A
v
|
R
C
R
E
= 4
The lower cut-o frequency will set the value of C
c
.
We start with the DC bias: As V
CC
is not given, we need to
choose it. To set the Q-point in the middle of load line, set
V
CC
= 2V
CE
= 15 V. Then, noting I
C
I
E
,:
V
CC
= R
C
I
C
+ V
CE
+ R
E
I
E
15 7.5 = 3 10
3
(R
C
+ R
E
) R
C
+ R
E
= 2.5 k
Values of R
C
and R
E
can be found from the above equation
together with the AC gain of the amplier, A
V
= R
C
/R
E
= 4:
R
C
R
E
= 4 4R
E
+ R
E
= 2.5 k R
E
= 500 , R
C
= 2. k
Commercial values are R
E
= 510 and R
C
= 2 k. Use these commercial values for the
rest of analysis.
We need to check if V
E
> 1 V, the condition for good biasing. V
E
= R
E
I
E
= 510310
3
=
1.5 > 1, it is OK (See next example for the case when V
E
is smaller than 1 V).
We now proceed to nd R
B
and V
BB
. R
B
is found from good bias condition (and trying to
have R
B
as large as possible) and V
BB
from a KVL in BE loop:
R
B
( + 1)R
E
R
B
= 0.1(
min
+ 1)R
E
= 0.1 101 510 = 5.1 k
BE-KVL: V
BB
= R
B
I
B
+ V
BE
+ R
E
I
E
V
BB
= 5.1 10
3
3 10
3
201
+ 0.7 + 510 3 10
3
= 2.28 V
Bias resistors R
1
and R
2
are now found from R
B
and V
BB
:
R
B
= R
1
R
2
=
R
1
R
2
R
1
+ R
2
= 5 k
V
BB
V
CC
=
R
2
R
1
+ R
2
=
2.28
15
= 0.152
R
1
can be found by dividing the two equations: R
1
= 33 k. R
2
is found from the equation
for V
BB
to be R
2
= 5.9 k. Commercial values are R
1
= 33 k and R
2
= 6.2 k.
Lastly, we have to nd the value of the coupling capacitor:
l
=
1
R
i
C
c
= 2 100
Using R
i
R
B
= 5.1 k, we nd C
c
= 3 10
7
F or a commercial values of C
c
= 300 nF.
So, are design values are: R
1
= 33 k, R
2
= 6.2 k, R
E
= 510 , R
C
= 2 k. and
C
c
= 300 nF.
Problem 10: Design a BJT amplier with a gain of 10 and a lower cut-o fre-
quency of 100 Hz. The Q point parameters should be I
C
= 3 mA and V
CE
= 7.5 V.
A power supply of 15 V is available.
R
1
R
C
R
2
C
c
v
i
R
E
v
o
V
CC
The prototype of this circuit is a common emitter amplier with an
emitter resistance. Using formulas of page 184:
|A
v
|
R
C
R
E
= 10
The lower cut-o frequency will set the value of C
c
.
We start with the DC bias: As the power supply voltage is given,
we set V
CC
= 15 V. Then, noting I
C
I
E
,:
V
CC
= R
C
I
C
+ V
CE
+ R
E
I
E
15 7.5 = 3 10
3
(R
C
+ R
E
) R
C
+ R
E
= 2.5 k
Values of R
C
and R
E
can be found from the above equation together with the AC gain of
the amplier A
V
= R
C
/R
E
= 10:
R
C
R
E
= 10 10R
E
+ R
E
= 2.5 k R
E
= 227 , and R
C
= 2.27 k
We need to check if V
E
> 1 V which is the condition for good biasing: V
E
= R
E
I
E
=
227 3 10
3
= 0.69 < 1. Therefore, we need to use a bypass capacitor and modify our
circuits as is shown.
R
1
R
C
C
c
v
i
v
o
V
CC
R
2
R
E1
C
b
R
E2
V
BB
R
B
R + R
E1 E2
R
C
V
CC
For DC analysis, the emitter resistance is R
E1
+ R
E2
while for
AC analysis, the emitter resistance will be R
E1
. Therefore:
DC Bias: R
C
+ R
E1
+ R
E2
= 2.5 k
AC gain: A
v
=
R
C
R
E1
= 10
Above are two equations in three unknowns. A third equation is
derived by setting V
E
= 1 V to minimize the value of R
E1
+R
E2
.
V
E
= (R
E1
+ R
E2
)I
E
R
E1
+ R
E2
=
1
3 10
3
= 333
Now, solving for R
C
, R
E1
, and R
E2
, we nd R
C
= 2.2 k,
R
E1
= 220 , and R
E2
= 110 (All commercial values).
We can now proceed to nd R
B
and V
BB
:
R
B
( + 1)(R
E1
+ R
E2
)
R
B
= 0.1(
min
+ 1)(R
E1
+ R
E2
) = 0.1 101 330 = 3.3 k
KVL: V
BB
= R
B
I
B
+ V
BE
+ R
E
I
E
V
BB
= 3.3 10
3
3 10
3
201
+ 0.7 + 330 3 10
3
= 1.7 V
Bias resistors R
1
and R
2
are now found from R
B
and V
B
B:
R
B
= R
1
R
2
=
R
1
R
2
R
1
+ R
2
= 3.3 k
V
BB
V
CC
=
R
2
R
1
+ R
2
=
1
15
= 0.066
R
1
can be found by dividing the two equations: R
1
= 50 k and R
2
is found from the
equation for V
BB
to be R
2
= 3.6k . Commercial values are R
1
= 51 k and R
2
= 3.6k
Lastly, we have to nd the value of the coupling and bypass capacitors:
R
E
= R
E2
(R
E1
+ r
e
) = 110 (220 + 25) = 76
R
i
R
B
= 3.3 k
l
=
1
R
i
C
c
+
1
R
E
C
b
= 2 100
This is one equation in two unknown (C
c
and C
B
) so one can be chosen freely. Typically
C
b
C
c
as R
i
R
B
R
E
R
E
. This means that unless we choose C
c
to be very small,
the cut-o frequency is set by the bypass capacitor. The usual approach is the choose C
b
based on the cut-o frequency of the amplier and choose C
c
such that cut-o frequency of
the R
i
C
c
lter is at least a factor of ten lower than that of the bypass capacitor. Note that
in this case, our formula for the cut-o frequency is quite accurate (see discussion in page
179) and is
l

1
R
E
C
b
= 2 100
This gives C
b
= 20 F. Then, setting
1
R
i
C
c
1
R
E
C
b
1
R
i
C
c
= 0.1
1
R
E
C
b
R
i
C
c
= 10R
E
C
b
C
c
= 4.7 10
6
= 4.7 F
So, are design values are: R
1
= 50 k, R
2
= 3.6 k, R
E1
= 220 , R
E2
= 110 , R
C
=
2.2 k, C
b
= 20 F, and C
c
= 4.7 F.
An alternative approach is to choose C
b
(or C
c
) and compute the value of the other from
the formula for the cut-o frequency. For example, if we choose C
b
= 47 F, we nd
C
c
= 0.86 F.
Problem 11. Design a BJT amplier with a gain of 5 and a lower cut-o frequency
of 10 Hz, powered by a 16 V supply. Set the Q-point parameters to be V
CE
= 10 V
and I
c
= 5 mA.
Answer: A common-emitter amplier with R
1
= 18 k, R
2
= 2.2 k, R
E
= 200 ,
R
C
= 1.0 k. and C
c
= 10 F.
Problem 12. Consider the BJT circuit below with R
1
= 47 k, R
2
= 39 k,
R
E
= 1.5 k, R
L
= 50 k, C
1
= 100 nF, C
2
= 0.47 F, and V
CC
= 15 V. An input
signal with v
i
= cos(5000t) is applied to the circuit. Calculate the expressions for
voltages v
B
, v
E
, and v
o
. (Include both AC and DC parts in the expression for
each voltage.)
1
C
R
1
R
2 E
R
L
R
2
C
V
CC
i
v
B
E
v
o
v
v
V
CC
V
BB
R
B
R
E
The voltages at Base and Emitter will be the sum of DC
and AC signals, e.g., v
B
= V
B
+v
B
. First we calculate
the DC voltages, V
B
and V
E
. Replacing R
1
and R
2
with
their Thevenin equivalent, we have:
R
B
= R
1
R
2
=
47 10
3
39 10
3
47 10
3
+ 39 10
3
= 21.3 k
V
BB
=
R
2
R
1
+ R
2
V
CC
= 6.80 V
KVL: V
BB
= R
B
I
B
+ V
BE
+ R
E
I
E
V
BB
V
BE
= [R
B
+ R
E
( + 1)]I
B
I
B
=
6.80 0.7
21.3 10
3
+ 1.5 10
3
201
= 18.9 A
I
C
I
E
= I
B
= 3.78 mA
V
E
= R
E
I
E
= 1, 500 3.78 10
3
= 5.67 V
V
B
= V
E
+ V
BE
= 5.67 + 0.7 = 6.37 V
AC voltages: The circuit is a voltage follower. But, we have to check to see if capacitors
aect the signal. The frequency of the input signal is 5000/(2) = 796 Hz. The impact of
C
1
coupling capacitor is to set a lower cut-o frequency for the amplier.
R
i
R
B
= 21.3 k
2 f
l
=
1
R
i
C
c
f
l
= 75 Hz 796 Hz
Thus: v
B
= v
i
v
B
= V
B
+ v
B
= 6.37 + cos(5000t)
A
v
1 v
E
= v
B
= v
i
v
E
= V
E
+ v
E
= 5.67 + cos(5000t)
Capacitor C
2
and resistor R
L
act as a high-pass lter. They separate the DC voltage. To
consider their impact on the AC signal, note:
2 f
l
=
1
R
L
C
2
f
l
= 6.8 Hz 796 Hz
Thus: v
o
= v
E
= v
B
= v
i
v
o
= 0 + v
o
= cos(5000t)
= 5 k, r
o
= 100 k).
v
i
v
o
47 F
0.33 F
15 V
2 k 39 k
510
6.2 k
510
v
i
v
o
0.33 F
15 V
2 k 39 k
510 6.2 k
v
i
v
o
0.33 F
510 || 510
= 255
15 V
2 k
6.2 k
39 k
DC Response AC signals
For DC signals, capacitors are open circuit and the emitter resistor is only 510 . For AC
signals, capacitors are short circuit and the emitter resistor is 510 510 = 255 .
DC analysis:
R
B
= 6.2 39 = 5.35 k V
BB
=
6.2 k
6.2 k + 39 k
15 = 2.06 V
V
BB
= R
B
I
B
+ V
BE
+ I
E
R
E
= 5.35 10
3
I
C
200
+ 0.7 + 510I
C
I
C
I
E
= 2.53 mA I
B
=
I
C
= 12.6 A
V
CC
= R
C
I
C
+ V
CE
+ R
E
I
E
V
CE
= 15 2.53 10
3
(2, 510) = 8.65 V
So Q point values are: I
C
I
E
= 2.53 mA, I
B
= 12.6 A, and V
CE
= 8.65 V.
AC analysis: This is common emitter amplier with emitter resistance:
A
v

R
C
R
E
=
2, 000
255
= 7.8
R
i
R
B
= 4.8 k
R
o
r
o
_
R
E
r
e
+ 1
_
= 1.1 M
Problems 14 & 15. Find the bias point and AC amplier parameters of these
circuits (Manufacturers spec sheets give: = 200, r
= 5 k, r
o
= 100 k).
Both of these circuits are PNP versions of problem 6. For DC bias we should get the
same value for currents and voltages would be negative: I
C
= I
E
= 4 mA, I
B
= 20 A,
V
CE
= 5 V, and V
BE
= 0.7 V. The amplier parameters are exactly identical to those of
problem 6.
= 5 k, r
o
= 100 k).
v
o
v
i
1k
4 V
5 V
v
o
1k
4 V
5 V
This circuit is also similar to the circuit of problem 6.
Here BJT is biased with two voltage sources (Note that
in problem 6, V
BB
5 V and here V
EE
= 5 and
V
CC
= 9 5 = 4 V. As such, the Q-point parameters
should be the same.
DC Analysis: We short v
i
and,therefore, the BJT base would be grounded:
BE-KVL: 0 = V
BE
+ 10
3
I
E
5 I
C
I
E
= 4.3 mA
I
B
=
I
C
= 20 A
CE-KVL: 4 = V
CE
+ 10
3
I
E
5
V
CE
= 9 10
3
4.3 10
3
= 4.7 V
DC Bias summary: I
E
I
C
= 4 mA, I
B
= 20 A, and V
CE
= 5 V.
AC analysis: The circuit is a common collector amplier. Using the formulas in page 189,
A
v
1
R
i
= r
+ (R
E
r
o
)(1 + ) r
+ r
o
(1 + ) = 20 M
R
o

r
= 25
f
l
=

l
2
=
1
2R
i
C
c
=
1
2 2 10
7
0.47 10
6
= 0.034 Hz
Note that because there are no bias resistors (R
B
), we have used the full formulas for
R
i
and the amplier has a large input resistance.
(Manufacturers spec sheets give K = 0.25 mA/V
2
, V
t
= 1 V, g
m
= 0.25 mA/V,
and r
o
= 100 k).
v
i
v
o
C
c
1k
110k 2k
51k
12 V
v
o
1k
2k
12 V
34.8k
3.8 V
+
DC Bias: Replacing the bias circuit with its Thevenin equivalent, we get:
V
GG
=
51, 000
51, 000 + 110, 000
12 = 3.80 V
R
G
= 51 k 110 k = 34.8 k
Since i
G
= 0,
GS-KVL: 3.8 = 34, 800i
G
+ V
GS
+ 1, 000i
D
= V
GS
+ 1, 000i
D
Assume NMOS is in active state,
i
D
= K(V
GS
V
t
)
2
= 0.25 10
3
(V
GS
1)
2
Substituting for i
D
in GS-KVL, we get:
3.8 = V
GS
+ 0.25(V
GS
1)
2
= 0.25V
2
GS
+ 0.5V
GS
+ 0.25
V
GS
= 2.9 V and V
GS
= 4.9 V
Negative root is unphysical, so V
GS
= 2.9 and i
D
= 0.9 mA. Then,
DS-KVL: 12 = 2, 000i
D
+ V
DS
+ 1, 000i
D
= V
DS
+ 2.7 V
DS
= 9.3 V
As V
DS
= 9.3 > V
GS
V
t
= 2.9 1 = 1.95, our assumption of NMOS in active state is
correct. Therefore, Bias Summary: V
GS
= 2.9 V, V
DS
= 9.3 V, and i
D
= 0.9 mA.
AC Analysis: This is a common source amplier with a source resistor. Using formulas in
page 190:
A
v

g
m
R
D
1 + g
m
R
S
=
0.25 10
3
2 10
3
1 + 0.25 10
3
10
3
=
0.5
1.25
= 0.4
R
i
= R
G
= 34.8 k
R
o
= 1/g
m
r
o
=
1
0.25 10
3
100 10
3
4 k
l
= 2 f
l
=
1
R
i
C
c
2
and V
t
= 3 V, g
m
= 0.2 mA/V,
and r
o
= 100 k).
v
i
v
o
C
c
C
b
1M
1k 1M
1k
20 V
v
o
1k
500k
10 V
1k
20 V
+
DC Bias:
Replacing the bias circuit with its Thevenin equivalent,
we have R
G
= 500 k and V
GG
= 10V:
GS-KVL: 10 = v
GS
+ 10
3
i
D
DS-KVL: 20 = v
DS
+ 10
3
i
D
Assume NMOS in active state: i
D
= K(v
GS
V
t
)
2
and
v
DS
> v
GS
V
t
. Substituting for i
D
in GS-KVL, we get:
GS-KVL: 10 = v
GS
+ 10
3
0.2 10
3
(v
GS
3)
2
10 = v
GS
+ 0.2v
2
GS
1.2v
GS
+ 1.8
v
2
GS
v
GS
41 = 0
v
GS
= 5.92 V and v
GS
= 6.92 V
Negative root is unphysical so v
GS
= 6.92 V.
GS-KVL give i
D
= 3.08 mA. DS-KVL gives v
DS
= 20 6.16 = 13.8 V Since v
DS
= 13.8 >
v
GS
V
t
= 6.92 3 = 3.92 V, our assumption of NMOS in active state is justied. Bias
summary: v
GS
= 6.92 V, v
DS
= 13.8 V, and i
D
= 3.08 mA
AC Analysis: This is a common source amplier with NO source resistor. Using formulas in
page 190:
A
v
g
m
R
D
= 0.2 10
3
10
3
= 0.2
R
i
= R
G
= 500 k
R
o
= r
o
= 100 k
Note: Problems 17 & 18 show some fundamental dierences between FET and BJT ampli-
ers. BJTs have a much larger gain compared to FET (compare g
m
= 20 40 mA/V for a
typical BJT with g
m
= 0.2 05mA/V for an NMOS). Therefore, typically R
D
and R
S
are a
factor of 10 or more larger than typical R
C
and R
E
values.
In addition, BJTs are more linear as i
C
= i
B
and does not vary considerably, while in
a MOSFET, i
D
= (v
GS
V
t
)
2
so FET response is quadratic instead of linear. Because of
the more linear behavior and the higher gain, BJTs are used most often in amplier circuits.
A rst-stage FET source follower is also used to increase the input resistance of the overall
circuit considerably.
2
and V
t
= 4 V, g
m
= 0.2 mA/V,
and r
o
= 100 k).
v
i
v
o
C
c
500k
1.3M
10k
18 V
v
o
10k
18 V
13 V
361k
+
DC Bias:
Replacing the bias circuit with its Thevenin equivalent,
we have R
G
= 360 k and V
GG
= 5V:
GS-KVL: 13 = v
GS
+ 10
4
i
D
DS-KVL: 18 = v
DS
+ 10
4
i
D
Assume NMOS in active state: i
D
= K(v
GS
V
t
)
2
and
v
DS
> v
GS
V
t
. Substituting for i
D
in GS-KVL, we get:
GS-KVL: 5 = v
GS
+ 50 10
3
0.2 10
3
(v
GS
4)
2
5 = v
GS
+ 10v
2
GS
80v
GS
+ 160
10v
2
GS
81v
GS
+ 155 = 0
v
GS
= 3.1 V and v
GS
= 5 V
Since V
GS
= 3.1 < V
t
= 4 V required for NMOS On, this root is unphysical so v
GS
= 5 V.
GS-KVL give i
D
= 0.2 mA. DS-KVL gives v
DS
= 18 10 = 8 V Since v
DS
= 8 > v
GS
V
t
=
54 = 1 V, our assumption of NMOS in active state is justied. Bias summary: v
GS
= 5 V,
v
DS
= 8 V, and i
D
= 0.2 mA
AC Analysis: This is a common drain amplier (or source follower). Using formulas in page
190:
A
v
=
g
m
r
o
R
S
r
o
+ (1 + g
m
r
o
)R
S
=
0.2 10
3
100 10
3
50 10
3
100 10
3
+ (1 + 0.2
3
100 10
3
) 50 10
3
= 0.87
R
i
= R
G
= 360 k
R
o
= 1/g
m
r
o
5 k
Problem 20: Find the bias point and AC amplier parameters of this circuit
= 5 k, r
o
= 100 k).
v
i
v
o
0.47 F
4.7 F
6.2k
Q1
33k
22k
18k
15 V
1k
Q2
2k
500
This is a two-stage amplier. The rst stage (Q1)
is a common emitter amplier and the second
stage (Q2) is an emitter follower. The two stages
are coupled by a coupling capacitor (0.47 F).
DC analysis:
When we replace the coupling capacitors with
open circuits, we see the that bias circuits for
the two transistors are independent of each other.
Each bias circuit can be solved separately.
For Q1, we replace the bias resistors (6.2k and 33k) with their Thevenin equivalent and
proceed with DC analysis:
R
B1
= 6.2 k 33 k = 5.22 k and V
BB1
=
6.2
6.2 + 33
15 = 2.37 V
BE-KVL: V
BB1
= R
B1
I
B1
+ V
BE1
+ 10
3
I
E1
I
B1
=
I
E1
1 +
=
I
E1
201
2.37 0.7 = I
E1
_
5.22 10
3
201
+ 500
_
I
E1
= 3.17 mA I
C1
, I
B1
=
I
C1
= 16 A
CE-KVL: V
CC
= 2 10
3
I
C1
+ V
CE1
+ 500I
E1
V
CE1
= 15 2.5 10
3
3.17 10
3
= 7.1 V
DC Bias summary for Q1: I
E1
I
C1
= 3.17 mA, I
B1
= 16 A, V
CE1
= 7.1 V
Following similar procedure for Q2, we get:
R
B2
= 18 k 22 k = 9.9 k and V
BB2
=
22
18 + 22
15 = 8.25 V
BE-KVL: V
BB2
= R
B2
I
B2
+ V
BE2
+ 10
3
I
E2
I
B2
=
I
E2
1 +
=
I
E2
201
8.25 0.7 = I
E2
_
9.9 10
3
201
+ 10
3
_
I
E2
= 7.2 mA I
C2
, I
B2
=
I
C2
= 36 A
CE-KVL: V
CC
= V
CE2
+ 10
3
I
E2
V
CE2
= 15 10
3
7.2 10
3
= 7.8 V
E2
I
C2
= 7.2 mA, I
B2
= 36 A, V
CE2
= 7.8 V
AC analysis:
We start with the emitter follower circuit (Q2) as the input resistance of this circuit will
appear as the load for the common emitter amplier (Q1). Using the formulas in page 189:
A
v2
1
R
i2
R
B2
= 9.9 k
f
l2
=

l2
2
=
1
2R
B2
C
c2
=
1
2 9.9 10
3
0.47 10
6
= 34 Hz
Since R
i2
= 9.9 k is NOT much larger than the collector resistor of common emitter
amplier (Q1), it will aect the rst circuit. Following discussion in pages 176 and 177, the
eect of this load can be taken into by replacing R
C
in common emitter ampliers formulas
with R
C
= R
C
R
L
= R
C1
R
i2
= 2 k 9.9 k = 1.66 k.
|A
v1
|
R
C
R
E
=
1.66k
500
= 3.3
R
i1
R
B1
= 5.22 k
f
l1
=

l1
2
=
1
2R
B1
C
c1
=
1
2 5.22 10
3
4.7 10
6
= 6.5 Hz
The overall gain of the two-stage amplier is then A
v
= A
v1
A
v2
= 3.3. The input resistance
of the two-stage amplier is the input resistance of the rst-stage (Q1), R
i
= 9.9 k. To
nd the lower cut-o frequency of the two-stage amplier, we note that:
A
v1
(j) =
A
v1
1 j
l1
/
and A
v2
(j) =
A
v2
1 j
l2
/
A
v
(j) = A
v1
(j) A
v2
(j) =
A
v1
A
v2
(1 j
l1
/)(1 j
l2
/)
From above, it is clear that the maximum value of A
v
(j) is A
v1
A
v2
and the cut-o frequency,
l
can be found from |A
v
(j =
l
)| = A
v1
A
v2
/
2 (similar to procedure we used for lters).

For the circuit above, since
l2

l1
the lower cut-o frequency would be very close to
l2
.
So, the lower-cut-o frequency of this amplier is 34 Hz.
= 5 k, r
o
= 100 k).
v
i
v
o
4.7 F
I
B2
I
1
I
C1
6.2k 500
15 V
1k
Q2
Q1
2k 33k
V
B2
This is a two-stage amplier. The rst stage (Q1) is
a common emitter amplier and the second stage (Q2)
is an emitter follower. The circuit is similar to the two-
stage amplier of Problem 20. The only dierence is that
Q2 is directly biased from Q1 and there is no coupling
capacitor between the two stages. This approach has its
own advantages and disadvantages that are discussed at
the end of this problem.
DC analysis:
Since the base current in BJTs are typically much smaller that the collector current, we start
by assuming I
C1
I
B2
. In this case, I
1
= I
C1
+ I
B2
I
C1
I
E1
(the bias current I
B2
has
no eect on bias parameters of Q1). This assumption simplies the analysis considerably
and we will check the validity of this assumption later.
For Q1, we replace the bias resistors (6.2k and 33k) with their Thevenin equivalent and
proceed with DC analysis:
R
B1
= 6.2 k 33 k = 5.22 k and V
BB1
=
6.2
6.2 + 33
15 = 2.37 V
BE-KVL: V
BB1
= R
B1
I
B1
+ V
BE1
+ 10
3
I
E1
I
B1
=
I
E1
1 +
=
I
E1
201
2.37 0.7 = I
E1
_
5.22 10
3
201
+ 500
_
I
E1
= 3.17 mA I
C1
, I
B1
=
I
C1
= 16 A
CE-KVL: V
CC
= 2 10
3
I
C1
+ V
CE1
+ 500I
E1
V
CE1
= 15 2.5 10
3
3.17 10
3
= 7.1 V
E1
I
C1
= 3.17 mA, I
B1
= 16 A, V
CE1
= 7.1 V
To nd the bias point of Q2, we note:
V
B2
= V
CE1
+ 500 I
E1
= 7.1 + 500 3.17 10
3
= 8.68 V
BE-KVL: V
B2
= V
BE2
+ 10
3
I
E2
8.68 0.7 = 10
3
I
E2
I
E2
= 8.0 mA I
C2
, I
B2
=
I
C2
= 40 A
KVL: V
CC
= V
CE2
+ 10
3
I
E2
V
CE2
= 15 10
3
8.0 10
3
= 7.0 V
E2
I
C2
= 8.0 mA, I
B2
= 40 A, V
CE2
= 7.0 V
We now check our assumption of I
C1
I
B2
. We nd I
C1
= 3.17 mA I
B2
= 41 A. So,
our assumption was justied.
It should be noted that this bias arrangement is also stable to variation in transistor . The
bias resistors in the rst stage will ensure that I
C1
( I
E1
) and V
CE1
is stable to variation
of Q1 . Since V
B2
= V
CE1
+ R
E1
I
E1
, V
B2
will also be stable to variation in transistor .
Finally, V
B2
= V
BE2
+ R
E2
I
E2
. Thus, I
C2
( I
E2
) will also be stable (and V
CE2
because of
CE-KVL).
AC analysis:
As in problem 20, we start with the emitter follower circuit (Q2) as the input resistance
of this circuit will appear as the load for the common emitter amplier (Q1). Using the
formulas in page 189 and noting that this amplier does not have bias resistors (R
B1
):
A
v2
1
R
i2
= r
+ (R
E
r
o
)(1 + ) = 5 10
3
+ 201 10
3
= 201 k
Note that because of the absence of the bias resistors, the input resistance of the circuit is
very large, and because of the absence of the coupling capacitors, there is no lower cut-o
frequency for this stage.
Since R
i2
= 201 k is much larger than the collector resistor of common emitter amplier
(Q1), it will NOT aect the rst circuit. The parameters of the rst-stage common emitter
amplier can be found using formulas of page 189.
|A
v1
|
R
C
R
E
=
2, 000
500
= 4
R
i1
R
B1
= 5.22 k
f
l1
=

l1
2
=
1
2R
B1
C
c1
=
1
2 5.22 10
3
4.7 10
6
= 6.5 Hz
v
= A
v1
A
v2
= 4. The input resistance
i
= 9.9 k. The
lower cut-o frequency of the two-stage amplier is 6.5 Hz.
This two-stage amplier has many advantages over that of problem 20. It has three less
elements. Because of the absence of bias resistors, the second-stage does not load the rst
stage and the overall gain is higher. Also because of the absence of a coupling capacitor
between the two-stages, the overall cut-o frequency of the circuit is lower. Some of these
issues can be resolved by design, e.g., use a large capacitor for coupling the two stages, use
a large R
E2
, etc.. The drawback of this circuit is that the bias circuit is more complicated
and harder to design.
= 5 k, r
o
= 100 k).
v
i
v
o
4.7 F
I
B2
I
C1
I
1
V
B2
510 2.7k
3.6k 15k
18 V
510
1.5k
Q1
Q2
We start with replacing 2.7 k and 15 k voltage di-
vider with its Thevenin equivalent (as seen in circuit
below)
R
B
= 2.7 15 = 2.29 k
V
BB
=
2.7 k
2.7 k + 15 k
18 = 2.75 V
Writing a KVL through BE terminals of Q1 and assuming that
Q1 is in the active-linear state (I
C1
I
E1
= I
B1
), we get:
V
BB
= R
B
I
B1
+ V
BE1
+ 510I
E1
= 2.29 10
3
I
C1
100
+ 0.7 + 510I
C1
I
C1
I
E1
= 3.85 mA I
B1
= I
C1
/ = 38.5 A
CE1-KVL: 18 = 3.6 10
3
I
1
+ V
CE1
+ 510I
E1
KCL: I
1
= I
C1
+ I
B2
We assume I
B2
I
C1
. Then, from KCL above, I
1
I
C1
= 3.85 mA. Substituting for I
1
and I
E1
in CE1-KVL, we nd V
CE1
= 2.18 V. Since V
CE1
> V
= 0.7 V, our assumption of

Q1 being in the active-linear state is justied.
To nd the Q-point of Q2, we rst calculate the voltage at the collector of Q1 through a
KVL its CE terminals:
V
C1
= V
B2
= V
CE1
+ 510I
E1
= 2.18 + 1.96 = 4.14 V
We assume that Q2 is in the active-linear state. We can calculate I
C2
I
E2
from a KVL:
V
C1
= V
B2
= V
BE2
+ 510I
E2
4.14 = 0.7 + 510I
E2
I
E2
I
C2
= 6.75 mA I
B2
=
I
C2
= 67.5 A
Since I
B2
= 67.5 A I
C1
= 3.85 mA, our assumption of I
B2
I
C1
is justied. Lastly, we
can nd V
CE2
from a KVL through CE terminals of Q2:
18 = 1.5 10
3
I
C2
+ V
CE2
+ 510I
E2
V
CE2
= 4.43 V
Ans since V
CE2
= 4.43 V > V
= 0.7 V, our assumption of Q2 being in the active-linear

state is justied.
Therefore, the operating points of BJTs are: I
E1
I
C1
= 3.85 mA, I
B1
= 38.5 A, V
CE2
=
2.18 V and I
E2
I
C2
= 6.75 mA, I
B2
= 67.5 A, V
CE2
= 4.43 V
AC analysis:
As in problems 20 & 21, we start with the Q2 circuit as the input resistance of this circuit
will appear as the load for the Q1 circuit. Q2 is congured as a common emitter amplifer
with an emitter resistor. Using the formulas in page 189 and setting R
B1
:
A
v2

R
C
R
E
=
1, 500
510
3
R
i2
= r
+ (R
E
r
o
)(1 + ) = 5 10
3
+ 201 510 = 108 k
Note that because of the absence of the bias resistors, the input resistance of the circuit is
very large, and because of the absence of any coupling capacitors, there is no lower cut-o
frequency for this stage.
Since R
i2
= 108 k is much larger than the collector resistor of common emitter amplier
(Q1), it will NOT aect the rst circuit. The parameters of the rst-stage common emitter
amplier can be found using formulas of page 189.
A
v1

R
C
R
E
=
3, 600
510
= 7.06
R
i1
R
B1
= 2.29 k
f
l1
=

l1
2
=
1
2R
B1
C
c1
=
1
2 2.29 10
3
4.7 10
6
= 14.8 Hz
v
= A
v1
A
v2
= 21. The input resistance
i
= 2.3 k. The
lower cut-o frequency of the two-stage amplier is 14.8 Hz.

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VI.

Transistor ampliers: Biasing and Small Signal Model

the BJT is not in the active-linear state (since I

Substituting the expression for i

ECE65 Lecture Notes (F. Najmabadi), Winter 2006 175

, the expression for R

In most circuits, (1 + )(r

(unless we choose a small value for R

The negative sign in A

phase shift between the input and output signals.

(Controlled source aux. Eq.)

phase shift between input and output

As with the emitter follower circuit, the load can

ECE65 Lecture Notes (F. Najmabadi), Winter 2006 182

(second approximation) leading to

are eectively shorted out of the

. Note that as an FET can be biased with large (M) R

, BJT is indeed in the active state.

in order for the BJT to remain in active state, we nd the amplitude

is reduced by a factor of 6 .e.,

(the case with no

2 (similar to procedure we used for lters).

= 0.7 V, our assumption of

= 0.7 V, our assumption of Q2 being in the active-linear

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