NCTU NCTU NCTU NCTU- -- -EE ICLAB EE ICLAB EE ICLAB EE ICLAB Sept. Sept. Sept. Sept.

t. Sept. 2005 2005 2005 2005

NCTU NCTU NCTU NCTU- -- -EE ICLAB EE ICLAB EE ICLAB EE ICLAB Sept. Sept. Sept. Sept. 2005 2005 2005 2005
Design for Testability Design for Testability Design for Testability Design for Testability Design for Testability Design for Testability Design for Testability Design for Testability
Design for Testability Design for Testability Design for Testability Design for Testability
Chen Chen Chih Chih- -Lung Lung email : email : lung@si2lab.org lung@si2lab.org
pg. 2 (50)
Outline
Introduction to design testability issues
Introduction to scan insertion flow
Introduction to auto test pattern generator (ATPG)
pg. 3 (50)
Introduction to design testability issues
pg. 4 (50)
Testing Methodology
Testing
Ensure the quality and reliability of an IC chip
Test coverage
Quality of a test
Test time
Cost of a test
Keys to testability
Controllability
The ability to control the gates inputs by applying values to the networks
primary inputs
Observability
The ability to observe the gates output by inferring its value from the values
at the networks primary outputs
Fault coverage

number of detected faults

fault_coverage =
total number of faults
pg. 5 (50)
Fault Model
Fault model
Stuck at fault: Net is connected to VDD or GND
Stuck at 0 (SA0)
Signal value is stuck at a fixed logical value 0
Stuck at 1 (SA1)
Signal value is stuck at a fixed logical value 1
pg. 6 (50)
Fault Detection
Detectable fault
Undetectable fault
Will make fault coverage smaller than 1
pg. 7 (50)
Test Sequential Circuit
Sequential circuit
Need a sequence of test patterns to detect a fault
Poor in ATPG (Automatic Test Pattern Generation)
pg. 8 (50)
Scan Methodology
Huffman model
A sequential circuit with memory elements (DFF and latch) is difficult to
control and observe.
The classical Huffman model for representing a sequential design:
Y is difficult to control
E is hard to observe
pg. 9 (50)
Scan Methodology (cont.)
Scan synthesis
Overcome the problem by inserting a scan element
Each memory element can be controlled by a scan-input and observed by a
scan-output during the testing process
Scan synthesized circuit with Huffman model
Y is easily controlled by Sin
E can be observed directly by Sout
pg. 10 (50)
Scan DFF cell
Scan D Flip-Flops
Scan DFFs initialize nodes within the design
(controllability)
Scan DFFs capture results from within the design
(observability)
Replace all flip-flops with their equivalent scan-type flip-flops
Additional inputs: scan shift input (SI) and scan enable (SE)
Cost: larger area and setup time requirement
pg. 11 (50)
Scan chain
Sequential design with scan chain for full scan
pg. 12 (50)
Scan Operation
The scan methodology operates in the following sequence
Normal sequence
Normal system operation
Shift sequence
Shift test patterns into each scan cells from scan input serially with clock
only
At the same time, shift out the captured data to scan outputs and compare
the scan output data
Hold sequence
Feeds patterns to primary inputs and runs in combinational state
Capture sequence
Latches the output data generated from the previous mode to each scan
cell synchronously and compares the scan output
pg. 13 (50)
Scan Operation (cont.)
Shift sequence
Shift in test patterns from SCAN_IN
pg. 14 (50)
Scan Operation (cont.)
Hold sequence
Run test patterns in combinational circuit
Capture sequence
Capture from internal nodes
pg. 15 (50)
Scan Operation (cont.)
Shift sequence
Shift out results to SCAN_OUT
pg. 16 (50)
Design for Testability
Test design rule errors
PI shorted with object output
A primary input port connects to another object output pin
Floating inputs
A primary input port is not connected properly to drive the internal logic
A gate input is not connected to a net
Floating outputs
A primary output port is not connected properly to be driven by the internal
logic
A gate output is not connected to a net
pg. 17 (50)
Design for Testability (cont.)
Test design rule errors (cont.)
Combinational feedback loop
Combinational feedback loop might cause races and hazards during testing
It will lead to unpredictable circuit behavior and invalidate test patterns
Cross couple gate
Cross-coupled objects are the simple form of combinational feedback loops
It can create races or hazards
pg. 18 (50)
Design for Testability (cont.)
Test design rule errors (cont.)
Gated clock circuit
The flip-flop/latch clock signal originating from a primary input port goes
through at least one combinational gate other than a buffer or an inverter
Gated asynchronous set/reset
The set/reset of a flip-flop/latch goes through at least one combinational
gate other than a buffer or an inverter
pg. 19 (50)
Introduction to scan insertion flow
pg. 20 (50)
SynTest tools
SynTest tools for test methodologies
TurboCheck
DFT testability analysis tool (asic123)
It analyzes a gate-level design with or without scan for DFT testability
It calculates the controllability and observability
TurboScan
Scan instance selection tool (scansel)
It selects storage elements as scan cells based on your specifications and clock
information
Scan insertion synthesis tool (scansyn)
It is a test synthesis tool including scan cell replacement, scan switching and
scan debug functions
ATPG and simulation tool (asicgen)
It is a combinational and sequential Automatic Test Pattern Generation (ATPG)
tool
The generated test patterns can be converted into serial or parallel Verilog test
benches
pg. 21 (50)
SynTest Scan Design Flow
pg. 22 (50)
Design Compilation
Compiling Verilog files
vlogin command
vlogin is used to compile Verilog structural netlists to SynTest
database .sdb file
Input files:
primitive.def: mapping the vendor cell library to the SynTest primitives
syntest.def: compiler control file
<library_cell>.v: cell library
<design>.v
Output files:
<library_cell>.sdb
<design>.sdb
pg. 23 (50)
Design Compilation (cont.)
Translate cell library
Options
Example
Note
-define SYNTEST_TS: make sure the
SYNTEST_TS block in cell library being compiled
vlogin [options] <verilog_files>
description arguments
The file lib_file are considered as library files and the generated .sdb files are
redirected to the sub-directory lib/ if lib/ exists
Redirect the output files to the specified path-directory
Without this option, all the contents in the ifdef block will be ignored
[-lib lib_file]
[-opath path]
[-define ifdef_cmd]
vlogin define SYNTEST_TS lib .flibsrcfsti_umc_artisan_18.v
pg. 24 (50)
Design Compilation (cont.)
Translate design netlist
Options
Example
vlogin [options] <verilog_files>
description arguments
Redirect the output files to the specified path-directory [-opath path]
vlogin netsrc/UDCOUNTER_SYN.v opath designs
pg. 25 (50)
Design Compilation (cont.)
Compiler control file syntest.def
It shows how the compiler handle the design names for POWER,
GROUND, NOCONNECTS and HIERARCHICAL DELIMILTER
Parameters
Example
GND
Specify additional signal names for ground
(e.g. ALIAS GND {name1} {name2} ;)
Ground
NC
Specify additional signal names for no-connect
(e.g. NOCONNECTS {name1} {name2} ;)
NOCONNECTS
VCC
Specify additional signal names for power
(e.g. ALIAS VCC {name1} {name2} ;)
Power
Delimit expanded signal names
(e.g. HIER_DOT char;)
description Default value parameter
. HIER_DOT
pg. 26 (50)
Design Compilation (cont.)
Compiler control file primitive.def
It contains alias information for primitive names
Resolve ambiguity when Verilog module names are the same as
SynTest primitives
Primitive characteristics
Example
SynTests reserved name for a primitive type. The class type name is unchangeable Classtype
Define the output port name list. Output port names are assigned the attribute o Outputs
User defined names. Map the cell library primitive names to the SynTest primitives Classname
Define the input port name list. Input port names are assigned the attribute i
Use Field
Inputs
pg. 27 (50)
Design Linking and Expanding
Linking and expanding (flattening) design
expin command
expin links and expands (flattens) the design
The expanded design files provide the source file .x.sdb for the TurboCheck
(testability analysis) and the source file .c.sdb for TurboScan (test synthesis
and test generation) tools
Input files:
<library_cell>.sdb, <design>.sdb
primitive.def
Output files:
<design>.x.sdb: design linked and flattened down to the SynTest primitive level
<design>.c.sdb: design linked and flattened down to the library cell level
<design>.conp: connectivity information linking <design>.c.sdb to <design>.x.sdb
pg. 28 (50)
Design Linking and Expanding (cont.)
Linking and expanding (flattening) design
Options
Example
Note
<design>.x.sdb: for TurboCheck
<design>.c.sdb: for TurboScan
expin [options] <top_design>
description arguments
Prevent expin from creating the design.x.sdb file (when you intend to run TurboScan only)
Keep expin from creating the design.c.sdb file (when you do not plan to run TurboScan)
Redirect the output files to the specified path-directory
[-cellonly]
[-nocell]
[-opath path]
expin UDCOUNTER
pg. 29 (50)
Testability Analysis
Analyzing design testability
asic123 command
Analyzes and reports the controllability and observability for designs, and
assumes non-scan, partial-scan or full-scan is implemented
Use a set of Design-For-Test (DFT) rules to identify and report the
problems which cause low fault coverage
Input files:
<design>.x.sdb: design linked and flattened down to the library cell level
<design>.conp: connectivity information linking <design>.c.sdb to <design>.x.sdb
<design>.dft: control the actions and specify constraints for asic123
Output files:
<design>.clk.rpt: contains a clock information report
<design>.123.rpt: contains process messages and a testability analysis report
pg. 30 (50)
Testability Analysis (cont.)
Analyzing design testability
Options
Example
Note
[-fscan] option will remodel all non-scan DFF/latches as scan DFF/latches
and perform testability analysis
[-psan] option will remodel the non-scan DFF/latches for instances or cell
types which are specified in .psi file as scan DFF/latches, and perform
testability analysis
asic123 <sdb_name> [options]
description arguments
Do testability analysis based on partial-scan assumption (need additional .psi file)
Do testability analysis based on full-scan assumption
Redirect the .123.rpt and .clk.rpt with the prefix <dir/prefix>
[-pscan]
[-fscan]
[-o path]
asic123 UDCOUNTER fscan o 123/UDCOUNTER
pg. 31 (50)
Testability Analysis (cont.)
The input files of asic123 command
<design>.dft
asic123 reads the %TA_CONSTRAINTS field only
%TA_CONSTRAINTS
This field defines testability analysis constraints
%CLOCK specifies nets which behave as clocks
%FORCE force the specified values on the nets
<design>.psi
It is an OPTIONAL file used to control flip-flops for the design requirement
in order to restrict the use of certain FFs
Key parameters
MUST_SCAN: specify the hierarchical instance
names of scan elements treated as scan element
in testability analysis
DONT_SCAN: specify the hierarchical instance
names of scan elements you do not want asic123
treat as scan elements in testability analysis
pg. 32 (50)
Test Synthesis
Scan elements selection
scansel command
scansel is a scan element selector which selects scan elements more
efficiently and lists them
scansel checks the clocks automatically and splits the selected elements
with different clock domains into separated chains
Input files:
<design>.x.sdb: design linked and flattened down to the library cell level
<design>.dft: control the preamble actions and specify different clocks in shift-
sequence
Output files:
<design>.sel<n>.pso: the cell list which should be converted to scan cells or
transparent cells for scan synthesis and test pattern generation
<design>.sel.rpt: contains the scan instance selection information
pg. 33 (50)
Test Synthesis (cont.)
Scan elements selection
Options
Example
Note
For different scan chains, scansel will report the selected instance names in
the numerical files. The clock domain groups detected are shown in
the .pso files for reference
scansel UDCOUNTER fscan scan_chain 1 o sel/UDCOUNTER
scansel <sdb_name> [options]
Specify the scan chain number. scansel splits the selected instance names to <n>.pso file [-scan_chain <n>]
description arguments
Do not select latches as scan elements
Select all memory elements as scan elements, except the DONT_SCAN specified in .psi
Redirect the report file as <dir/prefix.sel.rpt>
[-no_latch]
[-fscan]
[-o dir/prefix]
pg. 34 (50)
Test Synthesis (cont.)
The input files of scansel command
<design>.dft
scansel reads the %SEQUENCE, %INSTRUCTION, and
%CONNECT_SCAN fields
%SEQUENCE
Some proper force-values should be set in %SEQUENCE to get a correct scan
synthesized netlist
%INSTRUCTION
This field defines the scan instruction and sequence names
%CONNECT_SCAN
All the scan chain information is defined in %CONNECT_SCAN field
Different chains have to be defined separately
%SCAN_CLOCK_<n>: defines the scan clock
%SCAN_INSTANCES_FILE: the scan list of the instance name of memory elements
%SCAN_PORT: the scan input and scan output port names list
%SCAN_INSTRUCTION: the scan synthesis instruction
pg. 35 (50)
Test Synthesis (cont.)
The input files of scansel command (cont.)
Example of <design>.dft
pg. 36 (50)
Test Synthesis (cont.)
Scan synthesis
scansyn command
scansel replaces scan cells and stitches them to scan chains
The new database is saved in the extension _s0
Input files:
<design>.x.sdb, <design>.c.sdb: expanded design
<design>.dft: control file
<design>.sel<n>.pso: list all the scanned memory element instances
<library>.map: scan and logic cells list
pg. 37 (50)
Test Synthesis (cont.)
Scan synthesis (cont.)
scansyn command (cont.)
Output files:
<design>_s0.sdb, <design>_s0.x.sdb, <design>_s0.conp: the modified design
scan_decoder.v: the scan decoder in Verilog format used to fix the netlist
SCAN_DECODER_CLASS.sdb: the scan decoder in SynTest format
<design>_s0.dft: the modified control file
<design>.syn.log: the process messages of related programs such as vlogin and
expin needed during netlist modification
<design>.syn.rpt: the scansyn process messages
<design>_s0.syn.rpt: the scan chain extraction message
<design>_s0.syn.pso: list DONT_MODIFY, DONT_SCAN, and
MUST_BE_TRANSPARENT scan instances
<design>_s0.ext<n>.pso: list all the scan instances which are extracted by
scansyn successfully
<design>_s0.ext<n>.clk: includes clock information of all scan chains and
transparent cells in each scan chain
pg. 38 (50)
Test Synthesis (cont.)
Scan synthesis
Options
Example
Note
scansyn reads %CONNECT_SCAN, %SCAN_INSTRUCTION, and
%READ_MAP fields in <design>.dft
scansyn UDCOUNTER fscan
scansyn <sdb_name> [options]
Run full scan synthesis [-fscan]
Direct the output file to specified directory or files [-o dir/prefix]
description arguments
Display the options list [-help]
pg. 39 (50)
Test Synthesis (cont.)
The input files of scansyn command
<library>.map
The .map is divided to two parts: %MAP_SCAN and %REPAIR_CELL
%MAP_SCAN: for scan cell replacement
defines the mapping of scan cell types and relevant pin names
%MAP_CELL: how to map one generic memory cell into scannable counterpart
%SCAN_PORT %SYSTEM_IN: normal data input pin
%SCAN_PORT %SCAN_IN: scan data input pin
%SCAN_PORT %SCAN_OUT: scan data output pin
%SCAN_PORT %SCAN_OUT_INV: inverse scan data output pin
%SCAN_SELECT_1 %SELECT: scan select pin
%SCAN_CLOCK_1 %CLOCK: scan clock pin
%REPAIR_CELL: list of available logic cells
The listed logic cells are used to fix the netlist by scansyn
scansyn will insert some combinational logic cells to fix some testability errors
such as the asynchronous set/reset, the gated clock and the bus contention
during the test mode
pg. 40 (50)
Test Synthesis (cont.)
The input files of scansyn command (cont.)
Example of <library>.map
pg. 41 (50)
Test Synthesis (cont.)
Scan debugging
scandbg command
Scandbg checks if the scan chains have been stitched completely and run
correctly
Most the case it does not need to use because the scansyn has done most
fixes already
Options
Example
scandbg <sdb_name> [options]
Direct the output file to specified directory or files [-o dir/prefix]
description arguments
scandbg UDCOUNTER_s0 o scandbg/UDCOUNTER_s0
pg. 42 (50)
Automatic Test Pattern Generation
ATPG
asicgen command
asicgen generate test patterns with both combinational-ATPG and
sequential-ATPG algorithms to improve fault coverage
It will report fault coverage and hard-detected/redundant/untestable fault list
Input files:
<design>[ _s0].x.sdb, <design>[ _s0].dft, <design>[ _s0].ext<n>.pso
Output files
<design>[ _s0].tp: the generated test vectors in SynTest pattern format
<design>[ _s0].pso: list all the scan instances checked out by asicgen
<design>[ _s0].rpt: fault coverage report and the asicgen processing messages
<design>[ _s0].int: the netlist interface information extracted by asicgen
<design>[ _s0].hdt, <design>[ _s0].udt, <design>[ _s0].red: the lists of hard-
detected, un-detected, and redundant faults
<design>[ _s0].rst: record all option restart information. Valid when post_fscan
pg. 43 (50)
Automatic Test Pattern Generation (cont.)
ATPG
Options
Example
asicgen UDCOUNTER_s0 atpg post_fscan compact 10 no_z
asicgen <design_name> [options]
Specify the number <num> of weighted random patterns [-weighted <num>]
Specify the effort for generate shorter test patterns using varied compaction algorithms
<num>: 1 to10; 1:less effort, larger # of patterns; 10:higher effort, smaller # of patterns
[-compact <num>]
Assume all memory elements are scannable [-fscan]
It calculates the exact fault coverage after scan chain insertion, which is used to get the
accurate fault coverage and generate the test vectors
[-post_fscan]
Generate test vectors and report the fault coverage (default option) [-atpg]
Direct the output files to the specified <dir/prefix> [-o dir/prefix]
description arguments
Do not allow floating primary outputs [-no_z]
pg. 44 (50)
Automatic Test Pattern Generation (cont.)
The input files of asicgen command
<design>[_s0].def
asicgen reads %ATPG_CONSTRAINTS, %SEQUENCE, and
%SCAN_INSTANCE_FILE fields in <design>[ _s0].def file
%ATPG_CONSTRAINTS
Sets the force values for ATPG which should be identical to the settings in the
hold sequence
The hold sequence defines the stable state when asicgen performs ATPG
function
pg. 45 (50)
Test Pattern Translation
Translating test patterns
tpout command
It is test patterns translator which translate test patterns from the SynTest
format to the different formats such as Verilog
tpout provides the broad-side loading approach to reduce simulation time
Broad-side loading: put scan patterns on the scan instances directly instead of
going through scan chains. It can save a lot of shifting pattern time
Input files
<design>[ _s0].tp, <design>[ _s0].int, <design>[ _s0].dft,
<design>[ _so].ext<n>.pso
Output files
<design>[ _s0].drv.v: driver file
<design>[ _s0].vector: vector file
<design>[ _s0].tpout.rpt: test pattern translation summary
pg. 46 (50)
Test Pattern Translation (cont.)
Translating test patterns
Options
Example
tpout vlog fscan sdf UDCOUNTER_SYN.sdf UDCOUNTER_s0
tpout <pattern_format> [options]
Read <num> pattern(s) from .tp file [-tp_limit <num>]
Generate broadside-load Verilog driver file. (Used in vlog fscan only) [-bl]
Use <filename> as interface (.int) file [-int_file <filename>]
Add $sdf_annotate(<sdf_name>,) in Verilog testbench. (Used in vlog fscan only) [-sdf <sdf_name>]
Use <filename> as pattern (.tp) file [-tp_file <filename>]
Translate the patterns for full-scan design [-fscan]
Verilog format (default) [-vlog]
description arguments
Redirect the output files to the specified <dir/filename> [-o dir/filename]
pg. 47 (50)
Writing Design back to Netlist
Writing SynTest database back to netlist
lsdb command
After the test-synthesis is completed, use lsdb to write out the new netlist in
Verilog format
Input files
<design>[ _s0].sdb
<library_cell>.sdb
primitive.def
Output files
<design_filename>.v
pg. 48 (50)
Writing Design back to Netlist (cont.)
Writing SynTest database back to netlist
Options
Example
lsdb UDCOUNTER_s0 verilog hierarchy o UDCOUNTER_scan.v
lsdb <sdb_name> [options]
Write the netlist to standard output in hierarchical format [-hierarchy]
Write the netlist to standard output in Verilog format [-verilog]
Output the generated netlist in the specified file [-o filename]
description arguments
Specify time unit time_scale 1ns/10ps in the Verilog netlist [-timescale]
pg. 49 (50)
Fault Simulation
Running fault simulation
Apply fault simulation using generated files <design_scan>.v,
<design>[ _s0].vector, and <design>[ _s0].drv.v
Example
set_dont_use during netlist synthesis
Scan-type DFF should not be used during synthesis. Use set_dont_use
command during netlist synthesis to avoid utilizing them
In synthesis script, remember to include
dont_use.tcl file
verilog UDCOUNTER_scan.v UDCOUNTER_s0.drv.v v /RAID/Manager/lib.18/Verilog/umc18.v
source dont_use.tcl
pg. 50 (50)
Relative File Preparation
For netlist synthesis
<design>.v: RTL design
<syn>.tcl: synthesis script
dont_use.tcl: set_dont_use on specified cells
For scan synthesis
<design>_SYN.v: design netlist
<design>.dft: the control file
<library>.map: scan cells and logic cells list
<design>.psi (OPTIONAL): the control file for partial scan
<library_cell>.v: cell library for translating to SynTest database
For fault simulation
<design>_SYN.sdf: delay information of design netlist