CS222: (a)ActivationRecordofMergeSort (a) Activation Record of Merge Sort (b)ArchitectureSpaceRISC/CISC

Dr.A.Sahu DeptofComp.Sc.&Engg. Dept of Comp. Sc. & Engg. IndianInstituteofTechnologyGuwahati

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Outline
ActivationRecordinRecursion:
MergeSortActivationRecord

FeaturesofMIPSISA Otherarchitecturalvariations RISCandCISC RISC and CISC Examples

Activationrecord/frame Activation record / frame

$sp
localdata saved sregisters s registers
(ifany)

returnaddr

$fp

arguments

Sortingexample Sorting example Main

constm=20; voidmain(void){ void main(void) { int N,i;int X[m],Y[m]; cout <<"enterthecountofintegers\n";cin >>N; t " t th t fi t \ " i N cout <<"entertheintegers\n"; for(i f ( =0;i <N;i++)cin >>X[i]; ) [] sort(X,Y,N); cout <<"sortedvalues:\n"; for(i =0;i <N;i++)cout <<Y[i]<<"";cout <<endl; }

Recursivemergesortprocedure
voidsort(int A[],int B[],int n){ int A1[m], A2[m]; int n1, n2; A1[m],A2[m];int n1,n2; if(n==1)B[0]=A[0]; else{ l { n1=n/2;n2=n n1; sort(A,A1,n1); sort(A+n1,A2,n2); sort (A+n1, A2, n2); merge(A1,A2,B,n1,n2); } }

Mergeprocedure Merge procedure

voidmerge(int P[],int Q[],int R[],int p,int q){ int i,j,k; k i =j=k=0; while(i <p&&j<q) if(P[i]<Q[j])R[k++]=P[i++]; if (P[i] < Q[ j]) R[k++] = P[i++]; elseR[k++]=Q[j++]; while(i <p)R[k++]=P[i++]; hil (i ) [k ] [i ] while(j<q)R[k++]=Q[j++]; }

Activationrecordformerge Activation record for merge

voidmerge(int P[], d ( [] int Q[],int R[], int i t ) i t p,int q) { int i,j,k; k .. } locals para ameters $sp
i j k returnaddr P Q R p q

Simplifyingactivationrecord Simplifying activation record

$sp $sp
i j k returnaddr P Q R p q returnaddr dd p q a0 a1 1 a2 t0 t1 t2 P Q R i j k

Activationrecordforsort Activation record for sort

voidsort(intA[], intB[],intn) { intA1[m],A2[m]; intn1,n2; }

$sp
A1 A2 n1 n2 returnaddr A B n

pa aramet ters

locals s

Partofmergeprocedure Part of merge procedure

.. while(i<p) R[k++]=P[i++]; R[k++] = P[i++]; returnaddr dd p q a0 a1 1 a2 t0 t1 t2 P Q R i j k
lw$t3,4($sp) l $t3 4($ ) L:bge$t0,$t3,X muli$t4,$t0,4 add$t4,$t4,$a0 lw$t6,0($t4) addi$t0,$t0,1 addi $t0, $t0, 1 muli$t5,$t2,4 add$t5,$t5,$a2 sw$t6,0($t5) $t6 0($t5) addi$t2,$t2,1 jL X:

Callingmerge
merge(A1,A2,B,n1,n2); returnaddr p q A1 A2 n1 n2 returnaddr A B n a0 a1 1 a2 t0 t1 t2 P Q R i j k

addi $a0,$sp,0 addi $ 1 $ 80 ddi $a1,$sp,80 lw $a2,176($sp) lw $t8,160($sp) l $t8 160($ ) sw $t8,8($sp) lw $t8,164($sp) l $t8 164($ ) sw $t8,4($sp) addi $ $ ddi $sp,$sp,12 12 jal merge . merge:sw $ra,0($sp)

Returnfrommerge Return from merge

returnaddr p q A1 A2 n1 n2 returnaddr A B n a0 a1 1 a2 t0 t1 t2 P Q R i j k

lw $ra,0($sp) l $ ($ ) addi $sp,$sp,12 jr $ra

Callingsort Calling sort

A B n A1 A2 n1 n2 returnaddr A B n sort(A,A1,n1); sort:sw $ra,168($sp) . lw $t8,172($sp) l $t8 172($ ) sw $t8,12($sp) addi $t8 $sp 0 $t8,$sp,0 sw $t8,8($sp) lw $t8,160($sp) $ , ($ p) sw $t8,4($sp) addi $sp,$sp,184 jal sort

Returnfromsort Return from sort

A B n A1 A2 n1 n2 returnaddr A B n

lw$ra,168($sp) l $ ($ ) addi$sp,$sp,184 jr$ra

Furtherwork(labexercise) Further work (lab exercise)

Complete the assembly program for recursive merge Completetheassemblyprogramforrecursivemerge sort Writeapointerversion(Candassembly) p ( y) Includecodetotrackthemaxstacksize Reducelocalarraysizetonandfindimprovement Reduce local array size to n and find improvement Writemorespaceefficientprogram(Cand assembly),stillrecursive y),

ArchitectureSpace Architecture Space

Features of MIPS ISA FeaturesofMIPSISA Other architectural variations Otherarchitecturalvariations RISCandCISC Examples

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WhatconstitutesISA? What constitutes ISA?

Mainfeatures: Main features: Setofbasic/primitiveoperations Storagestructure registers/memory How addresses are specified Howaddressesarespecified Howinstructionsareencoded

MIPSISAfeatures MIPS ISA features operations

Arithmetic Logical Relational l i l Branch/jump Datamovement Procedurelinkage Procedure linkage

MIPSISAfeatures MIPS ISA features storage

Memory Registers 0 1 0 4

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2304

MIPSISAfeatures MIPS ISA features addressing

Addressingmodes Addressing modes Immediate Register Base/index PCrelative (pseudo)Direct R i t i di t Registerindirect

Purpose Purpose Operandsources ResultDestinations Jumptargets Jump targets

MIPSaddressingmodes MIPS addressing modes 1

Immediateaddressing
op rs rt constant

Registeraddressing
op rs rt rd func Registers 0 1

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MIPSaddressingmodes MIPS addressing modes 2

Baseaddressing Base addressing
op rs rt register constant Memory 0 4

data

PCrelativeaddressing
op rs rt PC constant

instruction

MIPSaddressingmodes MIPS addressing modes 3

(pseudo)Directaddressing (pseudo) Direct addressing
op constant PC Memory 0 4

instruction

Registerindirectaddressing
op rs rt rd func instruction Register

MIPSISAfeatures MIPS ISA features encoding

addi,lui,beq,bne,lw,sw I format op rs rt 16bitnumber 16 bit number j,jal J format op26bitnumber add,jr R format oprs rt rdshamt funct

MIPSISAfeatures MIPS ISA features summary

Allinstructionsofsamesize All instructions of same size Only3formats FairnumberofGPregisters Simpleoperations eitherarith/logic Simple operations either arith/logic ormemoryaccessorcontroltransfer Limitedaddressingmodes Separate fields for src1 src2 and dest Separatefieldsforsrc1,src2anddest

AlternativeArchitectures Alternative Architectures

Providemorepowerfuloperations
e.g.J++andbranchtoLifJ>N,whereJisin memory or copyablockofdatainmemory memoryorcopy a block of data in memory

Goalistoreducenumberofinstructions executed Dangerisaslowercycletimeand/ora / higherCPI higher CPI

Locationofoperands Location of operands R/M

RR RM MM MM R+M Bothoperandsinregisters Both operands in registers oneoperandinregisterandone inmemory Bothoperandsinmemory Both operands in memory CombinesRR,RMandMM

Howmanyoperandfields? How many operand fields?

3 address machine 3addressmachine 2addressmachine 1addressmachine 0addressmachine r1=r2+r3 r1 = r2 + r3 r1=r1+r2 Acc=Acc+x Accisimplicit Acc is implicit addvalueson topofstack

Registerorganizations Register organizations

Registerlessmachine Register less machine Accumulatorbasedmachine Afewspecialpurposeregisters Severalgeneralpurposeregisters Largenumberofregisters/register Large number of registers / register windows

Additionaladdressingmodes Additional addressing modes

Direct Indirect Basevs.Index Autoincrementandautodecrement Auto increment and auto decrement Pre(post)increment/decrement Stack

RISCvs.CISC RISC vs. CISC

Reduced(vs.Complex)InstructionSet ( p ) Computer Uniformityofinstructions Simple set of operations and addressing Simplesetofoperationsandaddressing modes Registerbasedarchitecturewith3address instructions

RISCPhilosophy RISC Philosophy

1970sJohnCocke atIBM Majorityofcombinationsoforthogonal addressingmodesandinstructionswere addressing modes and instructions were notused
B Bymostprogramsgeneratedbycompilers t t db il

Difficultinmanycasestowritea compiler
To take advantage of the features provided Totakeadvantageofthefeaturesprovided byconventionalCPUs.
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RISCexamples RISC examples

Virtuallyallnewinstructionsetssince1982have beenRISC
SUNsSPARC(Scalable Processor ARChitecture) HPsPARISC ARM(AdvanceRISCMachine) MotorolasPowerPC(Performance Optimization With Enhanced RISCPerformanceComputing,) DECsAlpha MIPS CDC6600(1960s)