SIMPLE MICROPROCESSOR IMPLEMENTATION O F NEW REGULAR-SAMPLED HARMONIC ELIMINATION PWM TECHNIOUES

Sidney R Bowes and Paul R Clark Department of Electrical and Electronic Engineering University of Bristol Bristol England, U K

Abstract New Harmonic Elimination PWM strategies for Drives and Static Power Converters have recently been developed using modified Regular-Sampling techniques. These new PWM strategies can be generated on-line in real-time using a simple microprocessor software algorithm, without resorting to the usual off-line mainframe computer Harmonic Elimination numerical techniques. The implementation and generation of these new PWM techniques is presented using the new INMOS Transputer, although the same techniques can be performed on any standard 8 or 16 bit microprocessor. Results from an experimental Transputer controlled PWM inverter drive are presented to demonstrate and confirm the operation of the new Regular - Sampled Harmonic Elimination PWM control strategies. Introduction It has recently been shown [1,2] how the Selected Harmonic Elimination [3,4] and Optimised [5] PWM techniques can be closely reproduced using a modified version of the simpler Regular-Sampled PWM techniques [6,7]. Using this modified Regular-Sampling technique it is possible to produce a simple algebraic equation to define the Harmonic-Elimination switching angles [I]. Based on this simple algebraic equation an efficient microprocessor-based software algorithm can be developed and used to calculate the Harmonic-Elimination switching angles "online" and in "real-time". This Regular-Sampling approach thus eliminates all of the difficulties and problems referred to previously [3-5, 8-10]. For example, in the past it has been necessary to employ significant off-line computing techniques and computing time to determine the relationships between the PWM switching angles and fundamental voltage [3- IO]. Also these switching angle to voltage characteristics were transcendental and therefore could not be solved on-line using a microprocessor-based PWM controller. Thus extensive Look-Up Tables (LUT's) were necessary to implement these PWM s t r a t e g i e s w d some form of interpolation between LUT's to provide voltage control with all the associated complexity. This ComPIexitY has in the past prevented many Drive and Static Power Converter Industries from adopting these Harmonic Minimisation PWM techniques, although it has been recognised for Some time that these techniques can significantly reduce harmonic losses, RFI, torque pulsations, speed ripple etc. This paper presents the development of a number of alternative microprocessor implementations for the new Regular-Sampled Harmonic Elimination PWM technique. It will be shown initially how the well-established RegularSampled PWM microprocessor implementation can be easily modified to include the new Harmonic Elimination PWM strategy. This microprocessor implementation will take advantage of the special Regular-Sampled characteristics of the new Harmonic Elimination Strategy to provide a simple four-timer implementation. This approach will subsequently be contrasted with the alternative single-timer approach used in the past [8-IO], but with the simpler Regular Sampled modifications. Finally, new two-timer and single-timer microprocessor implementations will be presented using the special characteristics and features of the Harmonic Elimination technique and based o n what will be referred to as the "Sextant Method". The microprocessor implementations considered can therefore be summarised as follows:
(1)

Four-timer implementation based on the per phase Regular-Sampling characteristics Single-timer implementation based on the three-phase vector characteristics Two-timer implementation based on the Sextant Method. Single-timer implementation based on the Sextant Method.

(2) (3)

(4)

Before proceeding to the development of the new microprocessor techniques, it is heIpful to briefly review the salient features of Regular-Sampling techniques as a basis for the development to follow. Regular-SamDled Harmonic Elimination PWM The development of the Harmonic Elimination technique using Regular-Sampling has been presented in an earlier paper [I]. The general features of the Regular-Sampling modulation process is illustrated in Figure I , using N=3 (number of switches per quarter cycle) as a simple illustrative example. Figure 1 shows the switching angles in the first quarter-cycle of the PWM waveform, with the centre of a pulse (corresponding to the sampling instant) coincident with the angular separation, given by tk = kT, at zero voltage. Which for N = 3, from equation (3), gives T = 30 degrees.

I t is therefore hoped that the Regular-Sampling microprocessor techniques outlined in this paper will encourage wider industrial application Of these Harmonic Elimination techniques.

90/CH 2935-5/90/~341$01.00@1990 IEEE

Fig.1

Regular-Sampled Harmonic Elimination PWM

Fig.2

Harmonics.

The degree of modulation Aa, has been shown [2] to be very closely sinusoidal for both odd and even k, and all odd N>3. Thus, two sinewaves suitably phase displaced can be Regularly Sampled, as shown in Figure I , to produce the degree of sinusoidal modulation required Aa,. The modulation Aa, (when suitably scaled) is subsequently used to asymmetrically modulate each edge of the pulse to produce the quarter- wave symmetric The results of this PWM waveform shown in Figure 1. modulation process have been analytically described previously [ I ] and can be expressed in the switching angle equations ( I ) and (2). For the leading-switching edge with k odd:
(Yk

Microprocessor-Based PWM Generation The implementation and generation of optimised 3-phase PWM Strategies, using the new INMOS T414,32bit, Transputer, has been presented earlier [2]. The previous paper [2] also highlighted the special features of the Transputer [ I l l and the programming language OCCAM [12] specifically for PWM generation. Four Timer ImDlementation The details of the PWM generation process using a four-timer implementation [13,14] is illustrated in Figure 3. As shown in Figure 3, at the start of each carrier cycle three timers, corresponding to phases A, B and C, begin timing out the prepulse times la,, tb,, tcl. for the 3-phases, whilst the fourth timer timesout the half sample period, T/2. On completion of each prepulse period, the corresponding phase outputs go high changing the PWM switching pattern. Subsequently, when the fourth timer finishes timing out T/2, the 3-phase timers commence timing out ta,, tb,, tcZ, corresponding to the remaining pulse-width times, and the fourth timer again times out T/2. On completion of each pulse period, the appropriate phase outputs are reset to change the PWM switching pattern. This process is repeated for the next and subsequent carrier cycles to generate the complete PWM waveform. The various pulse-width times are calculated from the switching angle equations [ I ] and [2]. It is possible to use a three-timer implementation [15], however, it has been shown previously [13,14] that it is less accurate and inefficient compared to the four-timer implementation. The timers can be implemented in software in the Transputer [2] or using external hardware when conventional microprocessors are used [ 13- 151.

= (k

1) T / 2 - M T/2 sin [(k

I ) T/2

+ $11

(1)

For the trailing-switching edge with k even:

ak = k T/2

+M

T / 2 sin [kT/2 +

$21

Where the sample period T is defined as:

= a 3(N t 1)

(3)

It has been shown [2] that the modulation index, M , is equal, in per unit (pu) terms, to the fundamental of the PWM voltage, thus providing a simple direct means of voltage control, In addition, it was also possible to derive generalised approximate relationships for the sinusoidal modulating wave phase- angles and 0, of equations (1) and (2), respectively in the form:
$1 =

N T/2

$2

= T/4

(4)

Using these equations analytically defines the Regular-Sampled Harmonic Elimination PWM process for all odd N>3. Using these switching angle equations the errors between the exact harmonic switching angles, and those produced from the RegularSampling process are extremely small, less than 0.25 degrees over the complete voltage range, and decrease as N increases. The effects of these small switching angle errors on the "Eliminated" harmonics is to reintroduce a small amplitude harmonic at the harmonic frequency corresponding to the eliminated harmonic when the exact switching angles are used. All of these harmonics are less than 2% and decrease with increasing N as the Regular Sampling process more accurately reproduces the Harmonic Elimination process [I], as shown in figure 2. Fig.3 Four-Timer Implementation.

342

Sinale Timer Three-phase Vector ImDlementation

As an alternative to the four-timer configuration it is possible to

Two-Timer Sextant Imolementation Typical 3-phase Harmonic Elimination PWM waveforms are shown in Figure 5, using N=3 as a simple illustrative example. All illustrated in Figure 5, the complete PWM cycle (Phase A) can be subdivided into six 0-60" periods (sextants), with PWM switching in the 0-60", 120-180" periods and no switching in the 60-120" period. Due to the half-wave symmetry this switching sequence is repeated in the second half cycle of the PWM waveform. Closer inspection of Figure 5 shows that within the first sextant Phase A is switching the 0-60" switching pattern, Phase B the 120-180" switching pattern and Phase C the 60-120" switching pattern. These switching patterns are rotated between each of the phases in subsequent sextants, as indicated by the "Phases Switching" sequence shown in Figure 5.
Sextant
0
@

use a single-timer configuration to generate the PWM switching pattern for all three phases. The main advantage of this method is the reduction of the number of devices and therefore the cost of the PWM waveform generator, however, additional on-line computation is required. The method consists of considering the three phases simultaneously rather than individually, as illustrated in Figure 4. Using the three-phase voltages shown in Figure 4a, an arbitrary timing diagram can be derived, as shown in Figure 4b, which has a number of intervals equal to the sum of the number of switching instants of all three phases. Within each interval, a switching pattern (vector) is defined which describes the state of all three phases. For example, if a, b and c correspond to a PWM waveform level in phases A , B , and C, respectively in a given interval, then Figure 4c describes the switching pattern in each interval of Figure 4b of the PWM waveform shown in Figure 4a. The generation of PWM waveforms using this method consists of determining the time interval A'k from the different pulse widths A'k in each phase voltage and constructing a switching vector to determine which device should be switched ON (OFF) at that instant. At each interrupt signal, the microprocessor outputs the duration A'k to the single-timer, and the corresponding switching pattern (a, b and c) to the inverter gating circuits. After completion of the time interval A'k the timer generates an interrupt signal signal to the microprocessor, which responds by loading the timer with a new value A'k+l and changes the output switching pattern accordingly. The additional on-line computation needed to calculate the time interval A'k and switching pattern vector LUTs reduces the response speed of the single-timer PWM controller, compared with the four-timer arrangement.

60

120

180 @

2dO

300

360'

I
I

phase B

-- - r
.
I I

A-B

B-C

C-A

A-B

B-C

C-A

Phase

Phases smtchmg

Fig.5
phaseC

Three-phase PWM Waveforms, N=3.

The two-timer and single-timer approach requires the threephases to be considered simultaneously rather than individually. Using the switching angle equations (1) and (2), the N switches per quarter cycle can be calculated in the 0-60" range and, because of the quarter-wave symmetry, used to generate the complete 3-phase PWM waveforms. However, because the N switchings only take place in the 0-60" range and the complete PWM waveform is symmetrical, it is only necessary to consider the first 1/6th of a cycle of the 3-phase PWM waveform, shown in Figure 6. As shown i n Figure 6 in the 3-phase system there exists three distinct switching patterns which repeat in each 1/6th cycle throughout the complete PWM cycle. For example, in the first 1/6th of a cycle: Phase A has a 0-60" switching pattern. Phase B has a 120-180" switching pattern Phase C has a 60-120" degree switching pattern and these switching patterns are alternated between the 3-phases in each subsequent 1/6th of a cycle over the complete PWM cycle. The 0-60" switching pattern is calculated from equations (1) and (2), the 60-120" switching pattern is simply a "full-on'' (or off) blanking period (no switching) and the 120-180" switching pattern, is the angular complement of the 0-60" pattern, thus: = ) 0 ~ ~ ~ ( 1 2 0 - 1 8 060 - ( ~ ~ ( 0 - 6 as) shown in Figure 7.

343

Phase Switching Sextant 1 2 3 0-60" Phase

A

60-120" Phase

C
A

120-180" Phase B

I I

I
I

I
I

Phase B 120'- 180'Swifchmg paltern

B C

C
A

0
At'

At1

' I
I

'

.
At2

j
,

1
~

1
60'

Moreover, since the 60- 120" switching pattern is only "blanking" (on or off) the phase switching sequence can be reduced to:
Phase :1 60'-120'No swjtchmg

Phase Switching Sextant

1

bt3
~

I
,All

0 - 60. At
Timing vecfor 120 -18O'At ABC Switching vector

0-60"
A

A(3

At2

2 3

120-180" B C
A

010

000 100

110

010 000

100

This phase switching sequence is stored as a look-up table (LUT) and only the two-phase PWM switching pattern for a 1/6th cycle period needs to be calculated, not the 3-phase switching pattern. When the timer has timed-out a time interval Atk, the state of the PWM output in one phase change, either from 0 to 1 or 1 to 0. The simplest method for implementing this change of state uses an Exclusive-Or (Ex-OR) function to Ex-OR a logic 1 with the previous state, thus changing 1 to 0 or 0 to 1 as required. The complete two-timer L U T implementation for the 3-phase system, incorporating the Ex-OR data for the 3-phases, is shown in Figure 8.

j
0-60.Ar,,

LUT
At;

120

18O"Atk LUT

SEXTANT EX-OR DATA PHASE I C B A ) !SWITCHING

~

'

z u'j

= 60

u3

;""ii
0-60' dlk

0 1 0

00 1

Timer 11

(timeout)

i7i
100

where uk

k ?2

M v2 sin I k & 2 '

I
Sextanf No

Only N + I tmrng mtervals A r k

need l o be calculated for 3-phase syslem

i
PRESENT INVERTER OUTPUT

Fig.7

Two-Timer Look-Up Tables.

It is therefore only necessary to generate the initial 0-60 degree switching pattern to reproduce the switching pattern for the complete 3-phase PWM waveform. For the 3-phase system with N switches per quarter cycle (per phase), there will be a total of 2N+1 switches in any 1/6th cycle. These 2 N t 1 switching angles will generate switching on only two phases with the third phase switched "on" (or off) for a 1/6th cycle. This switching pattern is repeated for the complete PWM cycle, with each phase switching alternately from one switching pattern to each of the other two switching patterns in each consecutive 1/6th cycle period. Thus, to implement this PWM strategy, using a two-timer implementation, requires only 2 N t 1 timing intervals, Atk (timing vector) as shown in Figure 7 and the associated order of the phase changes. Noting that the 2N+1 timing intervals, Atk calculated in the first 1/6th cycle period are the same in each consecutive 1/6th cycle period and therefore are only calculated once, and used over the complete PWM cycle. Moreover, because of the half-wave symmetry of the PWM waveform, it is necessary only to know the order of the phase changes in the first half cycle, as shown in Figure 5. The difference angles, corresponding to the timer intervals Atk calculated from equation ( I ) and (2), can be simply stored in two look-up tables (LUTs), thereby preserving the phase relationship and the sequence of the phase switching for each 1/6th cycle tabulated as: 344

Fig.8

Details of Two-Timer Implementation.

Sinale-Timer Sextant Imolementation In the case of the single-timer implementation the 0-60" and 120180" switching patterns are combined into one L U T using the timing vector shown in Figure 9. The difference angles, corresponding to the timer intervals Atk (timing vector Figure 9) are calculated from equations (1) and (2). and sorted into ascending order to preserve the phase relationship. To identify each switching pattern a "Pattern Identification Bit (PIB) is used in the L U T , as illustrated in Figure IO.
"

A L U T can be generated which combines the phase-switching sequence, PIB and Ex-OR data for a particular sextant, as shown in Figure 11.

This Ex-OR table may be stored as a reduced LUT, which is offset addressed by the sum of the sextant number and the PIB, as shown in Figure 1 1 .

To generate the complete 3-phase PWM cycle from the 2 N t 1 timer intervals Atk (per 1/6 cycle), it is only necessary to add the PIB to the sextant number, access the Ex-OR data from the L U T and EX-OR, this with the present output state, as illustrated in Figure 1 I. The sextant number is incremented at the end of each 1/6th of a cycle, with a Modulo 3 characteristic, such that, when sextant number = 4, reset sextant number to 1, as shown in Fig. 11. Thus, when a 1/6th of a cycle has been timed out, the phase pointers are moved to the next 1/6th of a cycle position in the LUT, and the phases alternated between the 0-60" and 120-180" switching patterns sequence given in the table above. The main components of the PWM generation process may therefore be itemised in descending order of priority, as:
010 000 100
110

Phase A 0-60' Swrlching patlern

1
I

Phase B 120'- 180' Switching pattern

60-U

I
Phase C 60'-120' No switching

Timing vector

010 000

100

ABC Switching vector

( I ) Pulse-width Timing and Output (2) Pulse-width Calculation. (3) Feedback Control and/or Operator interface.
Fig.9 Item ( I ) to (3) can be run as "prioritised" parallel processes on the Transputer, with the highest priority process, item ( I ) , having access to the Ips resolution internal timer for timing out the 3phase PWM pulse-widths.
0-60' SWITCHING PATTERN IDENTIFIER BIT ( P I B I -0

Single-Timer Sextant Method

It is important to note, however, that during the timing-out of the pulse-widths, using the 1 fis internal timer, the Transputer gutomaticallv "deschedules" the timer process whilst waiting for the timer to "time-out". This allows other lower priority process, for example, the calculation of new switching angles, to continue. Once the internal timer has timed-out the Transputer automatically "reschedules" the highest priority process, which loads the next PWM time-delay into the timer [11,12]. Following the timing-out of a 1/6th of a cycle, the timing delay Atk vector and the two- phase switching pattern vector are reused, after the phase-pointer has been moved down one step (1/6th cycle) in the L U T in accordance with the phase switching sequence table given above. If, however, during the timing-out process new PWM conditions are demanded then the timing delay and switching vectors are recalculated and subsequently used. The output of the PWM gating signals to the inverter is via a memory-port mapped peripheral interface adaptor (PIA), connected to the inverter gating circuitry. Thus the complete 3-

120'- 180' SWITCHING PATTERN IOENTIFIER BIT (PI B I - 1

ZN+l

S WITCHINGS

TIMING VECTOR LUT

PHASE SWITCHING LUT

Fig.10

Single-Timer Look-Up Tables

As clearly illustrated in these Figures, the new PWM technique

frequencies and high voltages. Noting that the triple harmonics do not produce harmonic currents in the 3-phase system, as clearly shown in the Figures.

001
At6 A17

PRESENT INVERTER

b) N=9

29
Current

Voltage Fig.12 Regular sampled PWM V=O.Sp.u., 32Hz

r
11
13

11

13

15

17

19 21 23

17

19

23

Fig.13 Regular sampled PWM. 4 3 H z

(a)

= 7 to 5, V

= 1 . 1 pu.

(b)

5 t o 3, V

= 1.18 pu.

( c ) N = 3 t o QSU. V

= 1 27 F U

Fig.14

PWM to QSW Gear-Changing Transitions 346

Conclusions It has been shown that the problems associated with the off-line calculation and implementation of Harmonic Elimination PWM can be eliminated using well-established Regular-Sampled PWM techniques, suitably modified to include two phase-shifted niodulating waves. The new Regular-Sampled PWM strategy combines the advantages of a well-defined modulation process which can be simply and efficiently implemented, with the potential for generating on-line, Harmonic-Elimination/optimised PWM with in real-time, minimised THD. This provides optimal PWM drive performance over a wide voltage/frequency range up to QSW operation, with a smooth low harmonic distortion, transition from PWM to QSW mode. Only minor modifications to the previously developed and now well-established microprocessor-based Regular-Sampled PWM implementation are required to accommodate the new optimal PWM technique, thus existing PWM implementations can be straightforwardly updated to include optimal PWM. The new Regular-Sampled PWM techniques can also be applied to Uninterruptible Power Supplies, Static Frequency Converters and all Converters requiring Harmonic-Elimination/minimisedPWM. Acknowledgements The authors gratefully acknowledge the financial support provided by the UK Science and Engineering Research Council and U K Industry, and the excellent computing and experimental facilities provided by the University of Bristol. References

9.

Soni, S. and Huri, Y., "Harmonic elimination of microprocessor controlled PWM inverter for electrical traction", Ibid., Industrial and Control Applications of Microprocessors, 1979, pp. 278-283. Buja, G.S. and Fiorini, P.,
"A microprocessor-based quasi-continuous output

10.

controller for PWM inverters", Ibid., 1980, pp. 107-111. "The Transputer Family" Ref. No. 72 T R N 056 01, 1987. INMOS Ltd., Bristol, U.K. 12. 13,
"A Tutorial Introduction to OCCAM Programming".

Ref. No. 72 OCC 04307, 1987. Bowes, S. R. and Davies, T., "Microprocessor-based development system for PWM variable-speed drives", IEE, Proc., B, 1985, 132(1), pp. 18-45. Bowes, S. R, and Midoun, A., "Microprocessor implementation of new optimal PWM switching strategies", Ibid., 1988, 133(2), pp.1-12.

14,

I.

Bowes, S.R. and Clark, P.R. "Transputer based harmonic-elimination PWM control of Inverter Drives", IEEE IAS 1989 Conf. pp. 744-752. Bowes, S.R. and Clark, P.R. "Transputer based optimal PWM control of inverter drives," IEEE, IAS 1988 Conf., pp 315-321. Patel, H.S. and Hoft, R.G., "Generalised techniques of harmonic elimination", IEEE Trans., 1973, IA-9, pp.310-317. Patel, H.S. and Hoft, R.G., "Generalised techniques of harmonic elimination and voltage control in thyristor inverters": Part 2 - "voltage control techniques" Ibid., 1974, IA-10, pp.666-673. Buja, G.S. and Indri G.B., "Optimal pulse-width-modulation for feeding AC motors", Ibid., 1977, IA-13, pp.38-44. Bowes, S.R., "New sinusoidal pulsewidth modulated inverter", IEE Proc., 1975, 122(1 I), pp.1279-1285. Bowes, S.R. and Clement, R.R., "Computer aided design of PWM inverter systems" IEE Proc., B, Electr. Power Appl., 1982, 129(1), pp.1- 17.. Dwyer, E. and Ooi, B.T., "A look-up table based microprocessor controller for a three-phase PWM inverter", IEEE, IECI Proceedings: Industrial and Control Applications of Microprocessors, 1979, pp. 19-22. 347

2.

3.

4.

6.

7.

8.