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ID 9A 9A 9A
3 1 2
TO-220FP
Extremely high dv/dt capability 100% avalanche tested Gate charge minimized Very low intrinsic capacitances Very good manufacturing repeability
TO-247
Description
The SuperMESH series is obtained through an extreme optimization of STs well established strip-based PowerMESH layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications.
Applications
Switching application
Order codes
Part number STP10NK80Z STP10NK80ZFP STW10NK80Z Marking P10NK80Z P10NK80ZFP W10NK80Z Package TO-220 TO-220FP TO-247 Packaging Tube Tube Tube
July 2006
Rev 6
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Contents
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................. 6
3 4 5
Test circuit
................................................ 9
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Electrical ratings
Electrical ratings
Table 1.
Symbol VDS VDGR VGS ID ID IDM(2) PTOT
Peak diode recovery voltage slope Insulation withstand voltage (DC) Operating junction temperature Storage temperature
VISO TJ Tstg
1. Limited only by maximum temperature allowed 2. Pulse width limited by safe operating area 3. ISD di/dt 9A, 200A/s,VDD V(BR)DSS, Tj TJMAX
Table 2.
Symbol Rthj-case Rthj-a Tl
Thermal data
Value Parameter TO-220 TO-220FP Thermal resistance junction-case Max Thermal resistance junction-ambient Max Maximum lead temperature for soldering purpose 0.78 62.5 300 3.1 TO-247 0.78 50 C/W C/W C Unit
Table 3.
Symbol IAS EAS
Avalanche characteristics
Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj Max) Single pulse avalanche energy (starting Tj=25C, Id=Iar, Vdd=50V) Value 9 290 Unit A mJ
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Electrical characteristics
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 4.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test condictions ID = 1mA, VGS= 0 VDS = Max rating, VDS = Max rating @125C VGS = 20V VDS= VGS, ID = 100A VGS= 10V, ID= 4.5A 3 3.75 0.78 Min. 800 1 50
10
Typ.
Max.
Unit V A A nA V
4.5 0.9
Table 5.
Symbol gfs (1) Ciss Coss Crss
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Test condictions VDS =15V, ID = 4.5A Min. Typ. 9.6 2180 205 38 105 72 12.5 37 Max. Unit S pF pF pF pF nC nC nC
Coss eq(2). Equivalent output capacitance Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge
VGS=0, VDS =0V to 640V VDD=640V, ID = 9A VGS =10V (see Figure 19)
1. Pulsed: pulse duration=300s, duty cycle 1.5% 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS inceases from 0 to 80% VDSS
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Electrical characteristics
Table 6.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on Delay Time Rise Time Test condictions VDD=400 V, ID=4.5A, RG=4.7, VGS=10V (see Figure 20) VDD=400 V, ID=4.5A, RG=4.7, VGS=10V (see Figure 20) Min. Typ. 30 20 Max. Unit ns ns
65 17
ns ns
Table 7.
Symbol
1. The built-in back-to-back Zener diodes have specifically been designed to enhance not only the devices ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the devices integrity. These integrated Zener diodes thus avoid the usage of external components.
Table 8.
Symbol ISD ISDM(1) VSD(2) trr Qrr IRRM
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300s, duty cycle 1.5%
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Electrical characteristics
2.1
Figure 1.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
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Figure 9.
Transconductance
Figure 11. Gate charge vs gate-source voltage Figure 12. Capacitance variations
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Test circuit
Test circuit
Figure 19. Gate charge test circuit
Figure 20. Test circuit for inductive load Figure 21. Unclamped Inductive load test switching and diode recovery times circuit
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P
Q
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DIM. A B D E F F1 F2 G G1 H L2 L3 L4 L5 L6 L7
L3 L6 L7
F1 F
G1 H
F2
L2 L5
E
1 2 3
L4
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DIM. A A1 b b1 b2 c D E e L L1 L2 P R S
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Revision history
Revision history
Table 9.
Date 08-Sep-2005 10-Mar-2006 28-Sep-2005
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