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8051 Interfacing
Address Mapping
Use address bus and data bus Interfaced device show up as memory locations from the processor They use up some of the address space Memories, displays etc
I/O Mapping
Connect the devices to the I/O Ports of the processor Dont use up address space Sensors, pushbuttons, LCDs, motors, LEDs etc
12-Sep-02
Device 1
12-Sep-02
What is needed ?
Need to know the following for all the devices before address generator can be designed
Base address of each device Where it starts in the address map Size of the device How much of the address space it uses up
Code RAM 4K RAM1 32K 0x1000 Code ROM1 4K0x5000 0x0000 0x4000 Code Memory Data Memory
LCD 8b LEd 2b
12-Sep-02
11 lowest address bits A10 to A0 have to be connected to the address pins on the memory
12-Sep-02
Example 1 : (contd.)
Unused address bits are
A15 to A11
Truth-Table for CE
A15 A14 A13 A12 A11 0 0 0 0 0 X X 1 X 1 1 X 1 1 X X _CE
Base address is 0x0000 CE has to be generated if all the unused address bits are logic-0
X X X X X X X
0 1 1 1 1 1
12-Sep-02
X X X and X
0 1 1 1 so 1 1
_CE
X X X on X
X 0
X 0
X X 1 1
0 0 1 0 1
_ CE = A A A A A11 15 14 13 12
7
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1 0 1 1 1 1 1 1 1
(In)Complete Addressing
Complete addressing:
Use all unused address bits to generate CE
Incomplete addressing
Use a sub-set of the unused address bits Used to reduce the address generator complexity Produces address aliases (same device at multiple addresses)
Example
2K memory at 0x0000, we used A15 to A11 Instead just connect A11 to _CE Same 2K memory device will then be aliased for all values of A15 to A12 0x0000, 0x1000, 0x2000, 0x3000, . , 0xF000 Address generator became very simple, but we lost a lot of address space
12-Sep-02
C B A
G2 G1
Y0 Y1 Y2
GND Vcc
Y7 74LS138
For more complicated address decoding use programmable devices like PALs, PLDs or FPGAs
9
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11
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12
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13
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14
8Kx8 external code memory in 28C64 EEPROM Code memory at 0x0000 32Kx8 external code+data overlapped in 62256 SRAM. SRAM mapped at 0x8000
15
12-Sep-02
17 16