Table of Contents:

Contents
Contents..................................................................................................................... 1 1.0 Abstract:............................................................................................................... 2 2.0 Objective:............................................................................................................. 2 3.0 Introduction:......................................................................................................... 2 3. 01 Hypothesis:.....................................................................................................4 3.02 Literature Survey / State of the Art.................................................................4 3.04 Motivation and Application..............................................................................5 4.0 Proposed Work:.................................................................................................... 5 4.01 Method:........................................................................................................... 5 4.02 Scope of Work:................................................................................................6 4.03 Specifications:.................................................................................................9 4.04 Statement of Work:.........................................................................................9 5.0 Summary and Conclusion:..................................................................................10 6.0 Proposed Schedule:............................................................................................11 7.0 References:........................................................................................................ 12

1.0 Abstract:
This paper proposes architecture development of a datalink layer and its implementation for an endpoint of a PCI express core with PCIe 2.1 base specifications. This project will implement data link layer transmitter and receiver part of a PCI express IP core in systemverilog, and will develop effective test benches for functional and timing verification. Further this part will be integrated and tested with transaction layer part of the PCI Express core project.

2.0 Objective:
Objective of the project is implementing data link layer for a PCI express endpoint that features a good architecture. Further the project focuses on improving reusability of the core, by developing all the modules of the project in the reusable form. The objective also includes integrating the data link layer part with transaction layer part of other project.

3.0 Introduction:
With explosive growth in computing and communication technologies the bandwidth requirements for processors and I/O devices is continuously increasing. For more than the last decade PCI bus acted as a solution provider for this requirement, but it failed with todays increasing I/O and complex processor requirements. PCI Express provided solution for the above requirements. This third generation I/O system developed by PCI SIG, carried forward important features of PCI and integrated
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it with the new developments that took place in computer architecture. With high speed and point to point technology, it provided high bandwidth at a low pin count. The PCI express 2.1 Base specification defines the transmission and reception data rate upto 5 Gbit/s. PCI express has a layered architecture. It consists of three layers Transaction layer, Datalink layer, and Physical layer. Each layer has two parts, transmitter that processes

Figure 1
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the data that is to be transmitted and the receiver part that processes the received data. The communication between the transmitter of one device and the receiver of another device is in the form of packets. Formation of the packets takes place at the transaction layer. As the packets moves through other layers it gets appended with additional information. This information is required for processing of packets at that particular layer. From the physical layer the data is transmitted over a serial link from one device to another device. This project focuses on the data link layer part of the PCI express, which will be integrated with transaction layer and other part of the PCI express core project.

3. 01 Hypothesis:
Good implementation of PCI express core is based on better architecture design. Designing an effective architecture of the data link layer with a proper interface will result in the overall improvement in the implementation of PCIe IP core.

3.02 Literature Survey / State of the Art

PCI Express is a serial interconnect standard based on as packet based transmission. The reliability of the interconnect lies on implementation of the various features that it supports. This includes flow control for buffer space management, data integrity checks and packet retransmission upon failure of delivery. Implementation of such a system is complex process and often involves latency overhead. The performance of the PCIe core depends on two classes of parameters, design specification class and design implementation class. The design implementation class suggests that improving the parameters such as replay and receiver buffer sizes and flow control credit update latencies, ACK/NAK latencies core design can give a better performance.
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These

parameters are architecture specific and improper architecture may adversely affect the performance. For a good architecture, it is necessary to understand the ways to improve these parameters.

3.04 Motivation and Application

Data link layer forms an important part of the PCI express core from the point of view of implementation. Problems with performance and latencies mostly lie in this part of the core. Study of these parameters and its use in architecture development is the main motivation behind this project. Along with this making it reusable for ease of integration also forms a part of the motivation.

4.0 Proposed Work:

As mentioned earlier PCI express has a layered architecture with three layers namely transaction layer, datalink layer and physical layer. The project focus will be on the datalink layer of the PCI express IP core. This section of the proposal provides specifics on technical details with appropriate block diagrams. This will assist a reader to get a clear understanding of scope of the work, methodology of implementation, and specifications related to the project.

4.01 Method:
The proposed design method concentrates on the implementing the datalink layer transmitter and receiver with systemverilog and integrating it with transaction layer that forms the other part of the whole project. The first step in the methodology is to define architecture for the data link transmitter and receiver. Architecture of the blocks is

developed in such a way that they support optimum performance and reusability such that it can be integrated in any PCIe core as a separate IP core. Architecture development stage is followed by RTL coding of the IP core, in which various blocks of the data link layer will be implemented in verilog. The complete functional verification of the blocks will be done at individual block level as well system as a whole. The complete process of RTL coding and verification process will use verilog 2001 as a hardware description language and system verilog for verification on VCS simulation tool. The synthesis part will be performed using Synopsys Design Vision or Design Compiler using Toshiba tc240c.db_NOMIN25 libraries.

4.02 Scope of Work:

Implementing PCIe core is a complex process. This project limits its scope to designing a data link layer of the IP core and integrating it with the transaction layer part of the complete project. The highlighted part in the following block diagram depicts the scope of the work in the entire system.

Figure 2

The detailed block diagram of the data link layer will be as shown in figure 3:

Figure 3 It will consist of two sides a transmitter side and as receiver side. At the transmitter side the datalink layer will accept the packets from the transaction layer. The datalink layer will append it with sequence number and LCRC generated by sequence generator and LCRC generator respectively, and send them to physical layer. Data link transmitter will also have a replay buffer to retransmit the unacknowledged packets. There will be a DLLP generator to generate datalink layer packets used to exchange flow control. On the receiver the integrity of the transmitted packet will be checked using side LCRC checker. Depending on the LCRC and sequence number either ACK or NACK DLLP will

be sent back. The correct data will further be transmitted to Transaction layer receiver buffer after its being decoded.

4.03 Specifications:

PCI express 2.1 base specifications. End point configuration. 2.5 and 5 Gbit/s bit rate. Implementation using tc240c.db_NOMIN25 Toshiba synthesis libraries.

4.04 Statement of Work:

This project implements data link layer of the PCI express core for an endpoint with the PCIe 2.1 base specifications. The major activities that will be involved are as shown in table 1: Table 1 Activity Architecture Development Interface Development Timing Diagrams RTL coding Test-Plan Development Test-bench Development and Functional Verification Synthesis Debug Project Report Writing Deliverable Comment Block diagram for Architecture. Describes the connections Interface Requirements between various modules. Timing requirements RTL code for project Using System Verilog. Plan for Testing With System Verilog using Test Reports VCS simulator tc240c.db_NOMIN25 Libraries Synthesized Netlist using Design Vision tool. Revised RTL / Netlist Report Approved by Advisors

5.0 Summary and Conclusion:

Implementing an effective data link layer of the PCIe core is possible by developing a better architecture. Better architecture may result in good performance. Also designing a reusable module makes the integration of a module in a larger project simpler and convenient.

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6.0 Proposed Schedule:

Table 2 Activity Research and Literature Survey Finalizing Specifications Project Proposal Submission Architecture Development Interface Development Timing Diagram RTL Coding Testplan Development Test-bench Development Synthesis Debug Project Report Time for Completion 02/28/2010 02/28/2010 04/09/2010 04/30/2010 04/30/2010 05/30/2010 09/30/2010 09/30/2010 10/15/2010 9/30/2010 11/15/2010 11/30/2010

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7.0 References:
[1] Ajay Bhatt Creating a PCI ExpressTM interconnect PCI Express White Paper, <www.pcisig.com>. [2] Ravi Budruk, Don Anderson, and Tom Shanley, PCI Express System Architecture, MindShare, 2003 [3] K Yogendhar, Vidhya Thyagarajan, Sriram Swaminathan."Realizing the

Performance Potential of a PCI-Express IP. [4] PCI SIG. PCI-Express base specification Rev 2.1. PCI SIG.

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