INTRODUCTION___________

The different topologies of multilevel converters show a number of characteristics in common, giving them some clear advantages over bi-level converters, such as: 1. reduction in the commutation frequency applied to the components, 2. reduction in the voltages applied to the main power switches, enabling operation at higher load voltages, 3. transient voltages automatically limited. The main disadvantage associated with the multilevel configurations is their circuit complexity, requiring a high number of power switches that must be commutated in a precisely determined sequence by a dedicated (and complex) modulator circuit; they also require a great number of auxiliary dc levels, provided either by independent supplies or, more commonly, by a cumbersome array of capacitive voltage dividers. In this case, ensuring that the dc voltages are kept in equilibrium is another factor that increases the complexity of the modulator circuit. In the past, these disadvantages were almost overwhelming, due to the cost differences they produced between multilevel and standard configurations. Multilevel converters were used only
1

power

in some high power applications such as high power motor drivers in marine, mining, or chemical industries applications, high power

transmission, power line conditioners, where their advantages compensate the cost differential. The continuing development of high power high switch frequency devices such as insulated-gate bipolar transistors (IGBTs) working at 3.3, 4.5, and 6.5 kV, and insulated-gate commutated thyristors (IGCT) working at 4.5 or 6 kV, has improved overall converter performance, renewing the interest in multilevel topologies, that may be able to compete in the market with the standard two-level pulse width modulation (PWM) converters at lower power ranges. Initially, the main interest was concentrated in three-level configurations but recently four- and five-level converters have also been reported. Even taking into account the technological tendency to lower the prize at which multilevel converters can compete with standard configurations, the prize difference will remain unless the complexity issue is solved at the power circuit. As a contribution to solve this problem (cumbersome power stages), the project proposes a new converter topology, presented as a block diagram in Fig. 1.

This topology includes an H-bridge stage with an auxiliary bidirectional switch, drastically reducing the power circuit complexity. The new converter topology used in the power stage offers an important improvement in terms of lower component count and reduced layout complexity when compared with the five-level converters. The new topology achieves almost a 40% reduction in the number of main power switches required and uses no more diodes or capacitors that the second best topology, the asymmetric cascade configuration.

INVERTERS___________________
2.1 INTRODUCTION
Dc-to-ac converters are known as inverters. The function of an inverter is to change dc input voltage to a symmetric ac output voltage of desired magnitude and frequency. The output voltage could be fixed or variable at a fixed or variable frequency. A variable output voltage can be obtained by varying the input dc voltage and maintaining the gain of the inverter constant. On the other hand, if dc input voltage is fixed and it is not controllable, a variable output voltage can be obtained by varying the gain of the inverter, which is normally accomplished by pulsewidth-modulation control within the inverter. The inverter gain may be defined as the ratio of ac output voltage to dc input voltage. The output voltage waveforms of ideal inverters must be sinusoidal. However, the waveforms of practical inverters are non-sinusoidal and contain certain harmonics. For low- and mediumpower applications, square-wave or quasi-square-wave voltages may be acceptable; and for high-power applications, low distorted sinusoidal waveforms are required. With the availability of high-speed power

semiconductor devices, the harmonic contents of the output voltage can be reduced significantly by switching techniques. Inverters can be broadly classified into two types: (1) single-phase inverters, and (2) three-phase inverters. Each type can use controlled turn=on and turnoff devices (BJTs, MOSFETs, IGBTs, MCTs, SITs, and GTOs). These inverters generally use PWM control signals for producing an ac output voltage. An inverter is called a voltage-fed inverter (VFI) if the input voltage remains constant, a current-fed inverter (CFI) if the input current is maintained constant, and a variable dc linked inverter if the input voltage is controllable. If the output voltage or the current of the inverter is forced to pass through zero by creating an LC resonant circuit, this type of inverter is called resonant pulse inverter and it has wide applications in power electronics.

2.2 SINGLE-PHASE INVERTERS

The principle of single-phase inverters can be explained with Fig. 2.1a.

When only transistor Q1 is turned on for a time To/2, the instantaneous voltage across the load is Vs/2. If transistor Q2 only is turned on for a time To/2, -Vs/2 appears across the load. The logic circuit should be designed such that Q1 and Q2 are not turned on at the same instant. Fig. 2.1b shows the waveforms for the output voltage with a resistive load.

This inverter is known as half-bridge inverter.

2.2 SINGLE-PHASE BRIDGE INVERTERS

A single-phase bridge voltage source inverter (VSI) is shown in fig. 2.2a.

When transistors Q1 and Q2 are turned on simultaneously, the input voltage Vs appears across the load. If transistors Q3 and Q4 are turned on at the same time, the voltage across the load is reversed and is Vs. The waveform for the output voltage is shown in fig. 2.2b.

2.3 THREE-PHASE INVERTERS

Three-phase inverters are normally used for high power applications. Three single-phase half or full -bridge inverters can be connected in parallel as in fig. 2.3a to form the configuration of a three-phase inverter.

The gating signals of single-phase inverters should be advanced or delayed by 120 degrees with respect to each other to obtain three-phase balanced voltages. The transformer primary windings must be isolated from each other, whereas the secondary windings may be connected in Y or delta. The transformer is normally connected in delta to eliminate triplen harmonics

(n=3, 6, 9 ) appearing on the output voltages and the circuit arrangement is shown in fig. 2.3b.

This arrangement requires three single-phase transformers, 12 transistors and 12 diodes. If the output voltages of the single-phase inverters are not perfectly balanced in magnitudes and phases, the three-phase output voltages are unbalanced.

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A three-phase output can be obtained from a configuration of 6 transistors and 6 diodes as shown in fig. 2.3c.

Two types of control signals can be applied to the transistors: 180 degrees conduction or 120 degrees conduction. The 180 degrees conduction has better utilization of the switches and is the preferred method.

180 Degrees Conduction:Each transistor conducts for 180 degrees. Three transistors remain on at any instant of time. When transistor Q1 is switched on, terminal a is connected to positive terminal of the DC input voltage. When transistor Q4 is switched on, terminal a is brought to negative terminal of the DC source. There are six modes of operation in a cycle and the duration of each mode is 60 degrees. The gating signals shown

11

in fig. 2.3d are shifted from each other by 60 degrees to obtain three-phase balanced (fundamental) voltages.

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The load may be connected if Y or delta. The switches of any leg of the inverter (S1, and S4, S3 and S6, or S5 and S2) cannot be switched on simultaneously; this would result in a short circuit across the dc link voltage supply. Similarly, to avoid undefined states and thus undefined ac output line voltages, the switches of any leg of the inverter cannot be switched off simultaneously; this can result in voltages that depend on the respective line current polarity.
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120-Degree Conduction:In this type of control, each transistor conducts for 120 degrees. Only two transistors remain on at any instant of time.

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The control signals are shown in fig. 2.3e. The conduction sequence of transistors is 61,12,23,34,45,56,61.

2.4 VOLTAGE CONTROL OF SINGLE PHASE INVERTERS

In many industrial applications, to control of the output voltage of inverters is often necessary 1. to cope with the variations of dc input voltage 2. to regulate voltage of inverters and 3. to satisfy the constant volts and frequency control equipment. There are various techniques to vary the inverter gain. The most efficient method of controlling the gain is to incorporate Pulse Width Modulation control with in the inverters. The commonly used techniques are:
1. Single-pulse-width modulation. 2. Multiple-pulse-width modulation. 3. Sinusoidal pulse-width modulation. 4. Modified sinusoidal pulse-width modulation. 5. Phase-displacement control.

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2.4.1 Single pulse width modulation:

In single pulse width modulation control, there is only one pulse per half-cycle and the width of the pulse is varied to control the inverter output voltage. The generation of control signals and inverter output voltage for single phase full bridge inverters is shown in fig. 2.4a. The control signals are generated by comparing a rectangular reference signal of amplitude Ar with a triangular carrier wave of amplitude Ac. The frequency of the reference signal determines the fundamental frequency of output voltage. The instantaneous output voltage is vo=Vs(g1-g4). The ratio of Ar to Ac is the control variable and defined as the amplitude modulation index and given as M = Ar/Ac

16

The RMS output voltage can be found from

by varying Ar from 0 to Ac, the pulse width can be modified from 0 to 180 and the RMS output voltage Vo, from 0 to Vs.

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3.4.2 MULTIPLE PULSE WIDTH MODULATION

The harmonic content can be reduced by using several pulses in each half-cycle of output voltage. The generation of control signals for turning on and off of transistors is shown in fig. 2.4b.a by comparing a reference signal with a triangular carrier wave. The control signals are shown in fig. 2.4b.b. The frequency of reference signal sets the output frequency fo, and the carrier frequency fc determines the number of pulses per half-cycle p. The modulation index controls the output voltage. This type of modulation is also known as uniform pulse width modulation (UPWM). The number of pulses per half-cycle is found from P = fc / 2fo = mf / 2

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Where mf = fc / fo is defined as the frequency modulation ratio. The instantaneous output voltage is vo= Vs(g1-g4). The output voltage for single phase bridge inverters are shown in fig. 2.4b.c. If (delta) is the width of each pulse, the RMS output voltage can be found from

The variation of the modulation index M from 0 to 1 varies the pulse width d from 0 to T/2p ( 0 to /p) and RMS output voltage Vo from 0 to Vs.

2.4.3 SINUSIODAL PULSE WIDTH MODULATION

Instead of maintaining the width of all pulses the same as in the case of multiple-pulse modulation, the width of each pulse is varied in proportion to the amplitude of a sine wave evaluated at the center of the same pulse. The distortion factor and lower order harmonics are reduces significantly. The control signals are generated by comparing a sinusoidal reference signal with a triangular carrier wave of frequency fc as shown in fig. 2.4c. This sinusoidal pulse width modulation is commonly used in industrial applications. The frequency of reference signal fr determines the inverter output frequency fo, and its peak amplitude Ar
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controls the modulation index m, and then in turn the RMS output voltage Vo. Comparing the bi-directional carrier signal vcr with two sinusoidal reference signals vr and vr, produces control signals gt1 and g4 respectively as shown in fig. 2.4.c.b. The output voltage is vo = Vs(g1-g4). However, g1 and g4 can not be released at the same time. The number of pulses per half-cycle depends on the carrier frequency. Within the constraint that twotransistors of the same arm(Q1 andQ4) cannot conduct at the same time, the inatantaneous output voltage is shown in fig. 2.4.c.c. The same control signals can be generated y using unidirectional triangular carrier wave as in fig. 2.4.c.d. It is easier to implement this method and is preferred. The generation of control signals is similar to that for the UPWM, except the reference signal is a sine wave vr= Vr sin wt, instead of a dc signal. The output voltage is vo = Vs(g1-g4).

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Fig. 2.4.c Sinusoidal PWM The RMS output voltage can be varied by varying the modulation index M. it can be observed that the area of each pulse corresponds approximately to the area under the sine wave between the adjacent midpoints of off periods on the control signals.

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If (m) is the width of mth pulse, then the RMS output voltage is

The output voltage of an inverter contains harmonics. The PWM pushes the harmonics into a high-fequency range around the switching frequency fc and its multiples, that is , around harmonics mf, 2mf, 3mf and so on.

2.4.4 MODIFIED SINUSOIDAL PULSE WIDTH MODULATION

Fig. 2.4.d indicates that the widths of pulses nearer the peak of the sine wave do not change significantly with the variation of modulation index. This is due to the characteristics of a sine wave , and the SPWM technique can be modified so that the carrier wave is applied during the first and last 60 degree intervals per half-cycle(e.g.,) to 60 and 120 to 180). This modified sinusoidal pulse width modulation is shown in fig. 2.4.d. The fundamental component is increased and its harmonic characteristics are improved. It reduces the number of switching of power devices and also reduces switching losses.

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Fig. 2.4.d Modified sinusoidal pulse width modulation The number of pulses q in the 60 degree period is normally related to the frequency ratio, particularly in three-phase inverters by fc / fo = 6q + 3.

The instantaneous output voltage is vo= Vs(g1-g4). The algorithm for generating the control signals is similar to that for sinusoidal PWM, except the reference signal is a sine wave from 600 to 1200 only.

2.4.5 PHASE DISPLACEMENT CONTROL

Voltage control can be obtained by using multiple inverters and summing the output voltage of individual inverters. A single phase full bridge inverter in fig. 2.4e can be perceived as the sum of two-bridge inverters in fig. 2.4e. a 1800 phase displacement produces an output voltage as shown in fig. 2.4e whereas a delay or displacement angle of produces an output as shown in fig. 2.4e
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The RMS output voltage,

The RMS value of fundamental output voltage is

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MULTILEVEL INVERTERS
3.1 INTRODUCTION
The voltage source inverters produce an output voltage or a current with levels either 0 or +/_ Vdc. They are known as two level inverters. To obtain a high quality output voltage or current waveform with a minimum amount of ripple content, they require high-switching frequency along with various pulse width modulation strategies. In high power and high voltage applications, these two level inverters, however, have some limitations in operating at high frequency mainly due to switching losses and constraints of device rating. Moreover, the semiconductor switching devices should be used in such a manner as to avoid problems associated with their series parallel combinations that are necessary to obtain capability of handling high voltages and currents. The multilevel inverters have drawn tremendous interest in the power industry. They present a new set of features that are well suited for use in reactive power compensation. It may be easier to produce a high power, high voltage inverter with the multilevel structure because of the way in which device voltage stresses are controlled in the structure. Increasing the number of voltage levels in the inverter without

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requiring higher ratings on individual devices can increase the power rating. The unique structure of multilevel voltage source inverters allows them to reach high voltages with low harmonics without the use of transformers or series-connected synchronized, switching devices. As the number of voltage levels increases, the harmonic content of the output voltage waveform decreases significantly.

3.2 MULTILEVEL CONCEPT

Let us consider a three phase inverter system, as shown in fig. 3.2a, with a dc voltage Vdc. Seriesconnected capacitors constitute the energy tank for the inverter, providing some nodes to which the multilevel inverter can be connected. Each capacitor has the same voltage Em, given by, Em=Vdc/(m-1) where m denotes the number of levels. The term level is referred to as the number of nodes to which the inverter can be accessible. An m-level inverter needs (m-1) capacitors.

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Output phase voltages can be defined as voltages across the output terminals of the inverter and the ground point denoted by o as shown in fig. 3.2a (a). Moreover, input node voltages and currents can be referred to input terminal voltages of the inverter with reference to ground point and the corresponding currents from each node of the capacitor to the inverter, respectively. For example input node (dc) voltages are designated by V1, V2, etc. and the input node dc currents by I1, I2, etc. as shown in fig. 3.2a. Va, Vb, and Vc are the root-mean-square (rms)
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values of the line load voltages; Ia, Ib, and Ic are the rms values of the line load currents. Fig. 3.2a(b) shows the schematic of a pole in a multilevel inverter where Va indicates an output phase voltage that can assume any voltage level depending on the selection of node (dc) voltage V1, V2, etc. Thus, a pole multilevel inverter can be regarded as a single-pole multiplethrow switch. By connecting the switch to one node at a time, one can obtain the desired output. Fig. 3.2b shows the typical voltage of a five level inverter.

The actual realization of the switch requires bidirectional switching devices for each node. The topological structure of the multilevel inverter must (1) have less switching devices as far as possible.

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(2) be capable of withstanding very high input voltage for high power applications, and (3) have lower switching frequency for each switching device.

3.3 TYPES OF MULTILEVEL INVERTERS

The general structure of the multilevel converter is to synthesize a near sinusoidal voltage from several levels of dc voltages, typically obtained from capacitor voltage sources. As the number of levels increases, the synthesized output waveform has more steps, which produces s staircase wave that approaches a desire waveform. Also, as more steps are added to the waveform, the harmonic distortion of the output wave decreases, approaching zero as the number of levels increases. As the number of levels increases, the voltage that can be spanned by summing multiple voltage levels also increases. The output voltage during the positive half cycle can be found from,

where SFn is the switching or control function of nth node and it takes a value of 0 or 1. Generally the capacitor terminal voltages E1, E2 all have the same value Em. Thus, the peak output voltage is

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To generate an output voltage with both positive and negative values, the circuit topology has another switch to produce the negative part

The multilevel inverters can be classified into three types. Diode-clamped multilevel inverter; Flying-capacitors multilevel inverter; Cascade multilevel inverter.

3.4 DIODE-CLAMPED MULTILEVEL INVERTER

A diode-clamped multilevel (m-level) inverter (DCMLI) typically consists of (m-1) capacitors on the dc bus and produces m levels on the phase voltage. Fig 3.4a (a) shows one leg and fig. 3.4a (b) shows a full-bridge five level diode-clamped converter. The numbering order of the switches is Sa1, Sa2, Sa3, Sa4, Sa1, Sa2, Sa3, and Sa4. The dc bus consists of four capacitors C1, C2, C3, and C4. For a dc bus voltage Vdc, the voltage across each capacitor is Vdc/4, and each device voltage stress is limited to one capacitor voltage level Vdc/4 through clamping diodes. An m-level inverter leg requires (m-1) capacitors, 2(m-1) switching devices and (m-1)(m-2) clamping diodes.
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31

Fig 3.4a.

3.4.1 PRINCIPLE OF OPERATION To produce a staircase-output voltage, let us consider only one leg of the five-level inverter as shown in fig 3.4a(a) as an example. A single phase bridge with two legs is shown in fig. 3.4a(b). The

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dc rail 0 is the reference point of the output voltage. The steps to synthesize the five-level voltages are as follows:
1. For an output voltage Vao = Vdc, turn on all upper half switches Sa1

through Sa4.
2. For an output voltage level Vao = 3Vdc/4, turn on three upper switches

Sa2 through Sa4 and one lower switch Sa1.

3. For an output voltage level Vao = Vdc/2, turn on two upper switches

Sa3 and Sa4 and two lower switches Sa1 and Sa2.
4. For an output voltage level Vao = Vdc /4, turn on one upper switch Sa4

and three lower switches Sa1 through Sa3.

5. For an output voltage level Vao = 0, turn on all lower half switches

Sa1 through Sa4. Table 3.4 shows the voltage levels and their corresponding switch states. State condition 1 means the switch is on, and state 0 means the switch is off. It should be noticed that each switch is turned on only once per cycle and there are four complementary switch pairs in each phase. These pairs for one leg of the inverter are (Sa1, Sa1), (Sa2, Sa2), (Sa3, Sa3) and (Sa4, Sa4). Thus, if one of the complementary switch pairs is turned on, the other of the same pair must be off. Four switches are always turned on at the same time. Fig. 3.4b shows the phase voltage waveform of the five-level inverter.

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________________________________________________________________ TABLE 3.4 Diode-Clamped Voltage Levels and Switch States ________________________________________________________________ Switch State ______________________________________________ Sa1 Sa2 Sa3 Sa4 Sa1 Sa2 Sa3 Sa4 ________________________________________________________________ V5 = Vdc 1 1 1 1 0 0 0 0 V4 = 3Vdc/4 V3 = Vdc/2 V2 = Vdc/4 0 0 0 1 0 0 1 1 0 1 1 1 1 1 1 0 1 1 0 0 1 0 0 0 Output Vao

V1 = 0 0 0 0 0 1 1 1 1 ________________________________________________________________

The line voltage consists of the positive phase-leg voltage of terminal a and the negative phase-leg voltage of the terminal b. each phase-leg voltage tracks one-half of the sinusoidal wave. The resulting line voltage is a nine-

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level stair case wave. This implies that an m-level converter has an m-level output phase-leg voltage and a (2m-1) level output line voltage. 3.4.2 FEATURES OF DIODE CLAMPED INVERTER The main features are as follows:
1. High-voltage rating for blocking diodes: although each witching

device is only required to block a voltage level of Vdc/ (m-1), the clamping diodes need to have different reverse voltage blocking ratings. For example, when all lower devices Sa1 through Sa4 are turned on, diode Da1 needs to block three capacitor voltages or 3Vdc/4. Similarly, diodes Da2 and Da2 need to block 2Vdc/4, and Da3 needs to block Vdc/4. Even though each main switch is supposed to block the nominal blocking voltage, the blocking voltage of each clamping diode in the diode clamping inverter is dependent on its position in the structure. In a m-level leg, there can be two diodes, each seeing a blocking voltage of

where m is the number of levels; k goes from 1 to (m-1); Vdc is the total dc link voltage. If the blocking voltage rating of each diode is the same as that of the
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switching device, the number of diodes required for each phase is ND = (m-1)*(m-2). This number represents a quadratic increase in m. Thus, m=5, ND = (5-1)*(5-2) = 12. When m is sufficiently high, the number of diodes makes the system impractical to implement, which in effect limits the number of levels.
2. Unequal switching device rating: We can notice from Table 4.4 that

switch Sa1 conducts only during Va0 = Vdc, whereas switch Sa4 conducts over the entire cycle except during the interval when Vao = 0. Such an unequal conduction duty requires different current ratings for switching devices. Therefore, if the inverter design uses the average duty cycle to find the device ratings, the upper switches may be over-sized, and the lower switches may be undersized. If the design uses the worst case condition, then each phase has 2*(m-2) upper devices oversized.
3. Capacitor voltage unbalance: because the voltage levels at capacitor

terminals are different, the currents supplied by the capacitors are also different. When operating at unity power factor, the discharging time for inverter operation (or charging time for rectifier operation) for each capacitor is different. Such a capacitor charging profile repeats every half cycle, and the result is unbalanced capacitor voltages

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between different levels. This voltage unbalance problem in a multilevel converter can be resolved by using approaches such as replacing capacitors by a controlled constant dc voltage source, PWM voltage regulators, or batteries. The major advantages of the diode clamped inverter can be summarized as follows: When the number of levels is high enough, the harmonic content is low enough to avoid the need for filters. Inverter efficiency is high because all devices are switched at the fundamental frequency. The control method is simple. The major disadvantages of the diode clamped inverter can be summarized as follows: Excessive clamping diodes are required when the number of levels is high. It is difficult to control the real power flow of the individual converter in multi-converter systems. 3.4.3 IMPROVED DIODE-CLAMPED INVERTER The problem of multiple blocking voltages of the clamping diodes can be solved by connecting diodes in series, as in fig. 3.4.3a.

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Fig 3.4.3a However due to mismatches of the diode characteristics, the voltage sharing is not equal. An improved version of the diode clamped inverter is shown in fig. 3.4.3b for five levels.
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Fig 3.4.3b The numbering order of the switches is S1, S2, S3, S4, S1, S2, S3, and S4. There are a total of eight switches and 12 diodes of equal voltage rating, which are the same as the diode-clamping inverter with series-connected
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diodes. This pyramid architecture is extensible to any level, unless otherwise practically limited. A five-level inverter leg requires (m-1=)4 capacitors, (2(m-1)=) 8 switches and ((m-1)(m-2)=) 12 clamping diodes.
Principle of operation. The modified diode-clamped inverter can be

decomposed into two-level switching cells. For an m-level inverter, there are (m-1) switching cells. Thus, for m=5, there are 4 cells: in cell 1 S2, S3, and S4 are always on whereas S1 and S1 are switched alternatively to produce an output voltage Vdc/2 and Vdc/4 respectively. Similarly in cell 2, S3, S4, and S1 are always on

whereas S2 and S2 are switched on alternatively to produce an output voltage Vdc/4 and 0, respectively. In cell 3, S4, S1, and S2 are always on whereas S3 and S3 are switched alternatively to produce an output voltage 0 and -Vdc/2, respectively. In final cell 4, S1, S2, and S3 are always on whereas S4 and S4 are switched alternatively to produce an output voltage -Vdc/4 and -Vdc/2, respectively. Each switching cell works actually as a normal twolevel inverter, except that forward or freewheeling path in the cell involves (m-1) devices instead of only one. Taking cell 2 as an example, the forward path of up-arm involves D1, S2, S2, and S4, whereas the freewheeling path of the up-arm involves S1, D12, D8, and D2,

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connecting the inverter output to Vdc/4 level for either positive or negative current flow. The forward path of the down-arm involves S1, S2, D10, and D4, whereas the freewheeling path of the down-arm involves D3, D7, S3, and S4, connecting the inverter output to zero level for either positive or negative current flow. The following rules govern the switching of an m-level inverter: 1. At any moment, there must be (m-1) neighboring switches that are on. 2. For each two neighboring switches, the outer can only be turned on when the inner switch is on. 3. For each two neighboring switches, the inner switch can only be turned off when the outer switch is off.

3.5 FLYING-CAPACITORS MULTILEVEL INVERTER

Figure 3.5 shows a single-phase, full-bridge, five-level converter based on a flying capacitors multilevel inverter (FCMLI). The numbering order of the switches is Sa1, Sa2, Sa3, Sa4, Sa4, Sa3, Sa2, and Sa1. Note that the order is numbered differently from that of the diode-clamped inverter.

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Fig 3.5. The numbering is immaterial as long as the switches are turned on and off in the right sequence to produce the desired output waveform. Each phase keg has an identical structure. Assuming that each capacitor has the same

voltage rating, the series connection of the capacitors indicates the voltage level between the clamping points. Three inner loop balancing capacitors (Ca1, Ca2, and Ca3) for phase-leg a are independent from those for phaseleg b. all phase legs share the same dc-link capacitors, C1 through C4.

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The voltage level for the flying-capacitors converter is similar to that of the diode-clamped type of converter. That is, the phase voltage Vao of an m-level converter has m levels (including the reference level), and the line voltage Vab has (2m-1) levels. Assuming that each capacitor has the same voltage rating as the switching device, the dc bus needs (m-1) capacitors for an m-level converter. The number of capacitors required for each phase is . Thus, for m=5, Nc=10.

3.5.1 PRINCIPLE OF OPERATION To produce a staircase-output voltage, let us consider the leg of the fivelevel inverter shown in fig. 3.5a as an example. The dc rail 0 is the reference point of the output phase voltage. The steps to synthesize the five-level voltages are as follows: 1. For an output voltage level Vao = Vdc, turn on all upper-half switches Sa1 through Sa4. 2. For an output voltage level Vao = 3Vdc/4, there are four combinations: a. Vao = Vdc Vdc/4 by turning on devices, Sa1, Sa2, Sa3, and Sa4.
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b. Vao = 3Vdc/4 by turning on devices Sa2, Sa3, Sa4, and Sa1. c. Vao = Vdc 3Vdc/4 + Vdc/2 by turning on devices Sa1, Sa3, Sa4, and Sa2. d. Vao = Vdc Vdc/2 + Vdc/4 by turning on devices Sa1, Sa2, Sa4, and Sa3. 3. For an output voltage level Vao = Vdc/2, there are six combinations: a. Vao = Vdc Vdc/2 by turning on devices Sa1, Sa2, Sa3, and Sa4. b. Vao = Vdc/2 by turning on devices Sa3, Sa4, Sa1, and Sa2. c. Vao = Vdc 3Vdc/4 + Vdc/2 Vdc/4 by turning on devices Sa1, Sa3, Sa2, and Sa4. d. Vao = Vdc 3Vdc/4 + Vdc/4 by turning on devices Sa1, Sa4, Sa2, and Sa3. e. Vao = 3Vdc/4 Vdc/2 + Vdc/4 by turning on devices Sa2, Sa4, Sa1, and Sa3. f. Vao = 3Vdc/4 Vdc/4 by turning on devices Sa2, Sa3, Sa1, and Sa4. 4. For an output voltage level Vao = Vdc/4, there are four combinations: a. Vao = Vdc 3Vdc/4 by turning on devices Sa1, Sa2, Sa3, and Sa4.

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b. Vao = Vdc/4 by turning on devices Sa4, Sa1, Sa2, an Sa3. c. Vao = Vdc/2 Vdc/4 by turning on devices Sa3, Sa1, Sa2, and Sa4. d. Vao = 3Vdc/4 Vdc/2 by turning on devices Sa2, Sa1, Sa3, and Sa4. 5. For an output voltage level Vao = 0, turn on all lower half Sa1 through Sa4. There are many possible switch combinations to generate the five level output voltage. Table 3.4, however, lists a possible combination of the voltage levels and their corresponding switch states.
--------------------------------------------------------------------------------------------------TABLE 3.4 One Possible Switch Combination of the Flying-Capacitors Inverter --------------------------------------------------------------------------------------------------Output Switch State ---------------------------------------------------------------------------Vao Sa1 Sa2 Sa3 Sa4 Sa4 Sa3 Sa2 Sa1 --------------------------------------------------------------------------------------------------V5 = Vdc 1 1 1 1 0 0 0 0 V4 = 3Vdc/4 V3 = Vdc/2 V2 = Vdc/4 1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 0 1 1 0 0 1 0 0 0

V1 = 0 0 0 0 0 1 1 1 1 ---------------------------------------------------------------------------------------------------

Using such a switch combination requires each device to be witched only once per cycle. It can be noticed from table 4.5 that the switching devices
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have unequal turn-on time. Like the diode-clamped inverter, the line voltage consists of the positive phase leg voltage of terminal a and the negative phase leg voltage of terminal b. The resulting line voltage is a nine level stair case wave. This implies that an m-level converter has an m-level output phase leg voltage and a (2m-1)-level output line voltage.

3.5.2 FEATURES OF FLYING-CAPACITORS INVERTER The main features are as follows:

1. Large number of capacitors: The inverter requires a large

number of storage capacitors. Assuming that that the voltage rating of each capacitor is the same as that of the switching device, an m-level converter requires a total of (m-1)*(m-2)/2 auxiliary capacitors per phase leg in addition to (m-1) main dc bus capacitors. On the contrary, an m-level diode-clamped inverter only requires (m-1) capacitors of the same voltage rating. Thus, for m=5, Nc = 4*3/2+4 = 10 compared with Nc = 4 for the diode clamped type.
2. Balancing

capacitor voltages: Unlike the diode-clamped

inverter, the FCMLI has redundancy at its inner voltage levels. A voltage level is redundant if two or more valid switch

46

combinations can synthesize it. The availability of voltage redundancies allows controlling the individual capacitor voltages. In producing the same output voltage, the inverter can involve different combinations of capacitors allowing

preferential charging or discharging of individual capacitors. This flexibility makes it easies to manipulate the capacitor voltages and keep them at their proper values. It is possible to employ two or more switch combinations for middle voltage levels (i.e., 3Vdc/4, Vdc/2, and Vdc/4) in one or several output cycle to balance the charging and discharging of the capacitors. Thus, by proper selection of switch combinations, the flyingcapacitors multilevel converter may be used in real power conversion. However, when it involves real power conversions, the selection of a switch combination becomes very

complicated, and the switching frequency needs to be higher than the fundamental frequency. The major advantages of flying-capacitors inverter can be summarized as follows: Large amounts of storage capacitors can provide capabilities during power stages.

47

 These inverters provide switch combination redundancy for balancing different voltage levels. Like the diode-clamp inverter with more levels, the harmonic content is low enough to avoid the need for filters. Both real and reactive power flow can be controlled. The major disadvantages of the flying-capacitors inverter can be summarized as follows: An excessive number of storage capacitors is required when the number of levels is high. High-level inverters are more difficult to package with the bulky power capacitors and are more expensive too. The inverter can be very complicated, and the switching frequency and switching losses are high for real power transmission.

3.6 CASCADED MULTILEVEL INVERTER

A cascaded multilevel inverter consists of a series of H-bridge (single-phase, full-bridge) inverter units. The general function of this multilevel inverter is to synthesize a desired voltage from several separate dc sources (SDCS s), which nay be obtained from batteries, fuel cells or solar cells. Figure 3.6a (a) shows the basic structure of a single phase
48

cascaded inverter with SDCSs. Each SDCS is connected to an H-bridge inverter. The ac terminal voltages of different level inverters are connected in series. Unlike the diode-clamp or flying-capacitors inverter, the cascade inverter does not require any voltage-clamping diodes or voltage balancing capacitors.

49

Fig.3.6a. 3.6.1 PRINCIPLE OF OPERATION Figure 3.6a (b) shows the synthesized phase voltage waveform of a five-level cascaded inverter with four SDCSs. The phase output voltage is synthesized by the sum of four inverter outputs, Van = Va1 + Va2 + Va3 + Va4. Each level inverter can generate three different voltage outputs, +Vdc, 0, and Vdc, by connecting the DC source to the ac output side by different combinations of the four switches, S1, S2,

50

S3, and S4. Using the top level as the example, turning on S1 and S4 yields Va4 = +Vdc. Turning on S2 and S3 yields Va4 = -Vdc. Turning off all switches yields V4 = 0. Similarly, the ac output voltage at each level can be obtained in the same manner. If Ns is the number of dc sources, the output phase voltage level is m = Ns+1. Thus, a five-level cascaded inverter needs four SDCSs and four full bridges. Controlling the conduction angles at different inverter levels can minimize the harmonic distortion of the output voltage. The output voltage of the inverter is almost sinusoidal, and it has less than 5% total harmonic distortion with each of the H-bridges switching only at fundamental frequency. If the phase current Ia, as shown in Fig. 3.6a(b), is sinusoidal and leads or lags the phase voltage Van by 90 degrees, the average charge of each dc capacitor is equal to zero over one cycle. Therefore, all SDCSs capacitor voltages can be balanced.

51

Fig 3.6b Each H-bridge unit generates a quasi-square waveform by phase shifting its positive and negative phase leg switching timings. Figure 3.6b shows the switching timings to generate a quasi-square waveform of an Hbridge. It should be noted that each switching device always conducts for 180 degrees (or half-cycle), regardless of the pulse width of the quasi-square wave. This switching method makes all of the switching device current stresses equal.

3.6.2 FEATURES OF CASCADED INVERTER The main features are as follows: For real power conversions from ac to dc and then dc to ac, the cascaded inverter needs separate dc sources. The structure of the

52

separate dc sources is well suited for various renewable energy sources such as fuel cell, photovoltaic, and biomass. Connecting dc sources between two converters in a back-to-back fashion is not possible because a short circuit can be introduced when two back-to-back converters are not switching synchronously. The major advantages of cascaded inverter can be summarized as follows: Compared with diode-clamped and flying-capacitors inverters, it requires the least number of components to achieve the same number of voltage levels. Optimized circuit layout and packaging are possible because each level has the same structure and there are no extra clamping diodes or voltage-balancing capacitors. Soft-switching techniques can be used to reduce switching losses and device stresses. The major disadvantages of cascaded inverter are as follows: It needs separate dc sources for real power conversions, thereby limiting its applications.

53

3.7 FEATURES OF MULTILEVEL INVERTERS

A multilevel inverter can eliminate the need for step up transformer and reduce the harmonics produced by the inverter. Although the multilevel inverter structure was initially introduced as a means of reducing the output waveform harmonic content, it was found that the dc bus voltage could be increased beyond the voltage rating of an individual power device by the use of a voltage clamping network consisting of diodes. A multilevel structure with more than three levels can significantly reduce the harmonic content. By using voltage clamping techniques, the system KV rating can be extended beyond the limits of an individual device. The intriguing feature of the multilevel inverter structures is their ability to scale up the kilovolt-ampere (kVA)-rating and also to improve the harmonic performance greatly without having resort to PWM techniques. The key features of multilevel structure follow: The output voltage and power increase with number of levels. Adding a voltage level involves adding a main switching device to each phase. The harmonic content decreases as the number of levels increases and filtering requirements are reduced.

54

 With additional voltage levels, the voltage waveform has more free switching angles, which can be preselected for harmonic elimination. In the absence of any PWM techniques, the switching losses can be avoided. Increasing output voltage and power does not require an increase in rating of individual device. Static and dynamic voltage sharing among the switching devices is built into the structure through either clamping diodes or capacitors. The switching devices do not encounter ant voltage-sharing problems. For this reason, multilevel inverters can easily be applied for high power applications such as large motor drives and utility supplies. The fundamental output voltage of the inverter is set by the dc bus voltage Vdc, which can be controlled through a variable dc link.

3.8 COMPARISONS OF MULTILEVEL CONVERTERS

The multilevel converters can replace the existing systems that use traditional multipulse converters without the need for transformers. For a three-phase system, the relationship between the number of levels m, and the number of pulses p, can be formulated by p = 6*(m-1). All three converters have the potential for applications in high55

voltage, high power systems such as an SVG without voltage unbalance problems because the SVG does not draw real power. The diode-clamped converter is most suitable for the back-to-back intertie system operating as unified power flow controller. The other two types may also be suitable for the back-to-back intertie, but they would require more switching per cycle and more advanced control techniques to balance the voltage. The multilevel inverters can find potential applications in adjustable speed drives where the use of multilevel converters can not only solve harmonics and EMI problems but also avoid possible high-frequency switching dv/dt-induced motor failures. -------------------------------------------------------------------------------------------TABLE 3.8 Comparisons of Component Requirements per Leg of Three Multilevel Converters -------------------------------------------------------------------------------------------Converter Type Diode-Clamp Flying Capacitors Cascaded inverter -------------------------------------------------------------------------------------------Main Switching (m-1)*2 (m-1)*2 (m-1)*2 Devices Main diodes (m-1)*2 (m-1)*2 0 (m-1) (m-1)*2 0 (m-1)/2

Clamping diodes (m-1)*(m-2) DC bus Capacitors (m-1)

Balancing 0 (m-1)*(m-2)/2 0 Capacitors --------------------------------------------------------------------------------------------

56

Table 3.8 compares the component requirements per phase leg among the three multilevel converters. All devices are assumed to have the same voltage rating, but not necessarily the same current rating. The cascaded inverter uses a full bridge in each level as compared with the half bridge version for the other two types. The cascaded inverter requires the least number of components and has the potential for utility interface applications because of its capabilities for applying modulation and soft switching techniques.

3.9 SUMMARY
Multilevel converters can be applied to utility interface systems and motor drives. These converters offer a low output voltage THD, and a high efficiency and power factor. There are three types of multilevel converters: (1) diode clamped, (2) flying capacitors, and (3) cascade. The main advantages of multilevel converters include the following: They are suitable for high-voltage and high-current applications. They have higher efficiency because the devices can be switched at a low frequency. Power factor is close to unity for multilevel inverter used as rectifiers to convert ac to dc.
57

 No EMI problem exists. No charge unbalance problem results when the converters are in either charge mode (rectification) or drive mode (inversion). The multilevel converters require balancing the voltage across the series connected dc bus capacitors. Capacitors tend to over charge or completely discharge, at which condition the multilevel converter reverts to a three level converter unless an explicit control is devised to balance the capacitor charge. The voltage balancing techniques must be applied to the capacitor during the operations of the rectifier and the inverter. Thus, the real power flow into a capacitor must be the same as the real power flow out of the capacitor, and the net charge on the capacitor over one cycle remains the same.

58

PROPOSED NEW TOPOLOGY________________

4.1 INTRODUCTION
Multilevel converters offer high power capability, associated with lower output harmonics and lower commutation losses. Their main disadvantage is their complexity, requiring a great number of power devices and passive components. The different topologies presented in the literature as multilevel converters show a number of characteristics in common, giving them some clear advantages over bilevel converters, such as:

reduction in the commutation frequency applied to the power components;

reduction in the voltages applied to the main power switches, enabling operation at higher load voltages;

transient voltages automatically limited. The main disadvantage associated with the multilevel configurations is their circuit complexity, requiring a high number of power switches that must be commutated in a precisely determined sequence by a dedicated (and complex) modulator circuit; they also require a great number of auxiliary dc

59

levels, provided either by independent supplies or, more commonly, by a cumbersome array of capacitive voltage dividers. In this case, ensuring that the dc voltages are kept in equilibrium is another factor that increases the complexity of the modulator circuit. In the past, these disadvantages were almost overwhelming; due to the cost differences they produced between multilevel and standard configurations. Multilevel converters were used only in some high power applications such as high power motor drivers in marine, mining, or chemical industries applications, high power transmission, power line conditioners, etc. In all these applications their advantages compensate the cost differential. The continuing development of high power high switch frequency devices such as insulated-gate bipolar transistors (IGBTs) working at 3.3, 4.5, and 6.5 kV, and insulated-gate commutated thyristors (IGCT) working at 4.5 or 6 kV has improved overall converter performance, renewing the interest in multilevel topologies, that may be able to compete in the market with the standard two-level pulsewidth modulation (PWM) converters at lower power ranges. Initially, the main interest was concentrated in three-level configurations, but recently four- and five-level converters have also been reported. Even taking into account the

60

technological tendency to lower the prize at which multilevel converters can compete with standard configurations, the prize difference will remain unless the complexity issue is solved. As a contribution to solve this problem (cumbersome power stages and complex firing control circuits), this work proposes a new converter topology, presented as a block diagram in Fig.4.1. This topology includes an H-bridge stage with an auxiliary bidirectional switch, drastically reducing the power circuit complexity. The new converter topology used in the power stage offers an important improvement in terms of lower component count and reduced layout complexity when compared with the five-level converters presented in the literature. The new topology achieves almost a 40% reduction in the number of main power switches required and uses no more diodes or capacitors that the second best topology, the asymmetric cascade configuration.

61

Fig.4.1. New topology block diagram. The new topology is a single phase configuration that can be used in three phase applications where an open delta primary is acceptable.

4.2 PROPOSED TOPOLOGY

4.2.1 POWER STAGE A. Circuit Configuration Fig. 4.2 shows the complete power circuit used in the fivelevel inverter. The H-bridge is formed by the four main power devices, Disp1 to Disp4. A capacitor voltage divider, formed by C1 and C2 provides a half supply voltage point, node A in Fig. 4.2. The auxiliary switch, formed by the controlled switch Disp5 and the four diodes, D5 to D8, connects the center point of the left hand half-bridge to node A. B. Stage Advantages To probe the reduction in component numbers achieved by this new configuration, Table 4.1 presents the number of components required to implement a five-level inverter using the new topology and three previously defined ones: the two that can be considered as the standard multilevel stages, the diode clamped and the capacitor clamped

62

configurations, and a new and highly improved multilevel stage, the asymmetric cascade configuration. TABLE 4.1

Moreover, the voltage stress and average current in the switches from each topology were calculated in order to compare the power managed by the power switches in each configuration. A resistive load and the same output waveform were considered in all the cases. In order to compare the results, the voltage and current magnitude in the power switches were normalized to
63

the maximum voltage and current in the converter output. This allows to compare different topologies with different dc bus voltages. The results were as follows. 1) Main power switches: The new topology achieves a 37.5% reduction in the number of main power switches required, using only five controlled power switches instead of the eight required in any of the other three configurations. The auxiliary switch voltage and current ratings are lower than the ones required by the main controlled switches. 2) Auxiliary devices (diodes and capacitors):

The new configuration reduces the number of diodes by 60% (eight instead of 20) and the number of capacitors by 50% (two instead of four) when compared with the diode clamped configuration.

The new configuration reduces the number of capacitors by 80% (two instead of 10) when compared with the capacitor clamped configuration.

The new configuration uses no more diodes or capacitors that the second best topology in the table, the asymmetric cascade configuration.

64

Additionally, since the two capacitors are connected in parallel with the main dc power supply, no significant capacitor voltage swing is produced during normal operation, avoiding a problem that can limit operating range in some other multilevel configurations. C. Power Stage Operation The required five voltage output levels (Vs, Vs/2, 0, -Vs/2, -Vs) are generated as follows: 1) Maximum positive output, Vs : Disp1 is ON, connecting the load positive terminal to Vs, and Disp4 is ON, connecting the load negative terminal to ground. All other controlled switches are OFF; the voltage applied to the load terminals is Vs.

Fig.4.3 shows the current paths that are active at this stage. 2) Half-level positive output, Vs/2: The auxiliary switch, Disp5 is ON, connecting the load positive terminal to point A, through diodes D5 and D8,

65

and Disp4 is ON, connecting the load negative terminal to ground. All other controlled switches are OFF; the voltage applied to the load terminals is Vs/2.

Fig.4.4 shows the current paths that are active at this stage. 3) Zero output: The two main switches Disp3 and Disp4 are ON, shortcircuiting the load. All other controlled switches are OFF; the voltage applied to the load terminals is zero.

Fig.4.5 shows the current paths that are active at this stage.

66

4) Half-level negative output, -Vs/2: The auxiliary switch, Disp5 is ON, connecting the load positive terminal to point A, through diodes D6 and D7, and Disp2 is ON, connecting the load negative terminal to Vs. All other controlled switches are OFF; the voltage applied to the load terminals is -Vs/2.

Fig.4.6 shows the current paths that are active at this stage. 5) Maximum negative output: Disp2 is ON, connecting the load negative terminal to Vs, and Disp3 is ON, connecting the load positive terminal to ground. All other controlled switches are OFF; the voltage applied to the load terminals is -Vs.

67

Fig.4.7 shows the current paths that are active at this stage. Table 4.2 lists the switching combinations that generate the required five output levels (Vs, Vs/2, 0, -Vs/2, -Vs). In this configuration the two capacitors in the capacitive voltage divider are connected directly across the dc bus, and since all switching combinations are activated in an output cycle, the dynamic voltage balance between the two capacitors is automatically restored.

68

SIMULATION RESULTS______________________

The conventional Flying Capacitor Multilevel inverter is implemented in MATLAB as a simulink model. The inverter is constructed in both single phase and three phase configurations to get 4, 5, and 6 leveled output waveforms. The below figures numbered 5.1 to 5.18

69

show the simulink models, the gating signals and the output waveforms of the Flying Capacitor Multilevel inverter. Flying Capacitor 3-level multilevel inverter: Single Phase Configuration:-

Scope1

Out1 Out2 g C

Out1 Out2 g

Ga

Sa1
m E

Da1

Ga1

Sa3
m E

Da3 Ca3

+ v -

Vo1 Scope

Sa2
m E

Da2

Sa4
m E

Da4

Ca1 RL
Out1 g C Out1 g

Ca2

Vdc

S'a2
m E Out2

D'a2
Out2

S'a4
m

D'a4
E C

G'a

G'a1

S'a1
m E

D'a1

S'a3
m E

D'a3 Ca4

Fig 5.1 Circuit Diagram

70

Fig 5.2 Gating Signals.

Fig 5.3 Output Voltage Waveform.

71

Three Phase Configuration:-

Out1 Out1 Out2 g C g C Out1 C Out2

Ga Sa1

Da1
m E

Gb

Sa5
m E

Da5

Out2

Gc Sa9
m E

Da9

Ca4

Scope1 Scope

+ v -

+ v -

Va

Va1

+ v -

Sa2 Va2
m E

Da2

Sa6
m E

Da6

Sa10
m E

Da10 Vdc

Ca1 RLa
Out1 Out1 g C g Out2 C Out2

Ca2
Out1 g Out2 C

Ca3

Sa3
m E

Da3

G'a1Sa7
m E

Da7

G'a2 Sa11
m E

Da11

G'a RLa1

RLa2

Sa4
m E

Da4

Sa8
m E

Da8

Sa12
m E

Da12 Ca5

Fig 5.4 Circuit Diagram.

Fig 5.5 Gating Signals for the upper switches of phases a and b.

72

Fig 5.6 Output Voltage Waveform (Phase Voltages) Flying Capacitor 4-level Multilevel Inverter: Single Phase Configuration:O u t1 O u t2 O u t3 g C O u t1 O u t2

Ga Sa1

Vdc Da 7

Da 1
m E

Sb 1
m

Gb Cb 4

O u t3

Sa 2

Da 2

Sb2 Ca 2

Da 8

Cb 2

V d c1

Vo
g C

Cb 5

+ v -

Vo 1 Sa3

Da 3
m E

S b3
m E

Da 9

Cb 1 RL
g

Ca 1
Out3 Out2 Out1 g C

V d c2

G 'a

Out3 Out2 Out1

G 'b

S 'a 3

Da 4

S 'b 3

Da 1 0 Cb6

S 'a 2

Da 5

S 'b 2 Ca 3

Da 1 1

Cb 3

Fig. 5.7 Circuit Diagram

73

S 'a 1

Da 6

S 'b 1

Da 1 2

Fig 5.8 Gating Signals.

Fig 5.9 Output voltage Waveform

74

Three Phase Configuration:Out1 Out2 Out3 m g m g E C m g E C

IGBT

Diode

Gb

IGBT6

Diode6 Scope2

Gb1

IGBT14

E C

Ga

Out1 Out2 Out3

Out1 Out2 Out3

Diode14

Ca10

mg

m g

m g

EC

E C

IGBT1

Diode1

IGBT7

Diode7

IGBT15

E C

Ca2

Ca5

Diode15 Ca8 Vdc2

m g

m g

m g

E C

IGBT8

Diode8

IGBT16

E C

IGBT2

E C

Diode2

Diode16

Ca11 Vdc1

Ca1 Ca4
+ v Out1 Out2 Out3 Out1 Out2 Out3 m g E C m g Out1 Out2 Out3

Ca7

m g

Scope1 G'a Va1

+ v -

IGBT9

E C

IGBT3

Di ode3

G'b

Diode9

G'c

IGBT17

E C

Ra1

Diode17 Vdc Ca12

mg

mg

Va2

IGBT4

EC

Di ode4
m g

IGBT12 IGBT10
E C

EC

Ca3 Diode10 Ca6

Diode12

Ca9

m g

m g

IGBT5
+ v -

E C

IGBT13 Diode5
m g

E C

Diode13

IGBT11

E C

Diode11

Ra3

Scope3

Va3

Fig. 5.10 Circuit Diagram.

Fig 5.11 Gating Signals for the upper switches of phases a and b.

75

Fig 5.12 Output Voltage Waveform (Phase Voltages).

76

Flying Capacitor 5 level Multilevel Inverter: Single Phase Configuration:O u t 1 O u t 2 C O u t 4 O u t 3 O u t 1

S c o p e 1 D a 1

O u t 2 O u t 3 O u t 4

G a

G b

V a 6
m

S a 1

S a 9

D a 9

V d c 1 D a 1 0 V b 4

S c o p e

S a 3

D a 3

V a 2

S a 2

D a 2

S a 1 0

S a 1 1

D a 1 1

V b 2

V d c 2

+ v -

V o 1 S a 4

D a 4

S a 1 2

D a 1 2

V a 1 R L
C

V a 5
C

V b 1

V b 5

G ' b
O u t 1 O u t 2 O u t 3 O u t 4

O u t 1 O u t 2 O u t 3 O u t 4

G ' a
C C g g

S a 5

D a 5

S a 1 3

V d c 3

D a 1 3

V b 3 D a 1 4

V d c 4

V a 4

S a 7

D a 7

S a 1 5

S a 6

D a 6

V a 3

S a 1 4

D a 1 5 V b 6

Fig 5.13 Circuit Diagram.

Fig 5.14 Output Voltage Waveform.

S a 8

D a 8

S a 1 6

D a 1 6

77

Fig 5.15 Gating Signals. Three Phase Configuration:O ut1 g C O ut1 g O ut2 O ut3 O ut4 m C O ut2 O ut3 O ut4 O ut1 g O ut3 C O ut2

IG T8 B
m E

D iode8

IG BT
E

D iode

BT22 O ut4 IG
m E

D iode22 Va19

G b

G c

G a

IG T9 B IG BT1
m E

D iode9
m E

D iode1

C a12

IG BT23
m E

D iode23

C a4

C a17

Va20

IG BT10 IG BT2
m E

D iode10
m E

D iode2 C a2

IG BT16 C a11
m E

D iode16 C a16

Va21
g C g g C C

IG BT11 IG BT3
m E

D iode11
m E

D iode3

IG BT17
m E

D iode17

C a7 C a1 C a5
O ut1 g C O ut2 g C O ut3 O ut4

C a8

C a15
O ut1 g O ut2 C

C a18

IG BT12
m E

D iode12

v -

R La

G 'a Scope1
g C

G 'c

Va

C a9 C a3
g g C C

IGt1 O BT4 u O t2 u O t3 u O t4 u

D iode4

O ut3 O ut4

IG BT18

D iode18

Va22

G 'b

C a14

IG BT13
m E v

D iode13

IG BT5
m E

D iode5

IG BT19
m E

D iode19

R La1
-

Va1

Scope
g C g g C C

IG BT14 IG BT6
m + E

D iode14
m E

D iode6 C a6

IG BT20 C a10
m E

D iode20 C a13

R La2
-

Va2 IG BT7

IG BT15 D iode7
m E m E

D iode15

IG BT21
m E

D iode21

Fig. 5.16 Circuit Diagram.

78

Fig 5.17 Gating Signals for the upper switches of the phases a and b.

79

Fig 5.18 Output Voltage Waveform (Phase Voltages) Flying Capacitor 6 level Multilevel Inverter: Single Phase Configuration:O t1 u O t2 u O t3 u O t4 u O t5 u C g

Vc d
Ot1 u Ot2 u Ot3 u Ot4 u Ot5 u

G a S1 a

D1 a
m E

G b

S1 a1
m E

D1 a1

C2 a1 D1 a3 C1 a8

S2 a
m E

D2 a

C7 a

S1 a3
m E C

C4 a S3 a
m E

C1 a5 S1 a4
m E

D3 a

D1 a4

So e cp S4 a

C2 a D4 a
m E

C8 a

C1 a3 S1 a5
m E

C2 a2 C1 a9

D1 a5

+ v -

V 1a oS 5
m E

D5 a

S1 a6
m E

D1 a6

C1 a R L
C g O t1 u O t2 u O t3 u O t4 u O t5 u

C1 a1 C5 a
C g

C1 a6 C2 a3 D1 a7
m E C

S6 a
m E

D6 a

G 'a

O t1 u O t2 u O t3 u O t4 u O t5 u

S1 a7

G 'b

S7 a
m E

D7 a C3 a C9 a

S1 a8
m E

D1 a8 C1 a4 C2 a0 C2 a5

S8 a
m E

D8 a C6 a

S1 a9
m E

D1 a9 C1 a7

C2 a4 D2 a0 C1 a2

S9 a
m E

D9 a

C1 a0

S2 a0
m E C

S1 a0
m E

D1 a0

S1 a2
m E

D1 a2

Fig. 5.19 Circuit Diagram.

80

Fig 5.20 Gating Signals.

Fig 5.21 Output Voltage Waveform.

81

Three Phase Configuration:Out1 Out2 Out3 Out4 Out5 g C Out1 Out2 Out3 Out4 Out5 IGBT10 Out1 Out2 Out3 Out4 Out5 IGBT20

Ga

IGBT
m E

Diode

Diode10

Diode20

Gb

Gc

Ca31

DC Voltage Source

IGBT1
m E

Diode1

Ca10

IGBT11
m E

Diode11

Ca12

IGBT21
m E

Diode21

Ca22

IGBT2
m E

Diode2

Ca4

IGBT12
m E

Diode12

Ca15

IGBT22
m E

Diode22

Ca25

Ca32
g g g

IGBT3
m E

Diode3

Ca2 Ca9

IGBT13
m E

Diode13

Ca13 Ca20

IGBT23
m E

Diode23

Ca23 Ca30

IGBT4
m E

Diode4

IGBT14
m E

Diode14

IGBT24
m E

Diode24 Ca33

Ca1 Ca5
Out1 Out2 Out3 Out4 Out5 Out1 Out2 Out3 Out4 Out5 g g

Ca11 Ca16
Out1 Out2 Out3 Out4 Out5 g

Ca21 Ca26

RLa RLa1 RLa2

+ v -

IGBT5
m E

Diode5

IGBT15
m E

Diode15

IGBT25
m E

Diode25

G'a
+ v g

G'a1

G'a2 Ca34
g g

IGBT6
m E + v -

Diode6 Ca3 Ca8

IGBT16
m E

Diode16 Ca14 Ca19

IGBT26
m E

Diode26 Ca24 Ca29

Scope1

IGBT7
m E

Diode7 Ca6

IGBT17
m E

Diode17 Ca17

IGBT27
m E

Diode27 Ca27

Scope2

IGBT8
m E

Diode8 Ca7

IGBT18
m E

Diode18 Ca18

IGBT28
m E

Diode28 Ca28

Ca35
g g g

IGBT9
m E

Diode9

IGBT19
m E

Diode19

IGBT29
m E

Diode29

Fig. 5.22 Circuit Diagram.

Fig 5.23 Gating Signals for the upper switches of the phases a and b.
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Fig.5.24 Output Voltage Waveform (Phase Voltages). The new topology five-level inverter was also implemented in MATLAB as simulink model. The simulink model constructed in MATLAB, the gating signals and the output waveform for

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both single phase and three phase configurations are presented in the figures numbered from Fig 5.25 to 5.32

Fig 5.25 Circuit Diagram of the Propoed Topology.

The gate signals applied to the IGBTs are shown in Fig.5.26. Fig 5.27 shows the waveform of the PWM signals generate by comparing the gate signals with triangular wave of frequency 10KHz. Fig. 5.28 presents the output voltage waveform showing the desired five voltage levels.

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Fig 5.26 The fundamental output frequency is 50 Hz and converter switching frequency is 10 kHz, and the five output voltage levels are Vs = 120V, Vs/2 = 60V, 0V, -Vs/2= -60V, -Vs = -120V. The load current waveform is presented Fig. 5.29.

Fig 5.27
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Fig 5.28

Fig 5.29 Three phase configuration of the proposed topology: A three phase inverter is implemented using the single phase configuration of the proposed circuit. Fig 5.30 presents the three phase inverter implemented in MATLAB as a simulink model. Three phase series RL load is connected and the three phase output voltage is demultiplexed and observed. The gating signals of the three phases differ by 120 degrees with respect to each other. Fig 5.31 shows the gating signal of the first IGBT of

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the three phases of the inverter. The three signals have phase shift of 120 degrees with respect to each other. Fig 5.32 presents the waveform of the three phase output of the inverter.

Fig .5.30

Fig 5.31
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Fig 5.32

The outputs of the single phase Flying Capacitor Multilevel Inverter for various levels and the Proposed topology are analyzed for harmonic components using the fourier block in simulink. The fundamental, 3rd, 5th, 7th harmonic components of the inverters are presented in the below figures. The figures present the results obtained without using PWM technique and using PWM technique.

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Without PWM technique: Fundamental, 3rd, 5th, 7th harmonic components: 3 level flying capacitor multilevel inverter.

Fig 5.33. 4 level flying capacitor multilevel inverter.

Fig 5.34.
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5 level flying capacitor multilevel inverter.

Fig 5.35. 6 level flying capacitor multilevel inverter.

Fig 5.36.

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The Proposed topology.

Fig 5.37. With PWM technique: Fundamental, 3rd, 5th, 7th harmonic components: 3 level flying capacitor multilevel inverter.

Fig 5.38.
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4 level flying capacitor multilevel inverter.

Fig 5.39. 5 level flying capacitor multilevel inverter.

Fig 5.40

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6 level flying capacitor multilevel inverter.

Fig 5.41 The Proposed topology.

Fig 5.42

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The Flying Capacitor 3 level multilevel inverter has the same output as the single phase configuration of the proposed topology. This is observed from the figs 5.3 and 5.28. To get the same output while the former has used 8 switching devices, the proposed topology has used only 5 switching devices. In order to increase the number of levels in the output voltage waveform using the new topology, it is suggested to add one more capacitor in voltage divider circuit and one auxiliary switch to the circuit. But a conventional topology requires 4 switching devices in extra to increase the number of levels by 1.

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CONCLUSION_____________________________

The multilevel inverters have drawn tremendous interest in the power industry. They present a new set of features that are well suited for use in reactive power compensation. It may be easier to produce a high power, high voltage inverter with the multilevel structure because of the way in which device voltage stresses are controlled in the structure. Increasing the number of voltage levels in the inverter without requiring higher ratings on individual devices can increase the power rating. The unique structure of multilevel voltage source inverters allows them to reach high voltages with low harmonics without the use of transformers or series-connected synchronized, switching devices. As the number of voltage levels increases, the harmonic content of the output voltage waveform decreases significantly. The main disadvantage associated with the multilevel configurations is their circuit complexity, requiring a high number of power switches that must be commutated in a precisely determined sequence by a dedicated (and complex) modulator circuit; they also require a great number of auxiliary dc levels, provided either by independent supplies or, more commonly, by a cumbersome array of capacitive voltage dividers.
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In this case, ensuring that the dc voltages are kept in equilibrium is another factor that increases the complexity of the modulator circuit. As a contribution to solve this problem (cumbersome power stages and complex firing control circuits), this work proposes a new converter topology. This topology includes an H-bridge stage with an auxiliary bidirectional switch, drastically reducing the power circuit complexity. The new converter topology used in the power stage offers an important improvement in terms of lower component count and reduced layout complexity when compared with the five-level converters presented in the literature. The proposed topology is implemented in MATLAB as a simulink model and the output voltage and current waveforms are observed. A satisfactory operation of the circuit is observed. Three phase inverter is also implemented using single phase configuration whose phase voltages are observed connecting a three phase RL load. Flying capacitor multilevel inverter for various levels is also implemented and the output voltages of these inverters and that of the proposed inverter are analyzed for harmonics and the results are presented.

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BIBLIOGRAPHY___________________________

(1) A New Simplified Multilevel Inverter Topology for DCAC Conversion. By Gerardo Ceglia, Vctor Guzmn, Member, IEEE, Carlos Snchez, Fernando Ibez, Julio Walter, and Mara I. Gimnez, Member, IEEE, IEEE transactions on Power Electronics, Vol 21, No.5, September 2006. (2) J. Rodriguez, J.-S. Lai, and F. Z. Peng, Multi-level inverter: a survey of topologies, controls, and applications, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724738, Aug. 2002. (3) K. A. Corzine and X. Kou, Capacitor voltage balancing in full binary combination schema flying capacitor multilevel inverters, IEEE Power Electron. Lett., vol. 1, no. 1, pp. 25, Mar. 2003. (3) Power Electronics, Circuits, Devices and Applications by M.H.Rasheed. (4) Power Electronics, by Ned Mohan. (5) Basic Power Electronics by P.S.Bhimbra.

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