Lab manual-2010 Lab

Microprocessors & Microcontrollers

JYOTHI ENGINEERING COLLEGE

CHERUTHURUTHY, THRISSUR- 679 531

DEPARTMENT OF ELECTRONICS & COMMUNICATION

MICROPROCESSORS AND MICROCONTROLLERS

LAB MANUAL

PREPARED BY FACULTY ECE DEPT- 2010

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EXPERIMENT NO. : 1 FAMILIARIZATION OF MICRO 8086 LCD TRAINER KIT

AIM: To familiarize the 8086 trainer kit.

THEORY: 8086 is a 16-bit microprocessor. M-86/88 is a 8086 trainer kit with LCD display. The block diagram of Intel 8086 microprocessor is shown in fig. 1. Intel 8086 microprocessor is a 40-pin chip having Dual In-line Package (DIP) and its pin details is shown in fig. 2.

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Fig. 1: Block diagram of Intel 8086 microprocessor.

Fig. 2 : Pin diagram of Intel 8086 microprocessor.

The hardware and software facilities available on M 86/88 LCD Trainer Kit is explained below. SPECIFICATIONS HARDWARE SPECIFICATIONS:
1.

CPU PROCESSOR AND CLOCK FREQUENCY:

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Intel 8086/8088 CPU at 5/4.77 M Hz clock rate [optionally 8 M Hz]

2.

MEMORY: MONITOR EPROM EPROM EXPANSION SYSTEM RAM SYSTEM RAM EXPANSION INTERRUPT VECTORS STACK/ DATA AREA ( MONITOR, ASM/DSM, EDITOR) : : : F000:0000-3FFF for 16K F000:0000-1FFF for 64K 0000:1000-3FFF for 16K

: :

0000:1000-FFFF for 64K 0000:0000-03FF

0000:0400-0FFF

3.

PERIPHERALS: PARALLEL I/O SERIAL : : 48 I/O lines using two numbers of 8255 One number of RS232C- Serial Interface using 8251A USART

TIMER

3 channel 16 bit programmable timer 8253 Channel 0 used as baud rate generator for the serial port

4.

DISPLAY: 16X2 LCD DISPLAY [ with back light provision]

KEYBOARD: IBM PC- AT KEYBOARD

5. 6.

AUDIO CASSETTE INTERFACE with file management ON- BOARD BATTERY BACKUP: (Optional) On board battery backup facility is optionally provided for RAM (U2 & U4)

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POWER CONSUMPTION: + 5V : 1.5 Amps

7.

POWER SUPPLY SPECIFICATIONS: Mode 1 Mains Input Output : : : : SMPS-01 230V AC at 50 Hz 230V AC at 50Hz 1) +5V, 3A regulated 1. +12V, 250mA regulated 2. -12V, 250mA regulated 3. +30V, 250mA unregulated

8.

PHYSICAL CHARACTERISTICS: M- 86/88 LCD trainer PCB : 830 mm X 680 mm

9.

BUS EXPANSION : A new concept of VXT_Bus has been incorporated in M-86/88 LCD trainer which facilitates addition of extra hardware on to M- 86/88 LCD trainer. An unlimited number of Add- On Boards can be add to this Expansion Bus. All buffered address, data and control signals are brought out to this bus. The trainer provision for one VXT_Bus connectors.

SOFTWARE SPECIFICATIONS M-86/88 LCD trainer contains a high performance 16K monitor program. It is designed to respond to user input, RS232 communications, printer interface, parallel port interface and so on. The simple description of the command functions supported by this monitor is as follows:

COMMAND KEY FUNCTION MEMORY: RES

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The RES key allows the user to terminate any activity and return the M 86/88 LCD trainer to an initialized state. When pressed, the Vi Microsystems Pvt. Ltd message appears in the display for a few seconds and then the monitor will come to the command prompt TECH 8086. Only after this prompt is displayed, the commands will be accepted. INT

The INT key allows the user to interrupt any activity and return to the command prompt. HARDWARE DETAILS: The hardware description of M 86/88 LCD trainer provided in this chapter, highlights on all technical aspects including memory allocation, peripheral interfacing and power supply. FUNCTIONAL BLOCK DIAGRAM DESCRIPTION : The functional block diagram of M 86 / 88 LCD trainer is given in Fig. 3. Referring to that fig. the following explanations outlines the working of the trainer as a complete system. 1. INPUTS AND OUTPUTS OF THE CPU

The CPU gets the clock from the clock generator 8284 which uses a crystal at 15 or 14.318 M Hz and if it is an 8 M Hz trainer, 24 M Hz. The reset, interrupt lines and data lines are also inputs to the CPU. The CPU outputs comprise the address lines, data lines and control lines. 2. ADDRESS AND DATA BUS

The 16 bit 8086 bi-directional multiplexed address/data lines and the higher order 4 address lines are brought to latches and buffers. The address lines are latched using ALE and thus de-multiplexed from the data lines. The data lines are buffered through octal transceivers. The outputs of these ICs comprise the 20 bit address and 16/8 bit data bus as the case may be. The direction of data transfer is decided by the direction select input of the transceiver which is the DT/R* output of the CPU. 3. CONTRL BUS

The other bus is the control bus. The control signals required for proper operation of the system are the IOR* (I/O read), IOW* (I/O write), MR* (memory read) and MW*
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(memory write). The peripherals on the trainer are all I/O mapped and hence to input from or output to a peripheral, IOR* and IOW* are utilized. The memory read and memory write signals are used to output enable and an EPROM and RAM and write into a RAM respectively. These signals are generated from the IO/M* or M/IO* and WR*, RD* signals in minimum mode operation. 4. CHIP SELECT LOGIC

The selection of any peripheral or memory device requires a CS* (chip select) to enable that particular device. This requires address decoding, both memory and I/O where in decoding is separately achieved for EPROM, RAM and I/O devices. All the above signals address, data, control and chip selected are routed to all the peripherals and memory devices in the trainer. 5. KEYPAD AND DISPLAY

The block diagram shows a AT keyboard and LCD display. This is the unit with which the user communicates with the system 16 x 2 LCD module is used for displaying the command and data. IBM PC AT keyboard is used for entering data and control commands. 6. MEMORY

The block diagram shows two sockets for RAM both odd and even in the case of 8086 and 2 RAM sockets for contiguous locations in memory in the case of 8088. two sockets are provided for RAM expansion. The basic EPROM capacity available is 16KB arranged as odd and even bands in the case of 8086 and continuous locations in the case of 8088. the remaining EPROM capacity which is 16 KB can be availed as an optional facility. Each of the EPROM sockets can support either 8/16/32 KB memory devices and the RAM sockets 8/32 KB devices. 7. PERIPHERALS

The peripherals depicted in the block diagram include a) 8253 timer for baud clock generation b) 8251A USART for RS232C serial communication with associated drivers c) 8259 Programmable Interrupt Controller d) Audio Cassette Interface e) 8255 PPI for parallel TTL I/O System expansion is facilitated by the expansion slots available on the board. The data bus to the expansion slots is sent through a second layer of buffering, the buffers being
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degated for addresses of all devices present on board.

COMPONENT LAYOUT AND FUNCTION BLOCK DIAGRAM The Fig. 3 shows the functional block diagram for Micro-86 LCD trainer. The functional block diagram provides the complete system design in blocks. Have a careful look at the components layout for the exact location for the connectors, ICs and so on.

MEMORY CONFIGURATION This section explains the memory mapping facilities available on Micro-86/88 LCD trainer. Fig. 3 shows the complete memory allocation of Micro-86/88 LCD trainer. As shown in Fig. 3 the monitor reserves some portion of total memory capacity of CPU for its internal use and some for the user interface. The remaining portion is left for the user for their own development. This is indicated in the diagram as LEFT FOR USER DEVELOPMENT.

I/O ALLOCATION The complete I/O allocation table of the peripherals of M-86/88 LCD trainer is given in Fig 4. As seen from the table, the peripherals occupy I/O addresses from 0000 to 0060. the I/O addresses from 0081H to 00FFH are used for Add-On Boards. Apart from these reserved addresses, the rest are available to the users for their own development purpose. The following sections briefly describe the various peripherals and interfaces available on M-86/88 LCD trainer, emphasizing on the component used, its features, the connector termination and addresses. The Connector Pin Assignments can be had from the chapter CONNECTOR DETAILS.

TIMER INTERFACE ( U17) i. ii. Device used : Intel 8253 Programmable Interval Timer Key features of 8253

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a. 3 independent 16 bit counters. b. Programmable counter modes c. Input clock up to 2 MHz. d. Programmable count from 2 to 216 iii. iv. System mapping Channel 0 Input clock Output clock Used for Channel 1 & 2 Input clock : : : : : I/O mapped I/O 1.25/1.19 MHz or user input clock TTL levels and frequency less than 2 MHz 153 KHz if using system clock. Baud rate generation for serial port. TTL level clock of rate less than 2 MHz can be by the user. User determined. Available for user development. given

v.

vi.

Output clock : Used for : I/O mapped I/O Address

FUNCTION Control register Channel 0 Channel 1 Channel 2

ADDRESS 0016H 0010H 0012H 0014H

SOCKET NUMBER U17 U17 U17 U17

RS 232C SERIAL INTERFACE : (U27), (U26) i. Device used : Intel 8251A UNIVERSAL SYNCHRONOUS / ASYNCHRONOUS RECEIVER / TRANSMITTER (USART) ii. Key Features of 8251A a. Both synchronous and Asynchronous operations b. Full duplex, double buffered, transmitter and receiver. c. Parity, Overrun and framing error detection. iii. iv. v. System Mapping Input clock Baud Clock : : : : I/O mapped I/O 2.5 / 2.35 M Hz Baud Clock for the 8251A (U26) provided by channel 0 of 8253 (U17) 9600 baud rate, 8 data bits, 1 stop bit and no parity

vi. Initialized to

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vii. Driver Used viii. Connector termination

upon power ON. Max 232 (U27) for RS232C serial transmission and reception. : The RTS*, CTS*, RXD and TXD lines are the connector P3 and the connector is an AMPHENOL STANDARD 9 PIN D TYPE MALE. CONNECTOR NO. P3 P3 SOCKET NO. U26 U26

ix. I/O mapped I/O address: FUNCTION ADDRESS 8251A CONTROL / 000AH STATUS 8251A DATA 0008H

PARALLEL INTERFACE: (U31, U30) i. ii. Device Used : Intel 8255 Programmable Peripheral Interface

Key features of 8255 a. 24 programmable I/O lines configured as three 8- bit ports. b. Direct bit SET/RESET capability. c. Three modes of operation BASIC I/O STROBED I/O BIDIRCTIONAL BUS System mapping : I/O mapped I/O 8255 Port 1 (U30) 8255 Port 2 (U31) : : All 24 I/O lines are available to users All 24 I/O lines are available to users

iii. iv. v.

vi.. Connector termination

The 48 TTL I/O lines of both the 8255 ICs, U30 & U 31 are terminated at the two 26 pin IDC Connectors P7 (U30) and P8 (U30) respectively. All these terminations are as per the Dio bus std.

CONNECROR DETAILS: P1 Power connector. P2 Bus expansion connector

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P3 Serial port connector. P4 Ear input (audio). P5 MIC output (audio interface) P6 VXT Bus connector. P7 & P8 Parallel port connectors P9 IBM keyboard and LCD interface.

RESULT: 8086 LCD trainer kit is familiarized.

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