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TYPE IRFP450
s s s s s
V DSS 500 V
ID 14 A
TYPICAL RDS(on) = 0.33 EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED
3 2 1
DESCRIPTION This power MOSFET is designed using the companys consolidated strip layout-based MESH OVERLAY process. This technology matches and improves the performances compared with standard parts from various sources. APPLICATIONS s HIGH CURRENT SWITCHING s UNINTERRUPTIBLE POWER SUPPLY (UPS) s DC/DC COVERTERS FOR TELECOM, INDUSTRIAL, AND LIGHTING EQUIPMENT.
TO-247
Value 500 500 20 14 8.7 56 190 1.5 3.5 -65 to 150 150
(1) ISD 14 A, di/dt 130 A/s, VDD V(BR)DSS, Tj TJMAX
Uni t V V V A A A W W/ C V/ ns
o o o
C C
August 1998
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IRFP450
THERMAL DATA
R t hj-ca se
Rthj -amb
R thc- si nk Tl
Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For Soldering Purpose
AVALANCHE CHARACTERISTICS
Symb ol I AR E AS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 o C, I D = IAR , VDD = 50 V) Max Valu e 14 800 Unit A mJ
V DS = Max Rating Zero G ate Voltage Drain Current (VGS = 0) V DS = Max Rating Gate-body Leakage Current (V DS = 0) V GS = 20 V
T c = 125 C
ON ()
Symb ol V GS(th) R DS( on) ID(o n) Parameter Gate Threshold Voltage V DS = VGS Test Cond ition s ID = 250 A ID = 8.4 A 14 Min. 2 Typ . 3 0.33 Max. 4 0.4 Un it V A
DYNAMIC
Symb ol g fs () C iss C oss C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse T ransfer Capacitance Test Cond ition s V DS > I D(on) x R DS(on) max V DS = 25 V f = 1 MHz I D = 8.4 A VGS = 0 Min. 9.3 Typ . 13 2600 330 40 Max. Un it S pF pF pF
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ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symb ol t d(on) tr Qg Q gs Q gd Parameter Turn-on Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Cond ition s V DD = 250 V I D = 7A VGS = 10 V R G = 4.7 (see test circuit, figure 1) V DD = 400 V I D = 14A V GS = 10 V Min. Typ . 24 14 75 13.5 27 Max. Un it ns ns nC nC nC
SWITCHING OFF
Symb ol t r(Vof f) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Cond ition s V DD = 400 V I D = 14 A R G = 4.7 V GS = 10 V (see test circuit, figure 3) Min. Typ . 15 25 35 Max. Un it ns ns ns
() Pulsed: Pulse duration = 300 s, duty cycle 1.5 % () Pulse width limited by safe operating area
Thermal Impedance
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Output Characteristics Transfer Characteristics
Transconductance
Capacitance Variations
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Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature
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Fig. 1: Unclamped Inductive Load Test Circuit Fig. 1: Unclamped Inductive Waveform
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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IRFP450
DIM.
P025P
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IRFP450
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1998 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. .
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