Code: 9A10504 B.

Tech III Year I Semester (R09) Regular & Supplementary Examinations, November 2012 LINEAR AND DIGITAL IC APPLICATIONS
(Common to E.Con.E, EIE & ECC)

Time: 3 hours

Max Marks: 70

(a) (b)

Answer any FIVE questions All questions carry equal marks ***** Draw the equivalent circuit of op-amp at both lower and higher frequency. When an 8 V peak to peak square wave of 3.6 MHz frequencies is the input to a voltage follower, the output is a triangular wave as shown in fig 1. What is the flow rate of op-amp: v0 2.5 V
O

t
0.277 s

2.5 V (c) Fig (1). In problem 1(b) What must the slow rate of the op-amp bein order to get the square wave output? Design an adder circuit using an op-amp to get the output expression as V 0 = -(0.1 V 1 + 10 V 2 + V 3 + 100 V 4 ). Where V 1 , V 2 , V 3 , and V 4 are the inputs. Draw and explain the operation of full wave rectifier using op-amp. Draw the pin configuration and interval diagram of 565. Explain any one application of 565. Draw and explain the operation of 2 input CMOS NAND gates. Compare all CMOS logic families. Compare all logic families. Draw and explain 2 input ECL NOR gate. Define the following VHDL forms: (i) Synthesis. (ii) Simulation. (iii) Functions. (iv) Procedure. Write VHDL syntax for data flow design elements. Design 12 -bit comparator using 74 X 85s. Write a VHDL code for 74 X 138. Explain edge triggered JKFF. Design mod 10 ripple counter and explain its operation with neat timing diagram. *****

(a) (b)

(a) (b) (a) (b) (a) (b) (a) (b)

(v) Package.

(a) (b) (a) (b)

Code: 9A10504 B.Tech III Year I Semester (R09) Regular & Supplementary Examinations, November 2012 LINEAR AND DIGITAL IC APPLICATIONS
(Common to E.Con.E, EIE & ECC)

Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** Explain DC and AC characteristics of op-amp. (a) (b)

Max Marks: 70

1 2

Find R 1 and R f in the lossy integrator so that the peak gain is 20 d B and the gain is 3 d B down form its peak when w = 10,000 rad/sec. Use a capacitance of 0.01 f. Design a square wave oscillator for f = 1 KHZ. The op= amp is a 741 with supply voltages 15 V. Explain block diagram of phase locked 100 P. Explain operation of square wave converter using 555 timers. Explain static electrical behavior of CMOS logic. Derive the expression for rise time and fall time in case of CMOS logic. Explain CMOS/TTL interfacing. Explain the operation of CMOS there state buffer. Write VHDL syntax for: (i) Entity. (ii) Library. (iii) Package. (iv) 100 p statement. (vi) Component instantiation. (vii) With select.

(a) (b) (a) (b) (a) (b)

(v) Case statement.

(a) (b) (a) (b)

Write behavioral VHDL code for a 74 X 280. Implement 5 to 32 decoder using 74 X 138s. Design an excess 3 sequence counter and explain its operation. Write VHDL code of edge triggered DFF. *****

Code: 9A10504 B.Tech III Year I Semester (R09) Regular & Supplementary Examinations, November 2012 LINEAR AND DIGITAL IC APPLICATIONS
(Common to E.Con.E, EIE & ECC)

Time: 3 hours

Max Marks: 70

Answer any FIVE questions All questions carry equal marks ***** Derive the expression for following terms in case of differential amplifier using transistors. (i) A c . (ii) A d . (iii) CMRR. (a) (b) Explain the operation of temperature compensated logarithmic amplifier. Explain operation monostable multivibrator using op-amp and derive expression for pulse duration. Design a square wave generator using 555 timer of frequency 1 KHZ and duty cycle of 75%. For voltage controlled oscillator derive the expression of K v . Explain static electrical behavior of CMOS logic with an ideal inputs. Define: (i) Fan-in. (ii) Fan-out. (iii) Noise margin. (iv) Propagation delay. Write logic levels of TTL, CMOS and ECL. Calculate DC noise margin for each logic family at both lower level and upper level. Draw and explain the operation of 2 input TTL NAND gate. Explain VHDL design flow. Write VHDL syntax for behavioral design elements. Implement 32 to 5 encoder using 74 X 148s. Explain the operation of 8 X 8 combinational multiplier. Write a VHDL code for edge triggered JKFF. Design 2 bit up/down counter and explain its working. *****

(a) (b) (a) (b) (a) (b)

(a) (b) (a) (b) (a) (b)

Code: 9A10504 B.Tech III Year I Semester (R09) Regular & Supplementary Examinations, November 2012 LINEAR AND DIGITAL IC APPLICATIONS
(Common to E.Con.E, EIE & ECC)

Time: 3 hours

Max Marks: 70

(a) (b) (c)

Answer any FIVE questions All questions carry equal marks ***** Briefly explain about IC packages. Explain ideal op-amp characteristics. A 741 IC op-amp is used as an investing amplifier with a gevin of 50. The voltage gain versus frequency curve of 741 is flat up to 20 KHZ. What maximum peak to peak input signal can be applied without distorting the output? In the circuit V to I converter with grounded load Vin= 5 V, R = 10 K and V1 = 1.5 V. Find (i)The load current. (ii) The output voltage V 0 . Assume that the op-amp initially nulled. Explain inverting comparator with zero reference voltage. Explain any two applications of astable multi using IC.555. Explain basic principle of phase locked loop. Implement given Boolean functions with CMOS logic: (i) AB+CD. (ii) (A+B). (C+D). Explain dynamic electrical behavior of CMOS logic. Compare all TTL families. Explain low voltage CMOS/TTL interfacing. Explain program structure of VHDL language. Write VHDL syntax for structural design elements. Draw and explain the operation of 4 bit ripple adder. Write behavioral code for a 74 X 148. Design mod 12 ripple counter and explain its operation with timing diagram. Convert JKFF to SRFF. *****

(a) (b)

(a) (b) (a) (b)

(a) (b) (a) (b) (a) (b) (a) (b)