C Mos - IC''s - Data - Book

DL131/D
Rev. 4, Mar-2000
ON Semiconductor
CMOS Logic Data
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further
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SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by
customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or
authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
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DL131/D
03/00
DL131
REV 4
CMOS Logic Data
ON Semiconductor
CMOS Logic Data
This book presents technical data for the broad line of CMOS logic integrated circuits and demonstrates ON Semiconductors continued commitment to MetalGate CMOS. Complete specifications are provided in the form of data sheets.
In addition, a Product Selector Guide and a Handling and Design Guidelines chapter have been included to familiarize
the user with these circuits.
DL131/D
Rev. 4, March2000
SCILLC, 2000
Previous Edition 1991
All Rights Reserved
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be
validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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Table of Contents
Page
Chapter 1 Master Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Alphanumeric Listing of All CMOS Part Numbers with Function and Page Number Information Provided
Chapter 2 Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CMOS Selection Guide Sorted by Product Function
Chapter 3 Reliability Audit Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Explanation of On Semiconductors Outgoing Product Performance Audit Program
Chapter 4 B and UB Series Family Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Explanation of Standardized Specifications for the Product Family
Chapter 5 CMOS Handling and Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Handling Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Protection Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Propagation Delay and Rise Time versus Series Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMOS Latch Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
24
25
26
27
28
29
29
Chapter 6 CMOS Logic Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

See the Master Index for Page Numbering Information
Chapter 7 CMOS Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Air Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optimizing the Long Term Reliability of Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
431
432
432
434
434
435
Chapter 8 Equivalent Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

Chapter 9 Packaging Information Including Surface Mounts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON Semiconductor Major Worldwide Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON Semiconductor Standard Document Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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439
441
447
448
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SCANSWITCH, SENSEFET, SLEEPMODE, SMALLBLOCK, SMARTDISCRETES, SMARTswitch, SUPERBRIDGES,
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UNIT/PAK, Uniwatt, WaveFET, ZSwitch and ZIP R TRIM are trademarks of Semiconductor Components Industries, LLC
(SCILLC).
HDTMOS and HVTMOS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
All other brand names and product names appearing in this publication are registered trademarks or trademarks of their
respective holders.
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CHAPTER 1
Master Index
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MASTER INDEX
Device
MC14001B
MC14001UB
MC14007UB
MC14008B
MC14011B
MC14011UB
MC14013B
MC14014B
MC14015B
MC14016B
MC14017B
MC14018B
MC14020B
MC14021B
MC14022B
MC14023B
MC14024B
MC14025B
MC14027B
MC14028B
MC14029B
MC14040B
MC14042B
MC14043B
MC14044B
MC14046B
MC14049B
MC14049UB
MC14050B
MC14051B
MC14052B
MC14053B
MC14060B
MC14066B
MC14067B
MC14069UB
MC14070B
MC14071B
MC14073B
MC14076B
MC14077B
Function
Page
Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Dual D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Dual 4Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Presettable DividebyN Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
14Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Triple 3Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Triple 3Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Dual JK FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
BCDtoDecimal/BinarytoOctal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Quad NOR RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Quad NAND RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
PhaseLocked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
8Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Dual 4Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Triple 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
14Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
16Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Quad 2Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Triple 3Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Quad DType Register with TriState Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
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Device
MC14081B
MC14082B
MC14093B
MC14094B
MC14099B
MC14106B
MC14174B
MC14175B
MC14490
MC14503B
MC14504B
MC14511B
MC14512B
MC14513B
MC14514B
MC14515B
MC14516B
MC14517B
MC14518B
MC14520B
MC14521B
MC14526B
MC14528B
MC14532B
MC14536B
MC14538B
MC14541B
MC14543B
MC14549B
MC14551B
MC14553B
MC14555B
MC14556B
MC14557B
MC14559B
MC14562B
MC14569B
MC14572UB
MC14584B
MC14585B
MC14598B
Function
Page
Quad 2Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Dual 4Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Quad 2Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
8Stage Shift/Store Register with TriState Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
8Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Hex D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Quad D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Hex 3State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
BCDto7Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
8Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
BCDto7Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . . . . . . . . . . . . 259
4Bit Transparent Latch/4to16 Line Decoder (High) . . . . . . . . . . . . . . . . . . . . . . . . . . 268
4Bit Transparent Latch/4to16 Line Decoder (Low) . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Dual 64Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
24Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Presettable 4Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
8Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
BCDto7Segment Latch/Decoder/Driver for Liquid Crystals . . . . . . . . . . . . . . . . . . . 354
Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Quad 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
3Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Dual Binary to 1of4 Decoder (Active High Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Dual Binary to 1of4 Decoder (Active Low Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
1to64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
128Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Programmable Dual 4Bit Binary/BCD Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
4Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
8Bit BusCompatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
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CHAPTER 2
Product Selection Guide
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CMOS Selection Guide by Function

Device
NAND Gates
MC14011B
MC14011UB
MC14093B
MC14023B
Function
Page

Triple 3Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
NOR Gates
MC14001B
MC14001UB
MC14025B

Triple 3Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AND Gates
MC14081B
MC14073B
MC14082B
Quad 2Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Triple 3Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Dual 4Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Complex Gates
MC14070B
MC14077B
MC14572UB
Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Inverters/Buffers/Level Translator
MC14007UB
MC14049B
MC14049UB
MC14050B
MC14069UB
MC14503B
MC14504B
MC14584B
Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Hex 3State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Decoders/Encoders
MC14028B
MC14511B
MC14513B
MC14543B
MC14514B
MC14515B
MC14532B
MC14555B
MC14556B
BCDtoDecimal/BinarytoOctal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCDto7Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCDto7Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . . . . . . . . . . . .
BCDto7Segment Latch/Decoder/Driver for Liquid Crystals . . . . . . . . . . . . . . . . . . .
4Bit Transparent Latch/4to16 Line Decoder (High) . . . . . . . . . . . . . . . . . . . . . . . . . .
4Bit Transparent Latch/4to16 Line Decoder (Low) . . . . . . . . . . . . . . . . . . . . . . . . . .
8Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual Binary to 1of4 Decoder (Active High Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual Binary to 1of4 Decoder (Active Low Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . .
114
246
259
354
268
268
320
383
383
Multiplexers/Demultiplexers/Bilateral Switches
MC14016B
MC14066B
MC14551B
MC14053B
MC14052B
MC14067B
MC14051B
MC14512B
Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Quad 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Triple 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Dual 4Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
16Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
8Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
8Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Schmitt Triggers
MC14093B
MC14106B
MC14584B

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Device
OR Gates
MC14071B
Function
Page
Quad 2Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FlipFlops/Latches
MC14042B
MC14043B
MC14044B
MC14076B
MC14175B
MC14013B
MC14027B
MC14174B
MC14099B
MC14598B
Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Quad NOR RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Quad NAND RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Quad DType Register with TriState Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Quad D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Dual D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Dual JK FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Hex D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
8Bit BusCompatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Shift Registers
MC14015B
MC14517B
MC14562B
MC14557B
MC14014B
MC14021B
MC14094B
MC14549B
MC14559B
Dual 4Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Dual 64Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
128Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
1to64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
8Stage Shift/Store Register with TriState Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Counters
MC14017B
MC14018B
MC14020B
MC14022B
MC14024B
MC14029B
MC14040B
MC14060B
MC14516B
MC14518B
MC14520B
MC14526B
MC14553B
MC14569B
Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Presettable DividebyN Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
14Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Presettable 4Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
3Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Programmable Dual 4Bit Binary/BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Oscillators/Timers
MC14521B
MC14536B
MC14541B
24Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Multivibrators
MC14528B
MC14538B
Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Adders/Comparators
MC14008B
MC14585B
4Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Other Complex Functions

MC14046B
MC14490
PhaseLocked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
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CHAPTER 3
Reliability Audit Program
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RAP"
Reliability Audit Program
For Logic Integrated Circuits
1.0 INTRODUCTION
The Reliability Audit Program developed in March 1977
is the ON Semiconductor internal reliability audit which is
designed to assess outgoing product performance under
accelerated stress conditions. Logic Reliability Engineering
has overall responsibility for RAP, including updating its
requirements, interpreting its results, administration at
offshore locations, and monthly reporting of results. These
reports are available at all sales offices. Also available is the
Reliability and Quality Handbook which contains data for

all ON Semiconductor devices (HBD851/D).
RAP is a system of environmental and electrical tests
performed periodically on randomly selected samples of
standard products. Each sample receives the tests specified
in section 2.0. Frequency of testing is specified per internal
document 12MRM15301A.
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2.0 RAP TEST FLOW

Pull 500* piece sample from lot following Group A
acceptance.
45*
340
100
INITIAL
SEAL**
OP LIFE
40 HOURS
PTHB
48 HRS
TEMP CYCLES
40 CYCLES
PTH***
48 HRS
INTERIM
ELECTRICAL
INTERIM
TEST
OP LIFE
210 HRS (ADDITIONAL)
ADD 460 CYCLES
INTERIM
ELECTRICAL
FINAL
INTERIM #
ELECTRICAL
INTERIM
TEST
ADD 500 CYCLES
FINAL
INTERIM*
TEST
PTH
48 HRS
(ADDITIONAL)
OP LIFE #
750 HRS
(ADDITIONAL)
TEMP CYCLES #
1000 CYCLES
(ADDITIONAL)
FINAL
ELECTRICAL
(48 HRS)
FINAL
ELECTRICAL
(96 HRS)
FINAL #
ELECTRICAL
(1000 HRS)
FINAL
ELECTRICAL
& SEAL**
(2000 CYCLES)
SCRAP
SCRAP
SCRAP
#One sample per month for FAST, LS, 10H, 10K, MG CMOS, and HSL CMOS.
* PTHB or PTH not required for hermetic products: reduce total sample size to 450 pcs.
** Seal (Fine & Gross Leak) required only for hermetic products.
*** PTH to be used when sockets for PTHB are not available.
3.0 TEST CONDITIONS AND COMMENTS

3. Sampling to include all package types routinely.
4. Device types sampled will be by generic type within each
logic I/C product family (CMOS, TTL, etc.) and will
include all assembly locations (Korea, Philippines,
Malaysia, etc.).
5. 16 hrs. PTHB is equivalent to approximately 800 hours
of 85C/85% RH THB for VCC 15 V.
6. Only moisture related failures (like corrosion) are criteria
for failure on PTHB test.
7. Special device specifications (48As) for logic products
will reference 12MRM15301A as source of generic data
for any customer required monthly audit reports.
PTHB 15 psig/121C/100% RH at rated VCC or VEE
to be performed on plastic encapsulated devices

only.
TEMP CYCLING MILSTD883, Method 1010,
Condition C, 65C/+ 150C.
OP LIFE MILSTD883, Method 1005, Condition C
(Power plus Reverse Bias), TA = 145C.
NOTES:
1. All standard 25C dc and functional parameters will be
measured Go/No/Go at each readout.
2. Any indicated failure is first verified and then submitted
to the Product Analysis Lab for detailed analysis.
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CHAPTER 4
B and UB Series Family Data
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B AND UB SERIES FAMILY DATA

Devices with specialized inputs, such as oscillator
inputs, have unique input specifications.
The CMOS Devices in this volume which have a B or UB

suffix meet the minimum values for the industry
standardized* family specification. These standardized
values are shown in the Maximum Ratings and Electrical
Characteristics Tables. In addition to a standard minimum
specification for characteristics the B/UB devices feature:
318 volt operational limits
Capable of driving two lowpower TTL loads or one
lowpower Schottky TTL load over the rated
temperature range
Direct Interface to HighSpeed CMOS
Maximum input current of 1 A at 15 volt power
supply over the temperature range
Parameters specified at 5.0, 10, and 15 volt supply
Noise margins: B Series
1.0 V min @ 5.0 V supply
2.0 V min @ 10 V supply
Input Voltage
The input voltage specification is interpreted as the
worstcase input voltage to produce an output level of 1 or
0. This 1 or 0 output level is defined as a deviation
from the supply (VDD) and ground (VSS) levels. For a 5.0 V
supply, this deviation is 0.5 V; for a 10 V supply, 1.0 V; and
for 15 V, 1.5 V. As an example, in a device operating at a 5.0
V supply, the device with the input starting at ground is
guaranteed to switch on or before 3.5 V and not to switch up
to 1.5 V. Switching and not switching are defined as within
0.5 V of the ideal output level for the example with a 5.0 V
supply. The actual switching level referred to the input is
between 1.5 V and 3.5 V.
Noise Margin
The values for input voltages and the defined output
deviations lead to the calculated noise margins. Noise
margin is defined as the difference between VIL or VIH and
Vout (output deviation). As an example, for a noninverting
buffer at VDD = 5.0 volts: VIL = 1.5 volts and Vout = 0.5
volts. Therefore, Noise Margin equals VIL Vout = 1.0 volt.
This figure is useful while cascading stages (See Figure 1).
With the input to the first stage at a worstcase voltage level
(VIL = 1.5 V), the output is guaranteed to be no greater than
0.5 volts with a 5.0 volt supply. Since the maximum
allowable logic 0 for the second stage is 1.5 volts, this 0.5
volt output provides a 1.0 volt margin for noise to the next
stage.
UB Series
0.5 V min @ 5.0 V supply
The industrystandardized maximum ratings are shown at
the bottom of this page. Limits for the static characteristics
are shown in two formats: Table 1 is in the industry format
and Table 2 is in the equivalent ON Semiconductor format.
The ON Semiconductor format is used throughout this data
book. Additional specification values are shown on the
individual data sheets.
Switching characteristics for the B and UB series devices
are specified under the following conditions:
Load Capacitance, CL, of 50 pF
Input Voltage equal to VSS VDD (RailtoRail
swing)
Input pulse rise and fall times of 20 ns
Propagation Delay times measured from 50% point of
input voltage to 50% point of output voltage
Three different supply voltages: 5, 10, and 15 V
Output Drive Current

Devices in the B Series are capable of sinking a minimum
of 0.36 mA over the temperature range with a 5.0 V supply.
This value guarantees that these CMOS devices will drive
one lowpower Schottky TTL input.
B Series vs UB CMOS
The primary difference between B series and UB series
devices is that UB series gates and inverters are constructed
with a single inverting stage between input and output. The
decreased gain caused by using a single stage results in less
noise immunity and a transfer characteristic that is less ideal.
The decreased gain is quite useful when CMOS Gates and
inverters are used in a Linear mode to form oscillators,
monostables, or amplifiers. The decreased gain results in
increased stability and a cleaner output waveform. In
addition to linear operation, the UB gates and inverters offer
an increase in speed, since only a single stage is involved.
The B and UB series, and devices with no suffix can be
used interchangeably in digital circuits that interface to other
CMOS devices, such as HighSpeed CMOS Logic.
Exceptions to the B and UB Series Family

Specification
There are a number of devices which have a B or UB suffix
whose inputs and/or outputs vary somewhat from the family
specification because of functional requirements. Some
categories of notable exceptions are:
Devices with specialized outputs on the chip, such as
NPN emitterfollower drivers or transmission gates,
do not meet output specifications.
* Specifications coordinated by EIA/JEDEC SolidState Products Council.
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19
MAXIMUM RATINGS* (Voltages Referenced to VSS)

Symbol
VDD
Vin, Vout
Parameters
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5
DC Supply Voltage
Input or Output Voltage (DC or Transient)
Input or Output Current (DC or Transient), per Pin
10
mA
PD
Power Dissipation, per Package
500
mW
Tstg
Storage Temperature
65 to + 150
_C
TL
Lead Temperature (8Second Soldering)
260
_C
Iin, lout
* Maximum Ratings are those values values beyond which damage to the device may occur.
Temperature Derating:
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C
Ceramic L Packages: 12 mW/_C From 100_C To 125_C
5.0 V
Vout = 0.5 V
VIL = 1.5 V
FIRST STAGE
(NONINVERTING BUFFER)
Vout
VIL = 1.5 V SECOND STAGE

(NONINVERTING BUFFER)
Figure 1.
Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications
ELECTRICAL CHARACTERISTICS
Limits
Parameter
IDD
Quiescent
Device Current
GATES
BUFFERS,
FLIPFLOPS
MSI
VOL
VOH
Temp
Range
VDD
(Vdc)
Mil
5
10
15
Comm
5
10
15
Mil
5
10
15
Comm
5
10
15
Mil
5
10
15
+ 25_C
TLOW*
Min
Conditions
Vin = VSS or VDD

All valid input
combinations
VIN = VSS or VDD

All valid input
combinations
VIN = VSS or VDD
Comm
5
10
15
All valid input

combinations
LowLevel
Output Voltage
All
5
10
15
VIN = VSS or VDD

|IO| < 1 A
HighLevel
Output Voltage
All
5
10
15
VIN = VSS or VDD

|IO| < 1 A
4.95
9.95
14.95
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Max
Min
Max
Units
0.25
0.5
1.0
0.25
0.5
1.0
7.5
15
30
Adc
1.0
2.0
4.0
1.0
2.0
4.0
7.5
15
30
Adc
1.0
2.0
4.0
1.0
2.0
4.0
30
60
120
Adc
4
8
16
4.0
8.0
16.0
30
60
120
Adc
5
10
20
5
10
20
150
300
600
Adc
20
40
80
20
40
80
150
300
600
Adc
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
4.95
9.95
14.95
Max
THIGH*
Min
4.95
9.95
14.95
Vdc
Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications (continued)
Limits
Parameter
Temp
Range
VDD
(Vdc)
TLOW*
Max
Units
Input
Low Voltage#
B Types
All
5
10
15
VO = 0.5V or 4.5V
VO = 1.0V or 9.0V
VO = 1.5V or 13.5V
|IO| < 1 A
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
Vdc
VIL
Input
Low Voltage#
UB Types
All
5
10
15
VO = 0.5V or 4.5V
VO = 1.0V or 9.0V
VO = 1.5V or 13.5V
|IO| < 1 A
1.0
2.0
2.5
1.0
2.0
2.5
1.0
2.0
2.5
VIH
Input
High Voltage#
B Types
All
5
10
15
VO = 0.5V or 4.5V
VO = 1.0V or 9.0V
VO = 1.5V or 13.5V
|IO| < 1 A
3.5
7.0
11.0
3.5
7.0
11.0
3.5
7.0
11.0
Vdc
VIH
Input
High Voltage#
UB Types
All
5
10
15
VO = 0.5V or 4.5V
VO = 1.0V or 9.0V
VO = 1.5V or 13.5V
|IO| < 1 A
4.0
8.0
12.5
4.0
8.0
12.5
4.0
8.0
12.5
Vdc
IOL
Output Low
(Sink) Current
Mil
VO = 0.4V,
VIN = 0 or 5V
VO = 0.5V,
VIN = 0 or 10V
VO = 1.5V,
VIN = 0 or 15V
0.64
0.51
0.36
1.6
1.3
0.9
4.2
3.4
2.4
0.52
0.44
0.36
1.3
1.1
0.9
3.6
3.0
2.4
0.25
0.2
0.14
0.62
0.5
0.35
1.8
1.5
1.1
0.2
0.16
0.12
0.5
0.4
0.3
1.4
1.2
1.0
15
Com
10
15
IOH
Output High
(Source) Current
Mil
10
15
Com
Min
VO = 0.4V,
VIN = 0 or 5V
VO = 0.5V,
VIN = 0 or 10V
VO = 1.5V,
VIN = 0 or 15V
VO = 4.6V,
VIN = 0 or 5V
VO = 9.5V,
VIN = 0 or 10V
VO = 13.5V,
VIN = 0 or 15V
15
VO = 4.6V,
VIN = 0 or 5V
VO = 9.5V,
VIN = 0 or 10V
VO = 13.5V
VIN = 0 or 15V
10
Max
Min
Max
THIGH*
VIL
10
Conditions
+ 25_C
Min
mAdc
mAdc
mAdc
mAdc
IIN
Input Current
Mil
Comm
15
15
VIN = 0 or 15V
VIN = 0 or 15V
0.1
0.3
0.1
0.3
1.0
1.0
Adc
Adc
Ioz
3State Output
Leakage Current
Mil
Comm
15
15
VIN = 0 or 15V
VIN = 0 or 15V
0.4
1.6
0.4
1.6
12
12
Adc
Adc
CIN
Input Capacitance
per unit load
All
Any Input
7.5
* TLOW = 55_C for Military temperature range device, 40C for Commercial temperature range device.
THIGH = + 125_C for Military temperature range device, + 85_C for Commercial temperature range device.
#Applies for Worst Case input combinations.
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pF
Table 2. ON Semiconductor Format for CMOS Industry B and UB Series Specifications
Characteristic
55_C
25_C
+ 125_C
VDD
Vdc
Min
Max
Min
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
3.5
7.0
11
5.0
10
15
1.0
2.0
2.5
1.0
2.0
2.5
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
4.0
8.0
12.5
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
1.7
0.36
0.9
2.4
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
0.7
0.14
0.35
1.1
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
Input Current
Iin
15
0.1
0.1
1.0
Input Capacitance (Vin = 0)
Cin
7.5
pF
Gate Quiescent Current

(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.25
0.5
1.0
7.5
15
30
Adc
FlipFlop and Buffer Quiescent Current

(Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
1.0
2.0
4.0
30
60
120
Adc
MSI Quiescent Current

(Per Package)
IDD
5.0
10
15
5.0
10
20
5.0
10
20
150
300
600
Adc
LSI Quiescent Current
IDD
Output Voltage
Vin = VDD or 0
Symbol
Vin = 0 or VDD
Input Voltage B Types

(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Input Voltage UB Types

(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
0 Level
1 Level
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Output Drive Current UB Gates

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Output Drive Current Other Devices

(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
VIL
Vdc
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current B Gates

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
mAdc
IOH
Source
Sink
IOL
mAdc
IOH
Source
Sink
IOL
mAdc
IOH
Source
Sink
See Individual Data Sheets.
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Adc
CHAPTER 5
CMOS Handling and Design Guidelines
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HANDLING AND DESIGN GUIDELINES

HANDLING PRECAUTIONS
All MOS devices have insulated gates that are subject to
voltage breakdown. The gate oxide for ON Semiconductor
CMOS devices is about 900 thick and breaks down at a
gatesource potential of about 100 volts. To guard against
such a breakdown from static discharge or other voltage
transients, the protection networks shown in Figures 1A and
1B are used on each input to the CMOS device.
Static damaged devices behave in various ways,
depending on the severity of the damage. The most severely
damaged inputs are the easiest to detect because the input
has been completely destroyed and is either shorted to VDD,
shorted to VSS, or opencircuited. The effect is that the
device no longer responds to signals present at the damaged
input. Less severe cases are more difficult to detect because
they show up as intermittent failures or as degraded
performance. Another effect of static damage is that the
inputs generally have increased leakage currents.
Although the input protection network does provide a
great deal of protection, CMOS devices are not immune to
large static voltage discharges that can be generated during
handling. For example, static voltages generated by a person
walking across a waxed floor have been measured in the
4 15 kV range (depending on humidity, surface conditions,
etc.). Therefore, the following precautions should be
observed:
1. Do not exceed the Maximum Ratings specified by the
data sheet.
2. All unused device inputs should be connected to VDD
or VSS.
3. All lowimpedance equipment (pulse generators,
etc.) should be connected to CMOS inputs only after
the device is powered up. Similarly, this type of
equipment should be disconnected before power is
turned off.
4. Circuit boards containing CMOS devices are merely
extensions of the devices, and the same handling
precautions apply. Contacting edge connectors wired
directly to device inputs can cause damage. Plastic
wrapping should be avoided. When external
connections to a PC board are connected to an input of
5.
6.
7.
8.
9.
10.
a CMOS device, a resistor should be used in series

with the input. This resistor helps limit accidental
damage if the PC board is removed and brought into
contact with static generating materials. The limiting
factor for the series resistor is the added delay. This is
caused by the time constant formed by the series
resistor and input capacitance. Note that the maximum
input rise and fall times should not be exceeded. In
Figure 2, two possible networks are shown using a
series resistor to reduce ESD (Electrostatic
Discharge) damage. For convenience, an equation for
added propagation delay and rise time effects due to
series resistance size is given.
All CMOS devices should be stored or transported in
materials that are antistatic. CMOS devices must not
be inserted into conventional plastic snow,
styrofoam, or plastic trays, but should be left in their
original container until ready for use.
All CMOS devices should be placed on a grounded
bench surface and operators should ground
themselves prior to handling devices, since a worker
can be statically charged with respect to the bench
surface. Wrist straps in contact with skin are strongly
recommended. See Figure 3 for an example of a
typical work station.
Nylon or other static generating materials should not
come in contact with CMOS devices.
If automatic handlers are being used, high levels of
static electricity may be generated by the movement
of the device, the belts, or the boards. Reduce static
buildup by using ionized air blowers or room
humidifiers. All parts of machines which come into
contact with the top, bottom, or sides of IC packages
must be grounded to metal or other conductive
material.
Cold chambers using CO2 for cooling should be
equipped with baffles, and the CMOS devices must be
contained on or in conductive material.
When leadstraightening or handsoldering is
necessary, provide ground straps for the apparatus
used and be sure that soldering ties are grounded.
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INPUT PROTECTION NETWORK

VDD
CMOS
INPUT
VDD
CMOS
INPUT
TO CIRCUIT
< 1500
VSS
300
VSS
Figure 1a. Input Protection Network

Double Diode
Figure 1b. Input Protection Network

Triple Diode
13. The use of static detection meters for production line

surveillance is highly recommended.
14. Equipment specifications should alert users to the
presence of CMOS devices and require
familiarization with this specification prior to
performing any kind of maintenance or replacement
of devices or modules.
15. Do not insert or remove CMOS devices from test
sockets with power applied. Check all power supplies
to be used for testing devices to be certain there are no
voltage transients present.
16. Double check test equipment setup for proper polarity
of VDD and VSS before conducting parametric or
functional testing.
17. Do not recycle shipping rails or trays. Repeated use
causes deterioration of their antistatic coating.
11. The following steps should be observed during wave

solder operations:
a. The solder pot and conductive conveyor system of
the wave soldering machine must be grounded to
an earth ground.
b. The loading and unloading work benches should
have conductive tops which are grounded to an
earth ground.
c. Operators must comply with precautions
previously explained.
d. Completed assemblies should be placed in
antistatic containers prior to being moved to
subsequent stations.
12. The following steps should be observed during
boardcleaning operations:
a. Vapor degreasers and baskets must be grounded to
an earth ground.
b. Brush or spray cleaning should not be used.
c. Assemblies should be placed into the vapor
degreaser immediately upon removal from the
antistatic container.
d. Cleaned assemblies should be placed in antistatic
containers immediately after removal from the
cleaning basket.
e. High velocity air movement or application of
solvents and coatings should be employed only
when assembled printed circuit boards are
grounded and a static eliminator is directed at the
board.
RECOMMENDED FOR READING:

Total Control of the Static in Your Business
Available by writing to:
3M Company
Static Control Systems
P.O. Box 2963
Austin, Texas 787692963
Or by Calling:
18003281368
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VDD
TO OFFBOARD
CONNECTION
R1
D1
CMOS
INPUT
OR
OUTPUT
TO OFFBOARD
CONNECTION
R2
CMOS
INPUT
OR
OUTPUT
D2
Advantage:
Disadvantage:
Advantage:
Requires minimal board area

R1 > R2 for the same level of
protection, therefore rise and fall
times, propagation delays, and output
drives are severely affected.
Disadvantage:
VSS
R2 < R1 for the same
level of protection.
Impact on ac and dc
characteristics is minimized
More board area, higher initial cost
Note: These networks are useful for protecting the following

A digital inputs and outputs
C 3state outputs
B analog inputs and outputs
D bidirectional (I/O) ports
PROPAGATION DELAY AND RISE TIME

vs. SERIES RESISTANCE
R [ t
C@k
where:
R = the maximum allowable series resistance in ohms
t = the maximum tolerable propagation delay or rise time in seconds
C = the board capacitance plus the driven devices
= input capacitance in farads
k = 0.7 for propagation delay calculations
k = 2.3 for rise time calculations
Figure 2. Networks for Minimizing ESD and Reducing

CMOS Latch Up Susceptibility
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2
5
NOTES: 1. 1/16 inch conductive sheet stock covering bench

top work area.
2. Ground strap.
3. Wrist strap in contact with skin.
4. Static neutralizer. (Ionized air blower directed at
work.) Primarily for use in areas where direct
grounding is impractical.
5. Room humidifier. Primarily for use in areas where
the relative humidity is less than 45%. Caution:
building heating and cooling systems usually dry
the air causing the relative humidity inside of
buildings to be less than outside humidity.
RESISTOR =
1 MEGAOHM
Figure 3. Typical Manufacturing Work Station
POWER SUPPLIES
the possibility of latchup related failures. This system

protection can be provided by the power supply filter and/or
voltage regulator.
CMOS devices can be used with battery or battery backup
systems. A few precautions should be taken when designing
batteryoperated systems:
1. The recommended power supply voltage should be
observed. For battery backup systems such as the one
in Figure 5, the battery voltage must be at least 3.7
Volts (3 Volts from the minimum power supply
voltage and 0.7 Volts to account for the voltage drop
across the series diode).
2. Inputs that might go above the battery backup voltage
should either use a series resistor to limit the input
current to less than 10 mA or use the MC14049UB or
MC14050B hightolow voltage translators.
3. Outputs that are subject to voltage levels above VDD
or below VSS should be protected with a series resistor
to limit the current to less than 10 mA or with
clamping diodes.
CMOS devices have low power requirements and the

ability to operate over a wide range of supply voltages.
These two characteristics allow CMOS designs to be
implemented using inexpensive, conventional power
supplies, instead of switching power supplies and power
supplies with cooling fans. In addition, batteries may be used
as either a primary power source or for emergency backup.
The absolute maximum power supply voltage for 14000
Series Metalgate CMOS is 18.0 Vdc. Figure 4 offers some
insight as to how this specification was derived. In the
figure, VS is the maximum power supply voltage and IS is
the sustaining current of the latchup mode. The value of VS
was chosen so that the secondary breakdown effect may be
avoided.
In an ideal system design, a power supply should be
designed to deliver only enough current to insure proper
operation of all devices. The obvious benefit of this type
design is cost savings; an added benefit is protection against
IDD
LATCH
UP MODE
SECONDARY
BREAKDOWN
LOW CURRENT
JUNCTION
AVALANCHE
IS
VS
VDD
VS = DATA SHEET MAXIMUM SUPPLY RATING
Figure 4. Secondary Breakdown Characteristics

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POWER SUPPLY
BATTERY BACKUP
RECHARGE
BATTERY BACKUP
SYSTEM
LINE POWER ONLY

SYSTEM
MC14049UB
MC14050B
CMOS
SYSTEM
CMOS
SYSTEM
MC14049UB
MC14050B
Figure 5. Battery Backup Interface
VDD = 5.0 Vdc
INPUTS
Vout , OUTPUT VOLTAGE (V)
All inputs, while in the recommended operating range

(VSS < Vin < VDD) can be modeled as shown in Figure 6. For
input voltages in this range, diodes D1 and D2 are modeled
as resistors, representing the reverse bias impedance of the
diodes. The maximum input current is worst case, 1 A,
when the inputs are at VDD or VSS, and VDD = 15.0 V. This
model does not apply to inputs with pullup or pulldown
resistors.
SINGLE INPUT NAND, AND

MULTIPLE INPUT NOR, OR
5.0
4.0
SINGLE INPUT NOR, OR

MULTIPLE INPUT NAND, AND
3.0
2.0
1.0
0
VDD
R1 = R2 = HIGH Z
R1
2.0
3.0
4.0
5.0
Vin, INPUT VOLTAGE (V)
Figure 7. Typical Transfer Characteristics

for Buffered Devices
7.5 pF
R2
Figure 6. Input Model for VSS
1.0
For these reasons, all unused inputs should be connected

either to VDD or VSS. For applications with inputs going to
edge connectors, a 100 kilohm resistor to VSS should be
used, as well as a series resistor for static protection and
current limiting (Figure 8). The 100 kilohm resistor will help
eliminate any static charges that might develop on the
printed circuit board. See Figure 2 for other possible
protection arrangements.
vV vV
in
DD
When left opencircuited, the inputs may selfbias at or

near the typical switchpoint, where both the Pchannel and
Nchannel transistors are conducting, causing excessive
current drain. Due to the high gain of the inverters (see
Figure 7), the device may also go into oscillation from any
noise in the system. Since CMOS devices dissipate the most
power during switching, this oscillation can cause very large
current drain and undesired switching.
FROM
EDGE
CONNECTOR
RS
CMOS
DEVICE
100 k
Figure 8. External Protection
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lout = 0 A. The output drives for all buffered CMOS devices

are such that 1 LSTTL load can be driven across the full
temperature range.
CMOS outputs are limited to externally forced output
voltages of VSS 0.5 V
Vout
VDD + 0.5 V. When
voltages are forced outside of this range, a silicon controlled
rectifier (SCR) formed by parasitic transistors can be
triggered, causing the device to latch up. For more
information on this, see the explanation of CMOS Latch Up
in this section.
The maximum rated output current for most outputs is
10 mA. The output shortcircuit currents of these devices
typically exceed these limits. Care must be taken not to
exceed the maximum ratings found on every data sheet.
For applications that require driving high capacitive loads
where fast propagation delays are needed (e.g., driving
power MOSFETs), two or more outputs on the same chip
may be externally paralleled.
For input voltages outside of the recommended operating

range, the CMOS input is modeled as in Figure 9. The
resistordiode protection network allows the user greater
freedom when designing a worst case system. The device
inputs are guaranteed to withstand voltages from VSS 0.5
V to VDD + 0.5 V and a maximum current of 10 mA. With
the above input ratings, most designs will require no special
terminations or design considerations.
D1
1.5 k
D2
7.5 pF
Figure 9. Input Model for Vin > VDD or Vin < VSS
CMOS LATCH UP
Latch up will not be a problem for most designs, but the
designer should be aware of it, what causes it, and how to
prevent it.
Figure 11 shows the crosssection of a typical CMOS
inverter and Figure 12 shows the parasitic bipolar devices.
The circuit formed by the parasitic transistors and resistors
is the basic configuration of a silicon controlled rectifier, or
SCR. In the latch up condition, transistors Q1 and Q2 are
turned ON, each providing the base current necessary for the
other to remain in saturation, thereby latching the devices in
the ON state. Unlike a conventional SCR, where the device
is turned ON by applying a voltage to the base of the NPN
transistor, the parasitic SCR is turned ON by applying a
voltage to the emitter of either transistor. The two emitters
that trigger the SCR are the same point, the CMOS output.
Therefore, to latch up the CMOS device, the output voltage
must be greater than VDD + 0.5 V or less than VSS 0.5 V
and have sufficient current to trigger the SCR. The latchup
mechanism is similar for the inputs.
Once a CMOS device is latched up, if the supply current
is not limited, the device will be destroyed. Ways to prevent
such occurrences are listed below:
1. Insure that inputs and outputs are limited to the
maximum rated values, as follows:
0.5 V Vin or Vout
VDD + 0.5 V (referenced to
VSS) |Iin or Iout| 10 mA (unless otherwise indicated
on the data sheet)
2. If voltage transients of sufficient energy to latch up the
device are expected on the inputs or outputs, external
protection diodes can be used to clamp the voltage.
Another method of protection is to use a series resistor
to limit the expected worst case current to the
maximum rating of 10 mA. (See Figure 2).
3. Sequence power supplies so that the inputs or outputs
of CMOS devices are not active before the supply pins
are powered up (e.g., recessed edge connectors and/or
Other specifications that should be noted are the

maximum input rise and fall times. Figure 10 shows the
oscillations that may result from exceeding the 15 s
maximum rise and fall time at VDD = 5.0 V, 5 s at 10 V, or
4 s at 15 V. As the voltage passes through the switching
threshold region with a slow rise time, any noise that is on
the input is amplified, and passed through to the output,
causing oscillations. The oscillation may have a low enough
frequency to cause succeeding stages to switch, giving
unexpected results. If input rise or fall times are expected to
exceed 15 s at 5.0 V, 5 s at 10 V, or 4 s at 15 V,
Schmitttrigger devices such as the MC14093B,
MC14584B, MC14106B, HC14, or HC132 are
recommended for squaringup these slow transitions.
VDD
Vin
VSS
VOH
Vout
VOL
Figure 10. Maximum Rise and Fall Time Violations
OUTPUTS
All CMOS BSeries outputs are buffered to insure
consistent output voltage and current performance. All
buffered outputs have guaranteed output voltages of VOL =
0.05 V and VOH = VDD 0.05 V for Vin = VDD or VSS and
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29
5. Limit the available power supply current to the

devices that are subject to latchup conditions. This
can be accomplished with the power supply filtering
network or with a currentlimiting regulator.
series resistors may be used in plugin board

applications).
4. Voltage regulating or filtering should be used in board
design and layout to insure that powersupply lines
are free of excessive noise.
PCHANNEL
NCHANNEL
INPUT
VDD
N+
PCHANNEL
OUTPUT
VDD
FIELD OXIDE
P+
P+
OUTPUT
VSS
NCHANNEL
OUTPUT
FIELD OXIDE
N SUBSTRATE
N+
N+
P+
FIELD OXIDE
P WELL
Figure 11. CMOS Wafer Cross Section
Q1
NCHANNEL OUTPUT
N+
VSS
N+
NSUBSTRATE RESISTANCE
N
N
P+
VSS
VDD
PWELL RESISTANCE
Q2
Figure 12. Latch Up Circuit Schematic
http://onsemi.com
30
P+
VDD
PCHANNEL OUTPUT
CHAPTER 6
CMOS Logic Data Sheets
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31
MC14001B Series
B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
http://onsemi.com
The B Series logic gates are constructed with P and N channel

enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
MARKING
DIAGRAMS
14
Supply Voltage Range = 3.0 Vdc to 18 Vdc

All Outputs Buffered
Capable of Driving Two Lowpower TTL Loads or One Lowpower
PDIP14
P SUFFIX
CASE 646
Schottky TTL Load Over the Rated Temperature Range.

Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
PinforPin Replacements for Corresponding CD4000 Series B
Suffix Devices
14
SOIC14
D SUFFIX
CASE 751A
VDD
Vin, Vout
Iin, Iout
PD
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5
Input or Output Current

(DC or Transient) per Pin
10
mA
Power Dissipation,
per Package (Note 2.)
500
mW
TA
Ambient Temperature Range
55 to +125
Tstg
Storage Temperature Range
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
14
TSSOP14
DT SUFFIX
CASE 948G
14
0XXB
ALYW
1
14
SOEIAJ14
F SUFFIX
CASE 965
MC140XXB
AWLYWW
1
XX
= Specific Device Code
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
DEVICE INFORMATION
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
140XXB
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)

Symbol
MC140XXBCP
AWLYYWW
Device
Description
MC14001B
Quad 2Input NOR Gate
MC14011B
Quad 2Input NAND Gate
MC14023B
Triple 3Input NAND Gate
MC14025B
Triple 3Input NOR Gate
MC14071B
Quad 2Input OR Gate
MC14073B
Triple 3Input AND Gate
MC14081B
Quad 2Input AND Gate
MC14082B
Dual 4Input AND Gate
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 39 of this data sheet.
Semiconductor Components Industries, LLC, 2000
March, 2000 Rev. 1
32
Publication Order Number:

MC14001B/D
MC14001B Series
LOGIC DIAGRAMS
NAND
OR
AND
MC14001B
MC14011B
MC14071B
Quad 2Input OR Gate
MC14081B
2 INPUT
NOR
1
2
1
2
1
2
1
2
5
6
5
6
5
6
5
6
8
9
10
8
9
10
8
9
10
8
9
10
12
13
11
12
13
11
12
13
11
12
13
11
3 INPUT
MC14025B
1
2
8
3
4
5
11
12
13
10
MC14023B
1
2
8
3
4
5
11
12
13
MC14073B
1
2
8
3
4
5
11
12
13
10
10
MC14082B
2
3
4
5
9
10
11
12
13
NC = 6, 8
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
PIN ASSIGNMENTS
MC14001B
MC14023B
MC14011B
MC14025B
IN 1A
14
VDD
IN 1A
14
VDD
IN 1A
14
VDD
IN 1A
14
VDD
IN 2A
13
IN 2D
IN 2A
13
IN 2D
IN 2A
13
IN 3C
IN 2A
13
IN 3C
OUTA
12
IN 1D
OUTA
12
IN 1D
IN 1B
12
IN 2C
IN 1B
12
IN 2C
OUTB
11
OUTD
OUTB
11
OUTD
IN 2B
11
IN 1C
IN 2B
11
IN 1C
IN 1B
10
OUTC
IN 1B
10
OUTC
IN 3B
10
OUTC
IN 3B
10
OUTC
IN 2B
IN 2C
IN 2B
IN 2C
OUTB
OUTA
OUTB
OUTA
VSS
IN 1C
VSS
IN 1C
VSS
IN 3A
VSS
IN 3A
MC14071B
Quad 2Input OR Gate
MC14073B
MC14081B
MC14082B
IN 1A
14
VDD
IN 1A
14
VDD
IN 1A
14
VDD
OUTA
14
VDD
IN 2A
13
IN 2D
IN 2A
13
IN 3C
IN 2A
13
IN 2D
IN 1A
13
OUTB
OUTA
12
IN 1D
IN 1B
12
IN 2C
OUTA
12
IN 1D
IN 2A
12
IN 4B
OUTB
11
OUTD
IN 2B
11
IN 1C
OUTB
11
OUTD
IN 3A
11
IN 3B
IN 1B
10
OUTC
IN 3B
10
OUTC
IN 1B
10
OUTC
IN 4A
10
IN 2B
IN 2B
IN 2C
OUTB
OUTA
IN 2B
IN 2C
NC
IN 1B
VSS
IN 1C
VSS
IN 3A
VSS
IN 1C
VSS
NC
NC = NO CONNECTION
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33
MC14001B Series
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Total Supply Current (4.) (5.)

(Dynamic plus Quiescent,
Per Gate, CL = 50 pF)
Sink
mAdc
IT = (0.3 A/kHz) f + IDD/N

Adc
3. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
4. The formulas given are for the typical characteristics only at 25_C.
5. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL 50) Vfk
where: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
per package.
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34
MC14001B Series
BSERIES GATE SWITCHING TIMES
SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)

Characteristic
Symbol
Output Rise Time, All BSeries Gates

tTLH = (1.35 ns/pF) CL + 33 ns
tTLH = (0.40 ns/PF) CL + 20 ns
tTLH
Output Fall Time, All BSeries Gates

tTHL = (1.35 ns/pF) CL + 33 ns
tTHL
Propagation Delay Time

MC14001B, MC14011B only
tPLH, tPHL = (0.90 ns/pF) CL + 80 ns
All Other 2, 3, and 4 Input Gates
8Input Gates (MC14068B, MC14078B)
VDD
Vdc
Min
Typ (7.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
tPLH, tPHL
ns
5.0
10
15
125
50
40
250
100
80
5.0
10
15
160
65
50
300
130
100
5.0
10
15
200
80
60
350
150
110
14
PULSE
GENERATOR
20 ns
VDD
20 ns
OUTPUT
0V
tPLH
tPHL
CL
VDD
90%
50%
10%
INPUT
INPUT
OUTPUT
INVERTING
VSS
tTHL
tPLH
OUTPUT
NONINVERTING
*All unused inputs of AND, NAND gates must be connected to VDD.

All unused inputs of OR, NOR gates must be connected to VSS.
tTLH
Figure 1. Switching Time Test Circuit and Waveforms
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35
VOH
90%
50%
10%
tTLH
tPHL
90%
50%
10%
tTHL
VOL
VOH
VOL
MC14001B Series
CIRCUIT SCHEMATIC
NOR, OR GATES
MC14001B, MC14071B
One of Four Gates Shown
MC14025B
One of Three Gates Shown
VDD
VDD
14
VDD
1, 3, 11
1, 6, 8, 13
*
2, 4, 12
2, 5, 9, 12
14
VDD
3, 4, 10, 11
*
VSS
VSS
9, 6, 10
VSS
VDD
*Inverter omitted in MC14001B

8, 5, 13
7
VSS
VSS
CIRCUIT SCHEMATIC
NAND, AND GATES
MC14023B, MC14073B
One of Three Gates Shown
MC14011B, MC14081B
One of Four Gates Shown
VDD
14
VDD
3, 4, 10, 11
2, 4, 12
1, 3, 11
14
2, 5, 9, 12
VDD
1, 6, 8, 13
VSS
7 VSS
VDD
9, 6, 10
8, 5, 13
7
VSS
VSS
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36
MC14001B Series
TYPICAL BSERIES GATE CHARACTERISTICS
NCHANNEL DRAIN CURRENT (SINK)
PCHANNEL DRAIN CURRENT (SOURCE)

10
5.0
ID , DRAIN CURRENT (mA)
9.0
4.0
TA = 55C
3.0
40C
+ 85C + 25C
2.0
+ 125C
1.0
8.0
TA = 55C
7.0
40C
6.0
5.0
+ 25C
+ 85C
4.0
+ 125C
3.0
2.0
1.0
1.0
2.0
3.0
4.0
VDS, DRAINTOSOURCE VOLTAGE (Vdc)
5.0
Figure 2. VGS = 5.0 Vdc

50
45
TA = 55C
16
14
40C
12
+ 25C
+ 85C
10
18
+ 125C
8.0
6.0
40
35
30
+ 85C
15
2.0
5.0
1.0
2.0 3.0 4.0 5.0

6.0
7.0 8.0
9.0
10
40C
+ 25C
20
10
TA = 55C
25
4.0
+ 125C
Figure 4. VGS = 10 Vdc

100
45
90
40
80
35
TA = 55C
30
40C
25
+ 25C
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10

50
+ 85C
20
+ 125C
15
10
5.0
0
5.0
Figure 3. VGS = 5.0 Vdc
20
1.0
2.0
3.0
4.0
70
60
TA = 55C
50
40C
+ 25C
40
+ 85C
30
+ 125C
20
10
2.0
4.0 6.0 8.0 10

12
14
16
18
20
2.0 4.0 6.0 8.0 10 12 14 16

These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.
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37
18 20
MC14001B Series
TYPICAL BSERIES GATE CHARACTERISTICS (contd)
V out , OUTPUT VOLTAGE (Vdc)
VOLTAGE TRANSFER CHARACTERISTICS

5.0
4.0

3.0
2.0
1.0
0
1.0
2.0

10
8.0

6.0
4.0
2.0
0
3.0
4.0
5.0
Vin, INPUT VOLTAGE (Vdc)
2.0
Figure 8. VDD = 5.0 Vdc
6.0
8.0
10
Figure 9. VDD = 10 Vdc
DC NOISE MARGIN
16
14
The DC noise margin is defined as the input voltage range

from an ideal 1 or 0 input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values VIL and VIH for the output(s) to
be at a fixed voltage VO are given in the Electrical
Characteristics table. VIL and VIH are presented graphically
in Figure 11.
Guaranteed minimum noise margins for both the 1 and
0 levels =
12
10
8.0
6.0
4.0
2.0
0
4.0
2.0
4.0
1.0 V with a 5.0 V supply

6.0
8.0
10
Figure 10. VDD = 15 Vdc
Vout
VDD
Vout
VO
VO
VO
VO
VDD
VDD
0
VDD
Vin
VIL
VIH
Vin
VIL
VIH
VSS = 0 VOLTS DC
(a) Inverting Function
(b) NonInverting Function
Figure 11. DC Noise Immunity
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38
MC14001B Series
ORDERING & SHIPPING INFORMATION:
Device
Package
Shipping
Package
Shipping
MC14001BCP
PDIP14
2000 Units per Box
MC14071BCP
Device
PDIP14
2000 Units per Box
MC14001BD
SOIC14
2750 Units per Box
MC14071BD
SOIC14
55 Units per Rail
MC14001BDR2
SOIC14
2500 Units / Tape & Reel
MC14071BDR2
SOIC14
MC14001BDT
TSSOP14
96 Units per Rail
MC14071BDT
TSSOP14
96 Units per Rail
MC14001BDTR2
TSSOP14
96 Units per Rail
MC14071BDTR2
TSSOP14
96 Units per Rail
MC14011BCP
PDIP14
2000 Units per Box
MC14073BCP
PDIP14
2000 Units per Box
MC14011BD
SOIC14
2750 Units per Box
MC14073BD
SOIC14
55 Units per Rail
MC14011BDR2
SOIC14
MC14073BDR2
SOIC14
MC14011BDT
TSSOP14
96 Units per Rail
MC14011BDTEL
TSSOP14
MC14081BCP
PDIP14
2000 Units per Box
MC14011BDTR2
TSSOP14
50 Units per Rail
MC14081BD
SOIC14
55 Units per Rail
MC14081BDR2
SOIC14
MC14023BCP
PDIP14
2000 Units per Box
MC14081BDT
TSSOP14
96 Units per Rail
MC14023BD
SOIC14
2750 Units per Box
MC14081BDTR2
TSSOP14
MC14023BDR2
SOIC14

MC14082BCP
PDIP14
2000 Units per Box
MC14025BCP
PDIP14
2000 Units per Box
MC14082BD
SOIC14
55 Units per Rail
MC14025BD
SOIC14
2750 Units per Box
MC14082BDR2
SOIC14
MC14025BDR2
SOIC14
For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
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39
MC14001UB, MC14011UB
UB-Suffix Series
CMOS Gates
The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired. The UB set of
CMOS gates are inverting nonbuffered functions.

Linear and Oscillator Applications
Schottky TTL Load Over the Rated Temperature Range

Double Diode Protection on All Inputs
PinforPin Replacements for Corresponding CD4000 Series UB
Suffix Devices
http://onsemi.com
MC14001UB
MC14011UB
MARKING
DIAGRAMS
14
PDIP14
P SUFFIX
CASE 646

Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Symbol
VDD
Vin, Vout
Iin, Iout

(DC or Transient)
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
1
14
may occur.
MC140XXUBCP
AWLYYWW
40
SOIC14
D SUFFIX
CASE 751A
140XXU
AWLYWW
1
XX
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14001UBCP
PDIP14
2000/Box
MC14001UBD
SOIC14
55/Rail
MC14001UBDR2
SOIC14
2500/Tape & Reel
MC14011UBCP
PDIP14
2000/Box
MC14011UBD
SOIC14
55/Rail
MC14011UBDR2
SOIC14
2500/Tape & Reel

MC14001UB/D
LOGIC DIAGRAMS
MC14001UB
Quad 2Input
NOR Gate
1
2
5
6
8
9
12
13
MC14011UB
Quad 2Input
NAND Gate
1
2
5
6
8
10
10
9
12
11
11
13
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
PIN ASSIGNMENTS
MC14001UB
MC14011UB
IN 1A
14
VDD
IN 1A
14
VDD
IN 2A
13
IN 2D
IN 2A
13
IN 2D
OUTA
12
IN 1D
OUTA
12
IN 1D
OUTB
11
OUTD
OUTB
11
OUTD
IN 1B
10
OUTC
IN 1B
10
OUTC
IN 2B
IN 2C
IN 2B
IN 2C
VSS
IN 1C
VSS
IN 1C
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41

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
1 Level
IIH
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

Per Gate CL = 50 pF)
Sink
Vdc
mAdc

Adc
where: IT is in H (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
per package.
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42

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL

VDD
Vdc
Min
Typ (7.)
Max
5.0
10
15
180
90
65
360
180
130
5.0
10
15
100
50
40
200
100
80
5.0
10
15
90
50
40
180
100
80
Unit
ns
ns
tPLH, tPHL
ns
20 ns
VDD
INPUT
14
PULSE
GENERATOR
INPUT
OUTPUT
20 ns
VDD
90%
50%
10%
0V
tPLH
tPHL
*
CL
7
VSS
*All unused inputs of AND, NAND gates must be

connected to VDD.
All unused inputs of OR, NOR gates must be
connected to VSS.
tTHL
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43
VOH
90%
50%
10%
OUTPUT
INVERTING
VOL
tTLH
MC14001UB CIRCUIT SCHEMATIC
VDD
14
MC14011UB CIRCUIT SCHEMATIC

(1/4 of Device Shown)
10
14 VDD
1
3, 4, 10, 11
1, 6, 8, 13
2, 5, 9, 12
13
12
16
12
10
8.0
8.0
6.0
5.0 Vdc
4.0
b
15 Vdc
b a
a
4.0
10 Vdc
2.0
2.0
0
5.0 Vdc
4.0
a b
2.0 4.0 6.0 8.0 10 12 14 16

c
10 Vdc
10
c
b
a
8.0
a
6.0
Figure 3. Typical Voltage Transfer

Characteristics versus
Temperature
a TA = 55C
b TA = + 25C
c TA = + 125C
6.0
a TA = + 125C
b TA = 55C
8.0
I D, DRAIN CURRENT (mAdc)
4.0
VGS = 5.0 Vdc
10 Vdc
10
2.0
Figure 2. Typical Voltage and

Current Transfer Characteristics
2.0
12
0
2.0 4.0 6.0 8.0 10 12 14 16
VDD = 15 Vdc Unused input

connected to
b
VSS.
a
14
6.0
16
VDD = 15 Vdc TA = + 25C

Unused input
connected to
VSS.
a One input only
10 Vdc
b Both inputs
14
Vout , OUTPUT VOLTAGE (Vdc)
11
7
VSS
7 VSS
b
c
15 Vdc
8.0
15 Vdc
b
a
VGS = 10 Vdc
b
c
6.0
a TA = 55C
b TA = + 25C
c TA = + 125C
4.0
a
2.0
5.0 Vdc
c
10
10
a
8.0
6.0
4.0
VDS, DRAIN VOLTAGE (Vdc)
a
2.0
0
0
Figure 4. Typical Output Source

Characteristics
2.0
4.0
6.0
8.0
Figure 5. Typical Output Sink

Characteristics
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44
10
MC14007UB
Dual Complementary Pair
Plus Inverter
The MC14007UB multipurpose device consists of three
Nchannel and three Pchannel enhancement mode devices packaged
to provide access to each device. These versatile parts are useful in
inverter circuits, pulseshapers, linear amplifiers, high input
impedance amplifiers, threshold detectors, transmission gating, and
functional gating.
http://onsemi.com
MARKING
DIAGRAMS
Diode Protection on All Inputs

14
PDIP14
P SUFFIX
CASE 646

PinforPin Replacement for CD4007A or CD4007UB
This device has 2 outputs without ESD Protection. Antistatic
precautions must be taken.
MC14007UBCP
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A
14007U
AWLYWW
1
14

Parameter
Symbol
VDD
Vin, Vout

(DC or Transient)
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5
10
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
mA
SOEIAJ14
F SUFFIX
CASE 965
MC14007U
AWLYWW
1
may occur.
to the range VSS
(Vin or Vout)
VDD.
14
007U
ALYW
14

Iin, Iout
TSSOP14
DT SUFFIX
CASE 948G
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14007UBCP
PDIP14
2000/Box
MC14007UBD
SOIC14
55/Rail
MC14007UBDR2
SOIC14
2500/Tape & Reel
MC14007UBDT
TSSOP14
96/Rail
MC14007UBF
SOEIAJ14
See Note 1.
MC14007UBFEL
SOEIAJ14
See Note 1.
1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local
ON Semiconductor representative.
March, 2000 Rev. 3
45

MC14007UB/D
MC14007UB
PIN ASSIGNMENT
DPB
14
VDD
SPB
13
DPA
GATEB
12
OUTC
SNB
11
SPC
DNB
10
GATEC
GATEA
SNC
VSS
DNA
D = DRAIN
S = SOURCE
SCHEMATIC
14
13
11
12
10
VDD = PIN 14
VSS = PIN 7
A
12
9
B
1
C
INPUT
VDD
14
C
11
INPUT OUTPUT CONDITION

1
0
13
INPUT
6
A = C, B = OPEN
A = B, C = OPEN
Substrates of Pchannel devices internally

connected to VDD; substrates of Nchannel
devices internally connected to VSS.
10
VSS
Figure 1. Typical Application: 2Input Analog Multiplexer
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46
MC14007UB

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
5.0
1.0
2.5
10
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
1.0
2.5
10
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
1 Level
VIH
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

Per Gate) (CL = 50 pF)
Sink
Vdc
mAdc
IT = (0.7 A/kHz) f + IDD/6

IT = (1.4 A/kHz) f + IDD/6
IT = (2.2 A/kHz) f + IDD/6
where: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.003.
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47
Adc
MC14007UB

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL
TurnOff Delay Time

tPLH = (1.5 ns/pF) CL + 35 ns
tPLH = (0.15 ns/pF) CL + 17.5 ns
tPLH
TurnOn Delay Time

tPHL = (1.0 ns/pF) CL + 10 ns
tPHL
VDD
Vdc
Min
Typ (8.)
Max
5.0
10
15
90
45
35
180
90
70
5.0
10
15
75
40
30
150
80
60
5.0
10
15
60
30
25
125
75
55
5.0
10
15
60
30
25
125
75
55
Unit
ns
ns
ns
ns
7. The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter.
VDD = VGS
VDD = VGS
14
IOH
7
14
VDS = VOH VDD
IOL
VSS
All unused inputs connected to ground.
20
8.0
b
a
c
12
b
10 Vdc
16
IOL , DRAIN CURRENT (mAdc)
IOH , DRAIN CURRENT (mAdc)
a TA = 55C
b TA = + 25C
c TA = + 125C
15 Vdc
a
a
20
10
VGS = 15 Vdc
c
VGS = 5.0 Vdc
VSS
All unused inputs connected to ground.
4.0
VDS = VOL
16
a
10 Vdc
12
b
c
a TA = 55C
b TA = + 25C
c TA = + 125C
8.0
a
4.0
b 5.0 Vdc
c
0
8.0
6.0
4.0
2.0
Figure 2. Typical Output Source Characteristics
2.0
4.0
6.0
8.0
Figure 3. Typical Output Sink Characteristics
These typical curves are not guarantees, but are design aids.
Caution: The maximum current rating is 10 mA per pin.
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48
10
MC14007UB
VDD
500 F
PULSE
GENERATOR
20 ns
0.01 F
CERAMIC
ID
VSS
tPHL
Vout
VDD
90%
50%
10%
Vin
14
Vin
20 ns
VSS
tPLH
CL
VOH
90%
50%
10%
Vout
VOL
tTHL
tTLH
Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms
APPLICATIONS
VDD
14
The MC14007UB dual pair plus inverter, which has

access to all its elements offers a number of unique circuit
applications. Figures 1, 5, and 6 are a few examples of the
device flexibility.
OUT = A+BC
13
11
+ VDD
2
DISABLE 3
12
10
B
1
8
OUTPUT
11
9
INPUT 10
12 OUTPUT
3
C
9
8
6
A
DISABLE 6
7
Substrates of Pchannel devices internally connected to VDD;

Substrates of Nchannel devices internally connected to VSS.
INPUT
DISABLE
OUTPUT
1
0
X
0
0
1
0
1
OPEN
Figure 6. AOI Functions Using Tree Logic
X = Dont Care
Figure 5. 3State Buffer
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49
MC14008B
4-Bit Full Adder
The MC14008B 4bit full adder is constructed with MOS
Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. This device consists of four full adders with fast
internal lookahead carry output. It is useful in binary addition and
other arithmetic applications. The fast parallel carry output bit allows
highspeed operation when used with other adders in a system.
http://onsemi.com
LookAhead Carry Output

PinforPin Replacement for CD4008B
MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MC14008BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B

Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Symbol
VDD
Vin, Vout
Iin, Iout

(DC or Transient)
may occur.
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
50
14008B
AWLYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966
MC14008B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14008BCP
PDIP16
2000/Box
MC14008BDR2
SOIC16
2500/Tape & Reel
SOEIAJ16
See Note 1.
MC14008BF


MC14008B/D
MC14008B
TRUTH TABLE
(One Stage)
Cin
Cout
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
PIN ASSIGNMENT
A4
16
VDD
B3
15
B4
A3
14
Cout
B2
13
S4
A2
12
S3
B1
11
S2
A1
10
S1
VSS
Cin
BLOCK DIAGRAM
HIGHSPEED
PARALLEL CARRY
B4 15
A4
B3
A3
B2
A2
B1
A1
Cin
14 Cout
ADDER
4
13 S4
C4
ADDER
3
12 S3
C3
ADDER
2
11 S2
C2
ADDER
1
10 S1
VDD = PIN 16
VSS = PIN 8
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51
MC14008B

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
(VO = 0.5 or 4.5 Vdc) 1 Level

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink

Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
Vdc
mAdc
IT = (1.7 A/kHz) f + IDD

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52
Adc
MC14008B

Characteristic
Symbol
Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH,
tTHL

Sum in to Sum Out
Sum In to Carry Out
Carry In to Sum Out
Carry In to Carry Out
VDD
Vdc
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
tPLH, tPHL
ns
5.0
10
15
400
160
115
800
320
230
5.0
10
15
305
145
110
610
290
220
5.0
10
15
375
155
115
750
310
230
5.0
10
15
170
75
55
340
150
110
VDD = VGS
Vout
VDD = VGS
16
B4
A4
B3
A3
B2
A2
S4
B1
A1
Cin
S1
16
S3
S2
IOH
Cout
VSS
Vout
EXTERNAL
POWER
SUPPLY
B4
A4
B3
A3
B2
A2
S4
B1
A1
Cin
S1
Figure 1. Typical Source Current

Characteristics Test Circuit
S3
S2
IOL
Cout
VSS
EXTERNAL
POWER
SUPPLY
Figure 2. Typical Sink Current

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53
MC14008B
VDD
16
20 ns
Vin
20 ns
90%
10%
VDD
VSS
PULSE
GENERATOR
B4
A4
B3
A3
B2
A2
S4
B1
A1
Cin
S1
S3
S2
CL
CL
CL
Cout
CL
CL
VSS
IDD
500 F
Figure 3. Dynamic Power Dissipation Test Circuit and Waveform
VDD
16
B4
A4
B3
A3
B2
A2
B1
A1
PULSE
GENERATOR
Cin
8
S4
S3
S2
CL
S1
CL
CL
Cout
CL
CL
VSS
IDD
20 ns
Cin
20 ns
VDD
90%
50%
10%
VSS
tPHL
tPLH
VOH
90%
50%
10%
S1 S4
VOL
tTHL
tTLH
VOH
Cout
50%
VOL
tPLH
tPHL
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54
MC14008B
Cout
B4
S4
A4
B3
S3
A3
B2
S2
A2
B1
S1
A1
Cin
Figure 5. Logic Diagram
TYPICAL APPLICATION
WORD A + B INPUTS
A1
Cin
S1
B4
CHIP
1
Cout
S4
A1
Cin
S1
B4
CHIP
2
Cout
S4
A1
Cin
S1
B4
CHIP
3
Cout
S4
A1
Cin
B4
CHIP
4
S1
SUM OUTPUTS
Calculation of 16bit adder speed:
tP total = tP (Sum to Carry) + tP (Carry to Sum) + 2 tP (Carry to Carry)
The guaranteed 16bit adder speed at 10 V, 25C, CL = 50 pF is:
tp total = 290 + 310 + 300 = 900 ns
Figure 6. Using the MC14008B in a 16Bit Adder Configuration

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55
Cout
S4
MC14013B
Dual Type D Flip-Flop
The MC14013B dual type D flipflop is constructed with MOS
monolithic structure. Each flipflop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q). These devices may be used as shift register
elements or as type T flipflops for counter and toggle applications.
http://onsemi.com
Static Operation
Logic EdgeClocked FlipFlop Design
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positivegoing
edge of the clock pulse
MARKING
DIAGRAMS
14
PDIP14
P SUFFIX
CASE 646
MC14013BCP
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A
14013B
AWLYWW
1
14
TSSOP14
DT SUFFIX
CASE 948G

Symbol
VDD
Vin, Vout
Parameter
(DC or Transient)
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
SOEIAJ14
F SUFFIX
CASE 965
MC14013B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
may occur.
to the range VSS
(Vin or Vout)
VDD.
1
14

Iin, Iout
14
013B
ALYW
Device
Package
Shipping
MC14013BCP
PDIP14
2000/Box
MC14013BD
SOIC14
55/Rail
MC14013BDR2
SOIC14
2500/Tape & Reel
MC14013BDT
TSSOP14
96/Rail
MC14013BDTR2
TSSOP14 2500/Tape & Reel
MC14013BF
SOEIAJ14
See Note 1.
MC14013BFEL
SOEIAJ14
See Note 1.

March, 2000 Rev. 3
56

MC14013B/D
MC14013B
TRUTH TABLE
Inputs
Clock
Outputs
Data
Reset
Set
X = Dont Care
= Level Change
PIN ASSIGNMENT
QA
14
VDD
QA
13
QB
CA
12
QB
RA
11
CB
DA
10
RB
SA
DB
VSS
SB
BLOCK DIAGRAM
6
5
13
12
4
8
9
11
10
VDD = PIN 14
VSS = PIN 7
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57
No
Change
MC14013B

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc
IT
5.0
10
15

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
Vdc
mAdc

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58
Adc
MC14013B

Characteristic
Symbol

tTLH,
tTHL

Clock to Q, Q
tPLH
tPHL
VDD
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
175
75
50
350
150
100
Set to Q, Q
5.0
10
15
175
75
50
350
150
100
Reset to Q, Q
5.0
10
15
225
100
75
450
200
150
Setup Times (9.)
tsu
5.0
10
15
40
20
15
20
10
7.5
ns
Hold Times (9.)
th
5.0
10
15
40
20
15
20
10
7.5
ns
tWL, tWH
5.0
10
15
250
100
70
125
50
35
ns
fcl
5.0
10
15
4.0
10
14
2.0
5.0
7.0
MHz
tTLH
tTHL
5.0
10
15
15
5.0
4.0
tWL, tWH
5.0
10
15
250
100
70
125
50
35
ns
5
10
15
80
45
35
0
5
5
5
10
15
50
30
25
35
10
5
Clock Pulse Width
Clock Pulse Frequency
Clock Pulse Rise and Fall Time
Set and Reset Pulse Width
trem
Removal Times
Set
ns
Reset
9. Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.
LOGIC DIAGRAM (1/2 of Device Shown)

S
C
D
C
C
C
C
C
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59
MC14013B
20 ns
20 ns
90%
50%
10%
tsu (L)
th
tsu (H)
C
tWH
SET OR
RESET
20 ns
VDD
90%
50%
tw
VSS
10%
trem
20 ns
tPHL
tTLH
VSS
20 ns
90%
50%
CLOCK
90%
50%
10%
20 ns
VSS
20 ns
VDD
90%
50%
10%
tWL
1
fcl
tPLH
VDD
tw
tPLH
tPHL
VOH
VSS
VOH
Q OR Q
VOL
10%
VDD
50%
VOL
tTHL
Inputs R and S low.
Figure 1. Dynamic Signal Waveforms

(Data, Clock, and Output)

(Set, Reset, Clock, and Output)
TYPICAL APPLICATIONS
nSTAGE SHIFT REGISTER
1
D
nth
CLOCK
BINARY RIPPLE UPCOUNTER (Divideby2n)

1
CLOCK
nth
T FLIPFLOP
MODIFIED RING COUNTER (Divideby(n+1))

1
nth
CLOCK
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60
MC14014B, MC14021B
8-Bit Static Shift Register
The MC14014B and MC14021B 8bit static shift registers are
constructed with MOS Pchannel and Nchannel enhancement mode
devices in a single monolithic structure. These shift registers find
primary use in paralleltoserial data conversion, synchronous and
asynchronous parallel input, serial output data queueing; and other
general purpose register applications requiring low power and/or high
noise immunity.
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MARKING
DIAGRAMS
Synchronous Parallel Input/Serial Output (MC14014B)

Asynchronous Parallel Input/Serial Output (MC14021B)
Synchronous Serial Input/Serial Output
Full Static Operation
Q Outputs from Sixth, Seventh, and Eighth Stages
Double Diode Input Protection
MC14014B PinforPin Replacement for CD4014B
MC14021B PinforPin Replacement for CD4021B
16
PDIP16
P SUFFIX
CASE 648
MC140XXBCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
140XXB
AWLYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966

Symbol
VDD
Vin, Vout
Iin, Iout
PD
Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
Power Dissipation,
500
mW

(DC or Transient)
XX
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
may occur.
to the range VSS
(Vin or Vout)
VDD.
MC140XXB
AWLYWW
Package
Shipping
MC14014BCP
PDIP16
2000/Box
MC14014BD
SOIC16
48/Rail
MC14014BDR2
SOIC16
2500/Tape & Reel
MC14014BF
SOEIAJ16
See Note 1.
MC14014BFEL
SOEIAJ16
See Note 1.
MC14021BCP
PDIP16
2000/Box
MC14021BD
SOIC16
48/Rail
MC14021BDR2
SOIC16
2500/Tape & Reel
MC14021BF
SOEIAJ16
See Note 1.
MC14021BFEL
SOEIAJ16
See Note 1.

March, 2000 Rev. 3
61

MC14014B/D
MC14014B, MC14021B
TRUTH TABLE
SERIAL OPERATION:
t
Clock DS P/S
n
n+1
n+2
n+3
Q6
t=n+6
Q7
t=n+7
Q8
t=n+8
0
1
0
1
0
0
0
0
0
1
0
1
?
0
1
0
?
?
0
1
Q6
Q7
Q8
PARALLEL OPERATION:
Clock
MC14014B MC14021B DS
X
X
X
P/S
Pn
*Qn
*Q6, Q7, & Q8 are available externally

X = Dont Care
PIN ASSIGNMENT
P8
16
VDD
Q6
15
P7
Q8
14
P6
P4
13
P5
P3
12
Q7
P2
11
DS
P1
10
VSS
P/S
LOGIC DIAGRAM
P1
P2
7
P3
6
P6
5
P7
14
P8
15
P/S
11
DS
D
C
D
C
10
CLOCK
VDD = PIN 16
VSS = PIN 8
P4 = PIN 4
P5 = PIN 13
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62
2
Q6
12
Q7
3
Q8
MC14014B, MC14021B

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
15
0.005
0.010
0.015
5.0
10
15
150
300
600
Adc
IT
5.0
10
15

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
Vdc
mAdc

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63
Adc
MC14014B, MC14021B

Characteristic
Symbol
VDD
Vdc
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
400
170
115
800
340
230
Unit
ns

tTLH,
tTHL
Propagation Delay Time (Clock to Q, P/S to Q)

tPHL, tPLH = (1.7 ns/pF) CL + 315 ns
tPLH,
tPHL
Clock Pulse Width
tWH
5.0
10
15
400
175
135
150
75
40
ns
fcl
5.0
10
15
3.0
6.0
8.0
1.5
3.0
4.0
MHz
Parallel/Serial Control Pulse Width
tWH
5.0
10
15
400
175
135
150
75
40
ns
Setup Time
P/S to Clock
tsu
5.0
10
15
200
100
80
100
50
40
ns
Hold Time
Clock to P/S
th
5.0
10
15
20
20
25
2.5
10
0
ns
Setup Time
Data (Parallel or Serial) to
Clock or P/S
tsu
5.0
10
15
350
80
60
150
50
30
ns
Hold Time
Clock to Ds
th
5.0
10
15
45
35
35
0
0
5
ns
Hold Time
Clock to Pn
th
5.0
10
15
50
45
45
25
20
20
ns
tr(cl)
5.0
10
15
15
5
4
Clock Frequency
Input Clock Rise Time
ns
VDD
PULSE
GENERATOR
P/S
C
P6
P7
P8
DS
Vout
VDD
Q6
PULSE
GENERATOR
Q7
Q8
IOH
EXTERNAL
POWER
SUPPLY
P/S
C
P6
P7
P8
DS
Vout
Q6
Q7
Q8
IOL
EXTERNAL
POWER
SUPPLY
Preset output under test to a logic 1 level.
Figure 1. Output Source Current Test Circuit
Figure 2. Output Sink Current Test Circuit

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64
MC14014B, MC14021B
VDD
500 F
ID
0.01 F
CERAMIC
P/S
C
P1
P2
P3
P4
P5
P6
P7
P8
DS
PULSE
GENERATOR 1
PULSE
GENERATOR 2
Q6
CL
Q7
CL
Q8
VSS
CL
1
f
CLOCK
50%
DATA
Figure 3. Power Dissipation Test Circuit and Waveform
SW 1
VDD
1
PULSE
GENERATOR 1
PULSE
GENERATOR 2
2
1
2
1
SWITCH POSITION 1 = PARALLEL IN

SWITCH POSITION 2 = SERIAL IN
VDD
P/S
C
P1
P2
P3
P4
P5
P6
P7
P8
DS
20 ns
PARALLEL OR
SERIAL DATA
INPUT
Q6
90%
50%
10%
tsu
tWH
Q7
CLOCK OR P/S
INPUT
CL
Q8
VSS
VSS
tTHL
90%
50%
10%
tWH
tPLH
Q
OUTPUT
SW 2
20 ns
VDD
VDD
VSS
tWL
tPHL
VOH
90%
50%
10%
tTLH
VOL
tTHL
tWL = tWH = 50% DUTY CYCLE
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65
MC14015B
Dual 4-Bit Static
Shift Register
The MC14015B dual 4bit static shift register is constructed with
MOS Pchannel and Nchannel enhancement mode devices in a
single monolithic structure. It consists of two identical, independent
4state serialinput/paralleloutput registers. Each register has
independent Clock and Reset inputs with a single serial Data input.
The register states are type D masterslave flipflops. Data is shifted
from one stage to the next during the positivegoing clock transition.
Each register can be cleared when a high level is applied on the Reset
line. These complementary MOS shift registers find primary use in
buffer storage and serialtoparallel conversion where low power
dissipation and/or noise immunity is desired.
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648

MC14015BCP
AWLYYWW
16
SOIC16
D SUFFIX
CASE 751B
information is transferred to the output only on the positive going
edge of the clock pulse.
Schottky TTL Load Over the Rated Temperature Range.
14015B
AWLYWW
1
16
TSSOP16
DT SUFFIX
CASE 948F
14
015B
ALYW
1

Symbol
16
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
VDD
Vin, Vout
Iin, Iout
Parameter
(DC or Transient)
may occur.
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
66
SOEIAJ16
F SUFFIX
CASE 966
MC14015B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14015BCP
PDIP16
2000/Box
MC14015BD
SOIC16
48/Rail
MC14015BDR2
SOIC16
2500/Tape & Reel
MC14015BDT
MC14015BF
SOEIAJ16
See Note 1.
MC14015BFEL
SOEIAJ16
See Note 1.


MC14015B/D
MC14015B
TRUTH TABLE
C
Q0
Qn
Qn1
Qn1
No Change
No Change
X = Dont Care
Qn = Q0, Q1, Q2, or Q3, as applicable.
Qn1 = Output of prior stage.
PIN ASSIGNMENT
CB
16
VDD
Q3B
15
DB
Q2A
14
RB
Q1A
13
Q0B
Q0A
12
Q1B
RA
11
Q2B
DA
10
Q3A
VSS
CA
BLOCK DIAGRAM
7
Q0
Q1
Q2
C
R Q3
10
Q0
13
Q1
12
Q2
11
6
15
C
R Q3
14
VDD = PIN 16
VSS = PIN 8
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67
MC14015B

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or .05 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
Vdc
mAdc
IT = (1.2 A/kHz)f + IDD

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68
Adc
MC14015B

Characteristic
Symbol

tTLH,
tTHL

Clock, Data to Q
Reset to Q
tPLH,
tPHL
Clock Pulse Width
VDD
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
310
125
90
750
250
170
5.0
10
15
460
180
120
750
250
170
tWH
5.0
10
15
400
175
135
185
85
55
ns
fcl
5.0
10
15
2.0
6.0
7.5
1.5
3.0
3.75
MHz
tTLH, tTHL
5.0
10
15
15
5
4
Reset Pulse Width
tWH
5.0
10
15
400
160
120
200
80
60
ns
Setup Time
tsu
5.0
10
15
350
100
75
100
50
40
ns
Clock Pulse Rise and Fall Times
7. The formulas given are for typical characteristics only at 25_C.

VDD
PULSE
GENERATOR
2
500 F
D
PULSE
GENERATOR
1
0.01 F
CERAMIC
ID
C
R
VDD
Q0
Q1
Q2
Q3
CL
CL
CL
CL
VSS
1
f
CLOCK
50%
DATA
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69
MC14015B
tTLH
tTHL
DATA
INPUT
VDD
90%
50%
10%
0V
tsu
PULSE
GENERATOR
2
VDD
D
PULSE
GENERATOR
1
Q0
CL
Q1
SYNC
CLOCK
INPUT
CL
Q2
C
R
tTLH
tWH
tPLH
CL
Q3
tTHL
90%
Q0
tWL = tWH = 50% Duty Cycle

tTLH = tTHL 20 ns
0V
tPHL
CL
VSS
VDD
90%
50%
10%
tWL
50%
10%
tTHL
tTLH
Figure 2. Switching Test Circuit and Waveforms
PULSE
GENERATOR
2
VDD
D
CL
Q1
SYNC
PULSE
GENERATOR
1
Q0
0V
tsu
CL
Q3
VDD
50%
CL
Q2
C
R
CLOCK
INPUT
th
CL
DATA
INPUT
VSS
50%
Figure 3. Setup and Hold Time Test Circuit and Waveforms
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70
VDD
0V
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71
DATA
IN
VSS
VDD
DATA INPUT BUFFER
DATA
IN
CLOCK
RESET
DATA TO
FIRST BIT
RESET
IN
VSS
VDD
RESET INPUT BUFFER
VSS
VDD
SINGLE BIT
RESET
TO 4 BITS
CLOCK
IN
TO D OF
NEXT BIT
VSS
VDD
CLOCK
TO 4 BITS
CLOCK INPUT BUFFER
MC14015B
CIRCUIT SCHEMATICS
MC14015B
LOGIC DIAGRAMS
SINGLE BIT
Q
TO D OF
NEXT BIT
DATA
C
RESET
C
C
C
COMPLETE DEVICE
5
4
Q0
3
Q1
10
Q2
Q3
DATA INPUT BUFFER

D
D
CLOCK INPUT BUFFER
Q
R
9
R
6
13
RESET INPUT BUFFER
12
Q0
11
Q1
2
Q2
Q3
DATA INPUT BUFFER

D
D
15
CLOCK INPUT BUFFER
C
Q
R
1
VDD = PIN 16
VSS = PIN 8
R
14
RESET INPUT BUFFER
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72
MC14016B
Quad Analog Switch/

Quad Multiplexer
The MC14016B quad bilateral switch is constructed with MOS
monolithic structure. Each MC14016B consists of four independent
switches capable of controlling either digital or analog signals. The
quad bilateral switch is used in signal gating, chopper, modulator,
demodulator and CMOS logic implementation.
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MARKING
DIAGRAMS

Linearized Transfer Characteristics
Low Noise 12 nV/Cycle, f 1.0 kHz typical
PinforPin Replacements for CD4016B, CD4066B (Note improved
transfer characteristic design causes more parasitic coupling
capacitance than CD4016)
For Lower RON, Use The HC4016 HighSpeed CMOS Device or
The MC14066B
This Device Has Inputs and Outputs Which Do Not Have ESD
Protection. Antistatic Precautions Must Be Taken.
14
PDIP14
P SUFFIX
CASE 646
MC14016BCP
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A
14016B
AWLYWW
1
14
SOEIAJ14
F SUFFIX
CASE 965

Parameter
Symbol
VDD
MC14016B
AWLYWW
1
Value
Unit
0.5 to +18.0
Vin, Vout

(DC or Transient)
0.5 to VDD + 0.5
Iin
Input Current (DC or Transient)

per Control Pin
10
mA
ISW
Switch Through Current
25
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
may occur.
Device
Package
Shipping
MC14016BCP
PDIP14
2000/Box
MC14016BD
SOIC14
55/Rail
MC14016BDR2
SOIC14
2500/Tape & Reel
MC14016BF
SOEIAJ14
See Note 1.
MC14016BFEL
SOEIAJ14
See Note 1.

to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
73

MC14016B/D
MC14016B
PIN ASSIGNMENT
IN 1
14
VDD
OUT 1
13
CONTROL 1
OUT 2
12
CONTROL 4
IN 2
11
IN 4
CONTROL 2
10
OUT 4
CONTROL 3
OUT 3
VSS
IN 3
BLOCK DIAGRAM
CONTROL 1
IN 1
CONTROL 2
IN 2
CONTROL 3
IN 3
CONTROL 4
IN 4
13
2
OUT 1
1
5
3
OUT 2
4
6
9
OUT 3
8
12
10
OUT 4
11
VDD = PIN 14
VSS = PIN 7
Control
Switch
0 = VSS
Off
1 = VDD
On
LOGIC DIAGRAM
(1/4 OF DEVICE SHOWN)
OUT
CONTROL
LOGIC DIAGRAM RESTRICTIONS
VSS Vin VDD
VSS Vout VDD
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74
IN
MC14016B

Characteristic
Input Voltage
Control Input
Min
Typ (4.)
Max
Min
Max
Unit
VIL
5.0
10
15
1.5
1.5
1.5
0.9
0.9
0.9
Vdc
VIH
5.0
10
15
3.0
8.0
13
2.0
6.0
11
Vdc
15
0.1
0.00001
0.1
1.0
Adc
5.0
5.0
5.0
0.2
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
5.0
600
600
600
300
300
280
660
660
660
840
840
840
7.5
360
360
360
240
240
180
400
400
400
520
520
520
10
600
600
600
260
310
310
660
660
660
840
840
840
15
360
360
360
260
260
300
400
400
400
520
520
520
Iin
Input Capacitance
Control
Switch Input
Switch Output
Feed Through
Cin
Quiescent Current
(Per Package) (5.)
2,3
IDD
4,5,6
RON
pF
(Vin = + 7.5 Vdc)

(Vin = 7.5 Vdc) VSS = 7.5 Vdc
(Vin = 0.25 Vdc)
(Vin = + 10 Vdc)
(Vin = + 0.25 Vdc) VSS = 0 Vdc
(Vin = + 5.6 Vdc)
(Vin = + 15 Vdc)
(Vin = + 0.25 Vdc) VSS = 0 Vdc
(Vin = + 9.3 Vdc)
Input/Output Leakage Current

(VC = VSS)
(Vin = + 7.5, Vout = 7.5 Vdc)
(Vin = 7.5, Vout = + 7.5 Vdc)
125_C
Max
ON Resistance
Between any 2 circuits in a common
package
(VC = VDD)
(Vin = 5.0 Vdc, VSS = 5.0 Vdc)
(Vin = 7.5 Vdc, VSS = 7.5 Vdc)
25_C
Min
Symbol
Input Current Control
ON Resistance
(VC = VDD, RL = 10 k)
(Vin = + 5.0 Vdc)
(Vin = 5.0 Vdc) VSS = 5.0 Vdc
(Vin = 0.25 Vdc)
55_C
VDD
Vdc
Figure
Adc
Ohms
RON
Ohms
5.0
7.5
15
10
Adc
7.5
7.5
0.1
0.1
0.0015
0.0015
0.1
0.1
1.0
1.0
NOTE: All unused inputs must be returned to VDD or VSS as appropriate for the circuit application.
5. For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e., the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.
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75
MC14016B
ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)

Characteristic
VDD
Vdc
Min
Typ (7.)
Max
Unit
5.0
10
15
15
7.0
6.0
45
15
12
ns
5.0
10
15
34
20
15
90
45
35
5.0
10
15
30
50
100
mV
5.0
80
dB
10,11
5.0
10
15
24
25
30
nV/Cycle
5.0
10
15
12
12
15
0.16
Figure
Symbol
Propagation Delay Time (VSS = 0 Vdc)

Vin to Vout
(VC = VDD, RL = 10 k)
tPLH,
tPHL
Control to Output
(Vin
10 Vdc, RL = 10 k)
tPHZ,
tPLZ,
tPZH,
tPZL
Crosstalk, Control to Output (VSS = 0 Vdc)

(VC = VDD, Rin = 10 k, Rout = 10 k,
f = 1.0 kHz)
Crosstalk between any two switches (VSS = 0 Vdc)

(RL = 1.0 k, f = 1.0 MHz,
V
crosstalk
20 log10 out1)
Vout2
Noise Voltage (VSS = 0 Vdc)
(VC = VDD, f = 100 Hz)
(VC = VDD, f = 100 kHz)
ns
Second Harmonic Distortion (VSS = 5.0 Vdc)

(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,
RL = 10 k, f = 1.0 kHz)
5.0
Insertion Loss (VC = VDD, Vin = 1.77 Vdc,

VSS = 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz)
V
Iloss
20 log10 out)
Vin
(RL = 1.0 k)
(RL = 10 k)
(RL = 100 k)
(RL = 1.0 M)
12
5.0
Bandwidth ( 3.0 dB)

(VC = VDD, Vin = 1.77 Vdc, VSS = 5.0 Vdc,
RMS centered @ 0.0 Vdc)
(RL = 1.0 k)
(RL = 10 k)
(RL = 100 k)
(RL = 1.0 M)
OFF Channel Feedthrough Attenuation
(VSS = 5.0 Vdc)
Vout
50 dB)
(VC = VSS, 20 log10
Vin
(RL = 1.0 k)
(RL = 10 k)
(RL = 100 k)
(RL = 1.0 M)
dB
12,13
BW
2.3
0.2
0.1
0.05
5.0
MHz
54
40
38
37
5.0
kHz
1250
140
18
2.0
6. The formulas given are for typical characteristics only at 25_C.

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76
MC14016B
VC
IS
Vin
Vout
VIL: VC is raised from VSS until VC = VIL.

VIL: at VC = VIL: IS = 10 A with Vin = VSS, Vout = VDD or Vin = VDD, Vout = VSS.
VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met.
Figure 1. Input Voltage Test Circuit
10,000
PD , POWER DISSIPATION (W)
VDD = 15 Vdc
VDD
ID
PULSE
GENERATOR
TO ALL
4 CIRCUITS
VDD
Vout
10 k
CONTROL
INPUT
fc
VSS
TA = 25C
10 Vdc
5.0 Vdc
1000
100
Vin
10
1.0
5.0 k 10 k
PD = VDD x ID
Figure 2. Quiescent Power Dissipation

Test Circuit
100 k
1.0 M
fc, FREQUENCY (Hz)
10 M
50 M
Figure 3. Typical Power Dissipation per Circuit

(1/4 of device shown)
TYPICAL RON versus INPUT VOLTAGE

700
RL = 10 k
TA = 25C
600
R ON, ON RESISTANCE (OHMS)
R ON, ON RESISTANCE (OHMS)
700
500
400
VC = VDD = 5.0 Vdc

VSS = 5.0 Vdc
300
200
100
0
10 8.0
VC = VDD = 7.5 Vdc

VSS = 7.5 Vdc
VSS = 0 Vdc
RL = 10 k
TA = 25C
600
500
400
VC = VDD = 10 Vdc
300
200
VC = VDD = 15 Vdc
100
0
4.0
0
4.0
8.0
10
Figure 4. VSS = 5.0 V and 7.5 V
2.0
6.0
10
14
Figure 5. VSS = 0 V
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77
18
20
MC14016B
Vout
RL
CL
Vin
Vout
20 ns
RL
20 ns
90%
50%
Vin
VC
tPLH
Figure 6. RON Characteristics

Test Circuit
10%
tPHL
VSS
50%
Vout
Vin
VDD
Figure 7. Propagation Delay Test Circuit

and Waveforms
Vout
VC
RL
CL
VX
Vin
20 ns
50%
VC
tPZH
Vout
Vout
VDD
90%
10%
tPHZ
90%
10%
tPZL
Vout
10 k
VC
VSS
Vin = VDD
Vx = VSS
15 pF
Vin
tPLZ
1k
90%
10%
Vin = VSS
Vx = VDD
Figure 8. TurnOn Delay Time Test Circuit

and Waveforms
Figure 9. Crosstalk Test Circuit
35
OUT
VC = VDD
IN
QUANTECH
MODEL
2283
OR EQUIV
NOISE VOLTAGE (nV/ CYCLE)
30
VDD = 15 Vdc
25
10 Vdc
20
5.0 Vdc
15
10
5.0
0
10
Figure 10. Noise Voltage Test Circuit
100
1.0 k
f, FREQUENCY (Hz)
10 k
Figure 11. Typical Noise Characteristics
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78
100 k
MC14016B
2.0
TYPICAL INSERTION LOSS (dB)
RL = 1 M AND 100 k
0
10 k
2.0
1.0 k
4.0
3.0 dB (RL = 1.0 M )
6.0
3.0 dB (RL = 10 k )
Vout
RL
VC
3.0 dB (RL = 1.0 k )

8.0
+ 2.5 Vdc
0.0 Vdc
2.5 Vdc
10
12
10 k
Vin
100 k
1.0 M
10 M
fin, INPUT FREQUENCY (Hz)
100 M
Figure 12. Typical Insertion Loss/Bandwidth

Characteristics
Figure 13. Frequency Response Test Circuit
ON SWITCH
CONTROL
SECTION
OF IC
LOAD
V
SOURCE
Figure 14. V Across Switch
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79
MC14016B
APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Switch. The 0to5
V Digital Control signal is used to directly control a 5 Vpp
analog signal.
The digital control logic levels are determined by VDD
and VSS. The VDD voltage is the logic high voltage; the VSS
voltage is logic low. For the example, VDD = + 5 V logic high
at the control inputs; VSS = GND = 0 V logic low.
The maximum analog signal level is determined by VDD
and VSS. The analog voltage must not swing higher than
VDD or lower than VSS.
The example shows a 5 Vpp signal which allows no

margin at either peak. If voltage transients above VDD
and/or below VSS are anticipated on the analog channels,
external diodes (Dx) are recommended as shown in Figure
B. These diodes should be small signal types able to absorb
the maximum anticipated current surges during clipping.
The absolute maximum potential difference between
VDD and VSS is 18.0 V. Most parameters are specified up to
15 V which is the recommended maximum difference
between VDD and V SS.
+5 V
VSS
VDD
+5 V
5 Vpp
ANALOG SIGNAL
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
+ 5.0 V
SWITCH
IN
SWITCH
OUT
5 Vpp
+ 2.5 V
ANALOG SIGNAL
0TO5 V DIGITAL
GND
CONTROL SIGNALS
MC14016B
Figure A. Application Example
VDD
VDD
Dx
Dx
SWITCH
IN
SWITCH
OUT
Dx
Dx
VSS
VSS
Figure B. External Germanium or Schottky Clipping Diodes
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80
MC14017B
Decade Counter
The MC14017B is a fivestage Johnson decade counter with
builtin code converter. High speed operation and spikefree outputs
are obtained by use of a Johnson decade counter design. The ten
decoded outputs are normally low, and go high only at their
appropriate decimal time period. The output changes occur on the
positivegoing edge of the clock pulse. This part can be used in
frequency division applications as well as decade counter or decimal
decode display applications.
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MARKING
DIAGRAMS
Fully Static Operation

DC Clock Input Circuit Allows Slow Rise Times
Carry Out Output for Cascading
DividebyN Counting
Triple Diode Protection on All Inputs
16
PDIP16
P SUFFIX
CASE 648
MC14017BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14017B
AWLYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966

Symbol
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
VDD
Vin, Vout
Iin, Iout
Parameter
(DC or Transient)
may occur.
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
81
MC14017B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14017BCP
PDIP16
2000/Box
MC14017BD
SOIC16
48/Rail
MC14017BDR2
SOIC16
2500/Tape & Reel
MC14017BF
SOEIAJ16
See Note 1.
MC14017BFEL
SOEIAJ16
See Note 1.
1. For ordering information on the EIAJ version of the

SOIC packages, please contact your local ON
Semiconductor representative.

MC14017B/D
MC14017B
PIN ASSIGNMENT
Q5
16
VDD
Q1
15
RESET
Q0
14
CLOCK
Q2
13
CE
Q6
12
Cout
Q7
11
Q9
Q3
10
Q4
VSS
Q8
FUNCTIONAL TRUTH TABLE

(Positive Logic)
Clock
Clock
Enable
0
X
X
X
1
X
0
X
X
1
BLOCK DIAGRAM
Reset
Decode
Output=n
0
0
1
0
0
0
0
n
n
Q0
n+1
n
n
n+1
CLOCK 14
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Cout
CLOCK
13
ENABLE
RESET 15
X = Dont Care. If n < 5 Carry = 1,

Otherwise = 0.
3
2
4
7
10
1
5
6
9
11
12
VDD = PIN 16
VSS = PIN 8
LOGIC DIAGRAM
Q5
Q1
C Q
C
D Q
R R
C Q
C
D Q
R R
Q7
6
Q3
7
Q9
11
14
CLOCK
CLOCK
ENABLE
RESET
12
13
15
C Q
C
D Q
R R
5
Q0
4
Q6
Q2
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82
C Q
C
D Q
R R
C Q
C
D Q
R R
10
Q3
Q4
CARRY
MC14017B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

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83
Adc
MC14017B

Characteristic
Symbol

tTLH,
tTHL

Reset to Decode Output
tPLH, tPHL = (0.66 ns/PF) CL + 197 ns
tPLH,
tPHL

Clock to Cout
tPLH,
tPHL

Clock to Decode Output
tPLH,
tPHL
TurnOff Delay Time

Reset to Cout
tPLH = (0.66 ns/pF) CL + 142 ns
tPLH
Clock Pulse Width
VDD
Vdc
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
500
230
175
1000
460
350
ns
5.0
10
15
400
175
125
800
350
250
ns
5.0
10
15
500
230
175
1000
460
350
ns
5.0
10
15
400
175
125
800
350
250
tw(H)
5.0
10
15
250
100
75
125
50
35
ns
fcl
5.0
10
15
5.0
12
16
2.0
5.0
6.7
MHz
Reset Pulse Width
tw(H)
5.0
10
15
500
250
190
250
125
95
ns
Reset Removal Time
trem
5.0
10
15
750
275
210
375
135
105
ns
Clock Input Rise and Fall Time
tTLH,
tTHL
5.0
10
15
Clock Enable Setup Time
tsu
5.0
10
15
350
150
115
175
75
52
ns
Clock Enable Removal Time
trem
5.0
10
15
420
200
140
260
100
70
ns
Clock Frequency
No Limit
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84
MC14017B
VDD
VSS
VDD
VSS
A
B
S1
S1
Vout
CLOCK Q0
ENABLE
Q1
Q2
Q3
Q4
RESET Q5
Q6
Q7
Q8
Q9
CLOCK Cout
Output
Sink Drive
Output
Source Drive
Decode
Outputs
(S1 to A)
Clock to
desired
outputs
(S1 to B)
Carry
Clock to 5
thru 9
(S1 to B)
S1 to A
VGS =
VDD
VDD
VDS =
Vout
Vout VDD
ID
EXTERNAL
POWER
SUPPLY
VSS
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
VDD
500 F
0.01 F
CERAMIC
ID
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Cout
CLOCK
ENABLE
RESET
PULSE
GENERATOR
fc
CLOCK
VSS
CL
CL
CL
CL
CL
Figure 2. Typical Power Dissipation Test Circuit
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85
CL
CL
CL
CL
CL
CL
MC14017B
Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
RESET
CLOCK
CE MC14017B
RESET
CLOCK
CE MC14017B
Q0 Q1 Q8 Q9
Q0Q1 Q8 Q9
9 DECODED
OUTPUTS
RESET
CLOCK
CE MC14017B
Q1 Q8 Q9
8 DECODED
OUTPUTS
8 DECODED
OUTPUTS
CLOCK
FIRST STAGE
INTERMEDIATE STAGES
LAST STAGE
Figure 3. Counter Expansion
Pcp
Ncp
90%
CLOCK
50%
trem
CLOCK
ENABLE
trem
RESET
20 ns
Q0
Q2
Q3
Q4
20 ns
20 ns
VDD
20 ns
20 ns
20 ns
tPLH
tPHL
tTLH
tPHL
90%
10%
tPLH
VDD
VSS
tPLH
tPHL
tPLH
tTLH
tPHL
tTHL
tTLH
VOH
VOL
tTHL
VOH
50%
tPLH
tPHL
tTLH
tPHL
tPLH
tPLH
tTHL
VOL
tTHL
VOH
VOL
tTHL
tTLH
tPHL
tTLH
tPHL
90%
10%
tTHL
VOH
VOL
Q7
tTHL
Q8
VOH
VOL
tPLH
tTLH
tTHL
tPLH
tPHL
Q9
Cout
tPHL
VOH
VOL
VOH
VOL
tTHL
tPHL
tPLH
VOH
VOL
VOH
VOL
50%
Q5
Q6
VDD
VSS
VSS
tPLH
Q1
tsu
10%
tTLH
tPLH
tTHL
tPHL
tTLH
Figure 4. AC Measurement Definition and Functional Waveforms
http://onsemi.com
86
tTHL
VOH
VOL
VOH
VOL
MC14018B
Presettable Divide-By-N
Counter
The MC14018B contains five Johnson counter stages which are
asynchronously presettable and resettable. The counters are
synchronous, and increment on the positive going edge of the clock.
Presetting is accomplished by a logic 1 on the preset enable input.
Data on the Jam inputs will then be transferred to their respective Q
outputs (inverted). A logic 1 on the reset input will cause all Q outputs
to go to a logic 1 state.
Division by any number from 2 to 10 can be accomplished by
connecting appropriate Q outputs to the data input, as shown in the
Function Selection table. Antilock gating is included in the
MC14018B to assure proper counting sequence.
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648

Schmitt Trigger on Clock Input
MC14018BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B

14018B
AWLYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966

Symbol
VDD
Parameter
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Vin, Vout
Iin, Iout
Value

(DC or Transient)
may occur.
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
87
MC14018B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14018BCP
PDIP16
2000/Box
MC14018BD
SOIC16
48/Rail
MC14018BDR2
SOIC16
2500/Tape & Reel
MC14018BF
SOEIAJ16
See Note 1.
MC14018BFEL
SOEIAJ16
See Note 1.


MC14018B/D
MC14018B
PIN ASSIGNMENT
Din
16
VDD
JAM 1
15
JAM 2
14
Q2
13
Q5
Q1
12
JAM 5
Q3
11
Q4
JAM 3
10
PE
VSS
JAM 4

Clock
Reset
Preset
Enable
Jam
Input
Qn
X
X
X
0
0
0
0
1
0
0
1
1
X
X
X
0
1
X
Qn
Dn *
1
0
1
*Dn is the Data input for that stage. Stage 1

has Data brought out to Pin 1.
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88
MC14018B

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
Vdc
mAdc

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89
Adc
MC14018B

Characteristic
Symbol

All Types
VDD
Vdc
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
tTLH, tTHL
ns
tPLH,
tPHL

Clock to Q
Unit
ns
5.0
10
15
310
120
85
620
240
170
Reset to Q
tPLH = (0.90 ns/pF) CL + 325 ns
tPLH = (0.36 ns/pF) CL + 132 ns
5.0
10
15
370
150
100
740
300
200
Preset Enable to Q
5.0
10
15
370
150
100
740
300
200
5.0
10
15
200
100
80
0
0
0
5.0
10
15
200
100
80
0
0
0
ns
th
5.0
10
15
540
500
480
270
250
240
ns
Clock Pulse Width
tWH
5.0
10
15
400
200
160
200
100
80
ns
Reset or Preset Enable

Pulse Width
tWH
5.0
10
15
290
130
110
145
65
55
ns
tTLH, tTHL
5.0
10
15
ns
ns
tsu
Setup Time
Data (Pin 1) to Clock
ns
Jam Inputs to Preset Enable
Data (Jam Inputs)toPreset

Enable Hold Time
Clock Rise and Fall Time
fcl
ns
No Limit
5.0
10
15
2.5
6.5
8.0
1.25
3.25
4.0
20 ns
20 ns
VDD
90%
50%
10%
ANY INPUT
VSS
tPLH
tPHL
VOH
90%
ANY OUTPUT
50%
10%
VOL
tTLH
tTHL
Figure 1. Switching Time Waveforms
http://onsemi.com
90
MHz
MC14018B
1
CLOCK
0
1
0
1
0
1
0
1
0
RESET
PRESET ENABLE
JAM 1
JAM 2
TIMING DIAGRAM
(Q5 Connected to Data Input)
JAM 3
JAM 4
1
0
1
0
1
0
1
DONT CARE
UNTIL PRESET ENABLE
GOES HIGH
JAM 5
Q1
0
1
Q2
0
1
0
1
0
1
Q3
Q4
Q5
FUNCTION SELECTION
Counter
Mode
Connect
Data Input
(Pin 1) to:
Divide by 10
Divide by 8
Divide by 6
Divide by 4
Divide by 2
Q5
Q4
Q3
Q2
Q1
No external
components needed.
Divide by 9
Divide by 7
Divide by 5
Divide by 3
Q5 Q4
Q4 Q3
Q3 Q2
Q2 Q1
Gate package needed

to provide AND
function. Counter
Skips all 1s state
Comments
LOGIC DIAGRAM
CLOCK 14
DATA
JAM 1
2
JAM 2
3
JAM 3
7
JAM 4
9
JAM 5
12
CLOCK
SHAPER
Q
R P
R P
R P
R P
R P
RESET 15
PRESET ENABLE 10
VDD = PIN 16
VSS = PIN 8
4
Q1
http://onsemi.com
91
Q2
11
Q3
13
Q4
Q5
MC14020B
14-Bit Binary Counter
The MC14020B 14stage binary counter is constructed with MOS
monolithic structure. This part is designed with an input wave shaping
circuit and 14 stages of ripplecarry binary counter. The device
advances the count on the negativegoing edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequencydividing circuits.
http://onsemi.com
MARKING
DIAGRAMS

Buffered Outputs Available from stages 1 and 4 thru 14
Common Reset Line
16
PDIP16
P SUFFIX
CASE 648
MC14020BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14020B
AWLYWW
1
16

Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Symbol
VDD
Vin, Vout
Iin, Iout

(DC or Transient)
may occur.
to the range VSS
(Vin or Vout)
VDD.
TSSOP16
DT SUFFIX
CASE 948F
14
020B
ALYW
1
16
SOEIAJ16
F SUFFIX
CASE 966
MC14020B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14020BCP
PDIP16
2000/Box
MC14020BD
SOIC16
48/Rail
MC14020BDR2
SOIC16
2500/Tape & Reel
MC14020BDT
TSSOP16
96/Rail
MC14020BF
SOEIAJ16
See Note 1.
MC14020BFEL
SOEIAJ16
See Note 1.

March, 2000 Rev. 3
92

MC14020B/D
MC14020B
PIN ASSIGNMENT
Q12
16
VDD
Q13
15
Q11
Q14
14
Q10
Q6
13
Q8
Q5
12
Q9
Q7
11
Q4
10
VSS
Q1
TRUTH TABLE
Clock
Reset
Output State
0
0
1
No Change
Advance to Next State
All Outputs are Low
X = Dont Care
LOGIC DIAGRAM
Q1
Q4
9
Q5
7
Q12
1
Q13
2
Q14
3
CLOCK
10
C
C
RESET
11
Q6 = PIN 4
Q7 = PIN 6
Q8 = PIN 13
Q9 = PIN 12
Q10 = PIN 14
Q11 = PIN 15
http://onsemi.com
93
VDD = PIN 16
VSS = PIN 8
MC14020B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

http://onsemi.com
94
Adc
MC14020B

Characteristic
Symbol

tTLH,
tTHL

Clock to Q1
tPLH,
tPHL
Clock to Q14
tPHL, tPLH (1.7 ns/pF) CL + 1735 ns
tPHL
Clock Pulse Width
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
260
115
80
520
230
160
5.0
10
15
1820
805
560
3900
1725
1200
ns

Reset to Qn
tPHL = (0.66 ns/pF) CL + 122 ns
VDD
Vdc
ns
5.0
10
15
370
155
115
740
310
230
tWH
5.0
10
15
500
165
125
140
55
38
ns
fcl
5.0
10
15
2.0
6.0
8.0
1.0
3.0
4.0
MHz
tTLH, tTHL
5.0
10
15
No Limit
Reset Pulse Width
tWL
5.0
10
15
3000
550
420
320
120
80
ns
Reset Removal Time
trem
5.0
10
15
130
50
30
65
25
15
ns
http://onsemi.com
95
MC14020B
VDD
VDD
500 F
PULSE
GENERATOR
0.01 F
CERAMIC
ID
C Q1
Q4
Qn
R
C Q1
Q4
Q
R n
20 ns
CL
20 ns
CLOCK
20 ns
90%
50%
10%
tWH
20 ns
VDD
tPLH
VSS
90%
50%
10%
Q
tTLH
Figure 1. Power Dissipation Test Circuit

and Waveform
2
CL
CL
CL
90%
50%
10%
50% DUTY CYCLE
CL
VSS
VSS
CLOCK
PULSE
GENERATOR
16
tPHL
tTHL
Figure 2. Switching Time Test Circuit

and Waveforms
32
64
128
256
512
CLOCK
RESET
Q1
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Figure 3. Timing Diagram
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96
1024
2048
4096
8192
16,384
CL
MC14022B
Octal Counter
The MC14022B is a fourstage Johnson octal counter with builtin
code converter. Highspeed operation and spikefree outputs are
obtained by use of a Johnson octal counter design. The eight decoded
outputs are normally low, and go high only at their appropriate octal
time period. The output changes occur on the positivegoing edge of
the clock pulse. This part can be used in frequency division
applications as well as octal counter or octal decode display
applications.
http://onsemi.com
MARKING
DIAGRAMS

DC Clock Input Circuit Allows Slow Rise Times
Carry Out Output for Cascading
16
PDIP16
P SUFFIX
CASE 648
MC14022BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14022B
AWLYWW
1

Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Symbol
VDD
Vin, Vout
Iin, Iout

(DC or Transient)
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14022BCP
PDIP16
2000/Box
MC14022BD
SOIC16
2400/Box
MC14022BDR2
SOIC16
2500/Tape & Reel
may occur.
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
97

MC14022B/D
MC14022B
PIN ASSIGNMENT
Q1
16
VDD
Q0
15
Q2
14
Q5
13
CE
Q6
12
Cout
NC
11
Q4
Q3
10
Q7
VSS
NC
NC = NO CONNECTION
BLOCK DIAGRAM
CLOCK
14
CLOCK
ENABLE
13
RESET
15
VDD = PIN 16
VSS = PIN 8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Cout

(Positive Logic)
2
1
3
7
11
4
5
10
12
Clock
Clock
Enable
0
X
X
1
0
X
1
X
X
Reset
Output=n
0
0
0
0
0
0
1
n
n
n+1
n
n+1
n
Q0
X = Dont Care. If n < 4 Carry = 1,

Otherwise = 0.
NC = PIN 6, 9
LOGIC DIAGRAM
11
1
Q4
5
Q1
7
Q6
Q3
CLOCK
14
13
CLOCK
ENABLE
15
RESET
VDD
VSS
C Q
C
D RQ
C Q
C
D RQ
Q0
2
Q5
4
http://onsemi.com
98
C Q
C
D RQ
C Q
C
D RQ
Q2
3
Q7
10
CARRY
12
MC14022B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

http://onsemi.com
99
Adc
MC14022B

Characteristic
Symbol

tTLH,
tTHL

Reset to Decode Output
tPLH,
tPHL

Clock to Cout
tPLH,
tPHL

Clock to Decode Output
tPLH,
tPHL
TurnOff Delay Time

Reset to Cout
tPLH = (0.66 ns/pF) CL + 142 ns
tPLH
Clock Pulse Width
VDD
Vdc
Min
Typ (7.)
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
500
230
175
1000
460
350
ns
5.0
10
15
400
175
125
800
350
250
ns
5.0
10
15
275
125
95
1000
460
350
ns
5.0
10
15
400
175
125
800
350
250
tWH
5.0
10
15
250
100
75
125
50
35
ns
fcl
5.0
10
15
5.0
12
16
2.0
5.0
6.7
MHz
Reset Pulse Width
tWH
5.0
10
15
500
250
190
250
125
95
ns
Reset Removal Time
trem
5.0
10
15
750
275
210
375
135
105
ns
tTLH, tTHL
5.0
10
15
Clock Frequency
No Limit
Clock Enable Setup Time
tsu
5.0
10
15
350
150
115
175
75
52
ns
Clock Enable Removal Time
trem
5.0
10
15
420
200
140
260
100
70
ns
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100
MC14022B
VDD
VSS
VDD
VSS
S1
Output
Sink Drive
Output
Source Drive
Outputs
(S1 to A)
Clock to desired
Output
(S1 to B)
Carry
Clock to Q5
thru Q7
(S1 to B)
S1 to A
VGS =
VDD
VDD
VDS =
Vout
Vout VDD
Vout
CLOCK Q0
ENABLE Q1
Q2
Q3
RESET Q4
Q5
Q6
Q7
CLOCK C
out
ID
EXTERNAL
POWER
SUPPLY
VSS
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
VDD
500 F
0.01 F
CERAMIC
ID
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Cout
CLOCK
ENABLE
RESET
PULSE
GENERATOR
fc
CLOCK
CL
VSS
CL
CL
CL
CL
CL
CL
CL
CL
Figure 3 shows a technique for extending the number of decoded output states for the MC14022B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
R
MC14022B
CE
Q0 Q1 Q6 Q7
7 DECODED
OUTPUTS
R
MC14022B
CE
Q0 Q1 Q6 Q7
6 DECODED
OUTPUTS
R
MC14022B
CE
Q1 Q6 Q7
6 DECODED
OUTPUTS
CLOCK
FIRST STAGE
INTERMEDIATE STAGES
Figure 3. Counter Expansion

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101
LAST STAGE
MC14022B
tWH
tWL
90%
CLOCK
trel
CLOCK
ENABLE
tsu
20 ns
trem
10%
20 ns
20 ns
20 ns
VDD
20 ns
VSS
tPLH
tPHL
tPLH
50%
tPLH
tPHL
tTHL
90%
Q1
VSS
VDD
RESET
Q0
VDD
50%
VSS
tPLH
tPHL
VOH
VOL
VOH
50%
10%
VOL
tTLH
VOH
Q2
tPLH
tPHL
VOL
tTLH
VOH
Q3
tPLH
tPHL
VOL
tTLH
VOH
Q4
tPLH
Q5
tTLH
tPHL
tPLH
VOL
tTLH
tTHL
tPHL
tTLH
tPHL
tTHL
VOH
Q6
VOL
tPLH
tPHL
VOH
Q7
Cout
tPHL
VOH
VOL
tTLH
tPLH
tTHL
VOL
VOH
tPHL
VOL
tTLH
Figure 4. AC Measurement Definition and Functional Waveforms
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102
tTHL
MC14024B
7-Stage Ripple Counter
The MC14024B is a 7stage ripple counter with short propagation
delays and high maximum clock rates. The Reset input has standard
noise immunity, however the Clock input has increased noise
immunity due to Hysteresis. The output of each counter stage is
buffered.
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Output Transitions Occur on the Falling Edge of the Clock Pulse
MARKING
DIAGRAMS
14
PDIP14
P SUFFIX
CASE 646
MC14024BCP
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A

Parameter
Symbol
VDD
Vin, Vout

(DC or Transient)
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Iin, Iout
may occur.
to the range VSS
(Vin or Vout)
VDD.
14024B
AWLYWW
1
14
SOEIAJ14
F SUFFIX
CASE 965
MC14024B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14024BCP
PDIP14
2000/Box
MC14024BD
SOIC14
2750/Box
MC14024BDR2
SOIC14
2500/Tape & Reel
MC14024BF
SOEIAJ14
See Note 1.
MC14024BFEL
SOEIAJ14
See Note 1.

March, 2000 Rev. 3
103

MC14024B/D
MC14024B
TRUTH TABLE
Clock
Reset
State
No Change
All Outputs Low
No Change
All Outputs Low
No Change
All Outputs Low
Advance One Count
All Outputs Low
PIN ASSIGNMENT
CLOCK
14
VDD
RESET
13
NC
Q7
12
Q1
Q6
11
Q2
Q5
10
NC
Q4
Q3
VSS
NC
VDD = PIN 14
VSS = PIN 7
NC = NO CONNECTION
LOGIC DIAGRAM
1
CLOCK
2
RESET
12
Q1
11
Q2
4
Q6
Q3 = PIN 9
Q4 = PIN 6
Q5 = PIN 5
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104
3
Q7
MC14024B

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
Vdc
mAdc

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105
Adc
MC14024B

Characteristic
Symbol

tTLH,
tTHL

Clock to Q1
Clock to Q7
Reset to Qn
tPLH,
tPHL
Clock Pulse Width
VDD
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
380
150
110
600
230
175
5.0
10
15
1000
400
300
2000
750
565
5.0
10
15
500
250
180
800
400
300
tWH
5.0
10
15
500
165
125
200
60
40
ns
Reset Pulse Width
tWH
5.0
10
15
600
350
260
375
200
150
ns
Reset Removal Time
trem
5.0
10
15
625
190
145
250
75
50
ns
tTLH, tTHL
5.0
10
15
1.0
8.0
200
s
ms
s
fcl
5.0
10
15
2.5
8.0
12
1.0
3.0
4.0
MHz
Input Pulse Frequency
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106
MC14024B
VDD
VOL = Vout
VDD
VOH = Vout
VDD
C Qn
R
COUNT Qn TO A
LOGIC 1 LEVEL.
C Qn
IOH
VSS
IOL
EXTERNAL
POWER
SUPPLY
VSS


VDD
500 F
PULSE
GENERATOR
EXTERNAL
POWER
SUPPLY
0.01 F
CERAMIC
ID
C Q1
Q2
Q3
Q4
Q5
Q6
R Q7
VSS
CL
CL
CL
CL
CL
CL
CL
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107
108
Figure 4. Functional Waveforms
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Q7 (3)
Q6 (4)
Q5 (5)
Q4 (6)
Q3 (9)
Q2 (11)
Q1 (12)
RESET (2)
CLOCK (1)
t rem
t WH
t TLH
t PLH1
t WL
2
t PLH3
t TLH
10%
90%
50%
t PHL1
t TLH
t PLH4
50%
t PHL2
Input t TLH and t THL = 20 ns
t PLH2
t TLH
10%
90%
50%
t PLH5
t TLH
50%
t PHL3
16
t TLH
t PLH6
50%
t PHL4
32
t PHL6
t TLH
t PLH7
50%
t PHL5
64
t THL
t PHL7
50%
t THL
t THL
t THL
t THL
t THL
128
t THL
10%
90%
255
t R7
t R6
t R5
t R4
t R3
t R2
t R1
50%
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VSS
VDD
VSS
VDD
MC14024B
MC14027B
Dual J-K Flip-Flop
The MC14027B dual JK flipflop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flipflop. These devices may be
used in control, register, or toggle functions.

Logic Swing Independent of Fanout
information is transferred to the output only on the positivegoing
edge of the clock pulse
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MC14027BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B

Symbol
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
VDD
Vin, Vout
Iin, Iout
Parameter
(DC or Transient)
may occur.
to the range VSS
(Vin or Vout)
VDD.
14027B
AWLYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966
MC14027B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14027BCP
PDIP16
2000/Box
MC14027BD
SOIC16
2400/Box
MC14027BDR2
SOIC16
2500/Tape & Reel
MC14027BF
SOEIAJ16
See Note 1.
MC14027BFEL
SOEIAJ16
See Note 1.

March, 2000 Rev. 3
109

MC14027B/D
MC14027B
TRUTH TABLE
Inputs
C
Outputs*
Qn
Qn+1
Qn+1
Qo
Qo
Qo
Qn
Qn
X = Dont Care
= Level Change
= Present State
* = Next State
PIN ASSIGNMENT
QA
16
VDD
QA
15
QB
CA
14
QB
RA
13
CB
KA
12
RB
JA
11
KB
SA
10
JB
VSS
SB
BLOCK DIAGRAM
7
6
15
14
4
9
10
13
11
12
VDD = PIN 16
VSS = PIN 8
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110
No
Change
MC14027B

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc
IT
5.0
10
15

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
Vdc
mAdc

http://onsemi.com
111
Adc
MC14027B

Characteristic
Symbol

tTLH,
tTHL
Propagation Delay Times**

Clock to Q, Q
tPLH,
tPHL
VDD
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
175
75
50
350
150
100
Set to Q, Q
5.0
10
15
175
75
50
350
150
100
Reset to Q, Q
5.0
10
15
350
100
75
450
200
150
Setup Times
tsu
5.0
10
15
140
50
35
70
25
17
ns
Hold Times
th
5.0
10
15
140
50
35
70
25
17
ns
tWH, tWL
5.0
10
15
330
110
75
165
55
38
ns
fcl
5.0
10
15
3.0
9.0
13
1.5
4.5
6.5
MHz
tTLH, tTHL
5.0
10
15
15
5.0
4.0
Set
5
10
15
90
45
35
10
5
3
Reset
5
10
15
50
25
20
30
15
10
5.0
10
15
250
100
70
125
50
35
Clock Pulse Width
Removal Times
Set and Reset Pulse Width
trem
tWH
ns
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112
ns
MC14027B
20 ns
20 ns
VDD
90%
50%
10%
20 ns
K
90%
50%
10%
tsu
tsu
20 ns
th
90%
50%
10%
VSS
20 ns
VDD
VSS
20 ns
VDD
VSS
20 ns
90%
SET OR
RESET
tw
tWL
tWH
1
fcl
tPLH
tPHL
VOH
90%
50%
10%
CLOCK
VDD
50%
10%
50%
Q or Q
20 ns
10%
tw
tPLH
tPHL
Inputs R and S low.

For the measurement of tWH, I/fcl, and PD
the Inputs J and K are kept high.
VSS
trem
20 ns
90%
VOL
tTHL
tTLH
20 ns
VSS
VOH
50%
VOL

(J, K, Clock, and Output)

(Set, Reset, Clock, and Output)
LOGIC DIAGRAM
S
Q
C
J
C
C
C
K
R
Q
C
C
VDD
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113
MC14028B
BCD-To-Decimal Decoder
Binary-To-Octal Decoder
The MC14028B decoder is constructed so that an 8421 BCD code
on the four inputs provides a decimal (oneoften) decoded output,
while a 3bit binary input provides a decoded octal (oneofeight)
code output with D forced to a logic 0. Expanded decoding such as
binarytohexadecimal (oneof16), etc., can be achieved by using
other MC14028B devices. The part is useful for code conversion,
address decoding, memory selection control, demultiplexing, or
readout decoding.
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MARKING
DIAGRAMS
16

PDIP16
P SUFFIX
CASE 648
MC14028BCP
AWLYYWW
1

Positive Logic Design
Low Outputs on All Illegal Input Combinations
Similar to CD4028B.
16
SOIC16
D SUFFIX
CASE 751B
14028B
AWLYWW
1

Symbol
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
VDD
Vin, Vout
Iin, Iout
Parameter
16

(DC or Transient)
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
114
MC14028B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
may occur.
SOEIAJ16
F SUFFIX
CASE 966
Package
Shipping
MC14028BCP
PDIP16
2000/Box
MC14028BD
SOIC16
2400/Box
MC14028BDR2
SOIC16
2500/Tape & Reel
MC14028BF
SOEIAJ16
See Note 1.
MC14028BFEL
SOEIAJ16
See Note 1.


MC14028B/D
MC14028B
PIN ASSIGNMENT
Q4
16
VDD
Q2
15
Q3
Q0
14
Q1
Q7
13
Q9
12
Q5
11
Q6
10
VSS
Q8
TRUTH TABLE
D C B A Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BLOCK DIAGRAM
8421
BCD
INPUTS
3BIT
BINARY
INPUTS
10
13
12
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
VDD = PIN 16
VSS = PIN 8
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115
3
14
2
15
1
6
7
4
9
5
OCTAL
DECODED
OUTPUTS
DECIMAL
DECODED
OUTPUTS
MC14028B
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
VOL
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
VOH
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
IOL
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
0 Level
1 Level
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
Vdc
1 Level
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
mAdc
Source
IOH
Sink

Per Package)
buffers switching)

Adc

Characteristic
Symbol

tTLH,
tTHL

tPLH,
tPHL
VDD
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
300
130
90
600
260
180
ns
ns
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116
Unit
MC14028B
20 ns
Inputs B, C, and D
switching in respect
to a BCD code.
20 ns
All outputs connected

to respective CL loads.
f in respect to a system
clock.
VDD
90%
INPUT A
50%
10%
VSS
1/f
20 ns
20 ns
VDD
90%
INPUT C
50%
10%
Inputs A, B, and D low.
VSS
tPLH
tPHL
VOH
90%
Q4
50%
10%
VOL
tTLH
tTHL
LOGIC DIAGRAM
Q0
Q1
A
Q2
Q3
B
Q4
Q5
C
Q6
Q7
Q8
Q9
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117
MC14028B
INPUTS
D
Expanded decoding can be performed by using the

MC14028B and other CMOS Integrated Circuits. The
circuit in Figure 2 converts any 4bit code to a decimal or
hexadecimal code. The accompanying table shows the input
binary combinations, the associated output numbers that
go high when selected, and the redefined output
numbers needed for the proper code. For example: For the
combination DCBA = 0111 the output number 7 is redefined
for the 4bit binary, 4bit gray, excess3, or excess3 gray
codes as 7, 5, 4, or 2, respectively. Figure 3 shows a 6bit
binary 1of64 decoder using nine MC14028B circuits and
two MC14069UB inverters.
The MC14028B can be used in decimal digit displays,
such as, neon readouts or incandescent projection indicators
as shown in Figure 4.
MC14028B
Q9
MC14028B
Q0
15
Q9
Q0
15
OUTPUT NUMBERS
Figure 2. Code Conversion Circuit and Truth Table
Code and Redefined

Output Numbers
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
1
2
3
0
1
3
2
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
5
6
7
7
6
4
5
1
2
3
4
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
9
10
11
15
14
12
13
5
6
7
8
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
12
13
14
15
8
9
11
10
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118
4221
Aiken
Decimal
Excess3
Gray
Output Numbers
Excess3
Inputs
4Bit
Binary
4Bit
Gray
Hexadecimal
0
3
0
1
2
3
0
1
2
4
3
4
1
2
5
6
9
5
5
6
8
7
6
7
8
9
7
8
9
MC14028B
INPUTS
A
INHIBIT
C
MC14028B
Q0
(NO SELECTION)
Q9
A B C D A B C D
A B C D A B C D A B C D A B C D A B C D
A B C D
MC14028B
MC14028B
MC14028B
MC14028B
MC14028B
MC14028B
MC14028B
MC14028B
Q0
Q9 Q0
Q9 Q0
Q9 Q0
Q9 Q0
Q9 Q0
Q9 Q0
Q9 Q0
Q9
0
*1/6 MC14069UB
15
16
23
24
31
32
39
40
47
48
55
56
63
64 OUTPUTS (SELECTED OUTPUT IS HIGH)
Figure 3. SixBit Binary 1of64 Decoder
A
B
MC14028B
C
D
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
APPROPRIATE
VOLTAGE
APPROPRIATE
VOLTAGE
INCANDESCENT
DISPLAY
NEON
DISPLAY
OR
0
Figure 4. Decimal Digit Display Application
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119
MC14029B
Binary/Decade Up/Down
Counter
The MC14029B Binary/Decade up/down counter is constructed
with MOS Pchannel and Nchannel enhancement mode devices in a
single monolithic structure. The counter consists of type D flipflop
stages with a gating structure to provide toggle flipflop capability.
The counter can be used in either Binary or BCD operation. This
complementary MOS counter finds primary use in up/down and
difference counting and frequency synthesizer applications where low
power dissipation and/or high noise immunity is desired. It is also
useful in A/D and D/A conversion and for magnitude and sign
generation.
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648

Internally Synchronous for High Speed
Logic EdgeClocked Design Count Occurs on Positive Going
Edge of Clock
Asynchronous Preset Enable Operation
Pin for Pin Replacement for CD4029B
MC14029BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14029B
AWLYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966

Symbol
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
VDD
Vin, Vout
Iin, Iout
Parameter
(DC or Transient)
may occur.
to the range VSS
(Vin or Vout)
VDD.
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14029BCP
PDIP16
2000/Box
MC14029BD
SOIC16
2400/Box
MC14029BDR2
SOIC16
2500/Tape & Reel
MC14029BF
SOEIAJ16
See Note 1.
MC14029BFEL
SOEIAJ16
See Note 1.

March, 2000 Rev. 3
MC14029B
AWLYWW
120

MC14029B/D
MC14029B
PIN ASSIGNMENT
TRUTH TABLE
PE
16
VDD
Q3
15
CLK
P3
14
Q2
P0
13
P2
Cin
12
P1
Carry In
Up/Down
Preset
Enable
No Count
Count Up
Count Down
Q0
11
Q1
Preset
Cout
10
U/D
VSS
B/D
Action
X = Dont Care

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
VDD
Vdc
Min
Max
Min
Typ
(4.)
125_C
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

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121
Adc
MC14029B
All Types
Characteristic
Symbol

tTLH,
tTHL

Clk to Q
tPLH,
tPHL
Clk to Cout
tPLH,
tPHL
Cin to Cout
tPLH,
tPHL
PE to Q
tPLH,
tPHL
PE to Cout
tPLH, tPHL = (1. 7 ns/pF) CL + 465 ns
tPLH,
tPHL
VDD
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
200
100
90
400
200
180
5.0
10
15
250
130
85
500
260
190
5.0
10
15
175
50
50
360
120
100
5.0
10
15
235
100
80
470
200
160
5.0
10
15
320
145
105
640
290
210
tW(cl)
5.0
10
15
180
80
60
90
40
30
ns
fcl
5.0
10
15
4.0
8.0
10
2.0
4.0
5.0
MHz
Preset Removal Time

The Preset Signal must be low prior to a positivegoing
transition of the clock.
trem
5.0
10
15
160
80
60
80
40
30
ns
tr(cl)
tf(cl)
5.0
10
15
15
5
4
Carry In Setup Time
tsu
5.0
10
15
150
60
40
75
30
20
ns
Up/Down Setup Time
5.0
10
15
340
140
100
170
70
50
ns
Binary/Decade Setup Time
5.0
10
15
320
140
100
160
70
50
ns
5.0
10
15
130
70
50
65
35
25
ns
Clock Pulse Width
Preset Enable Pulse Width
tW
ns
ns
ns
ns
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122
MC14029B
VDD
PE
Cin
B/D
U/D
CLK
P0
P1
P2
P3
PULSE
GENERATOR
0.01 F
CERAMIC
ID
500 pF
Q0
Q1
Q2
CL
CL
Q3
CL
Cout
CL
CL
20 ns
20 ns
90%
50%
CLK
10%
VARIABLE
WIDTH
VDD
VSS
VDD
PE
Cin
B/D
U/D
CLK
P0
P1
P2
P3
PROGRAMMABLE
PULSE
GENERATOR
Q0
Q1
Q2
CL
CL
Q3
CL
Cout
CL
CL
VSS
tW
tsu
CARRY IN OR
UP/DOWN
OR BINARY/DECADE
trem
1/fcl
VDD
50%
CLOCK
VSS
VDD
50%
VSS
VDD
tW
PRESET ENABLE
20 ns
Cout ONLY
90%
10%
Q0 OR CARRY OUT
10%
VSS
tTLH
90%
VOL
tPLH
tTHL
tPHL
tPLH
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123
VOH
MC14029B
TIMING DIAGRAM
CLOCK
CARRY IN
UP/DOWN
BINARY/DECADE
PE
P0
P1
P2
P3
Q0
Q1
Q2
Q3
CARRY OUT
COUNT 0
Q3 Q2 Q1 Q0
Cout
Cin
MC14029B
U/D
MSD
PE
B/D
P3 P2 P1 P0 CLK
Q3 Q2 Q1 Q0
Cout
Cin
MC14029B
U/D
PE
B/D
P3 P2 P1 P0 CLK
VDD
Q3 Q2 Q1 Q0
Cout
Cin
MC14029B
U/D
LSD
PE
B/D
P3 P2 P1 P0 CLK
VDD
VDD VDD
INPUT
CLOCK
CLOCK
Cout 1 (LSD)
Cout 2
Cout 3 (MSD)
*tW
122
123
10
11
99
100
101
119
120
121
122
COUNT
123
PE
^ 900 ns @ VDD = 5 V
Figure 3. Divide by N BCD Down Counter and Timing Diagram

(Shown for N = 123)
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124
OUTPUT
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125
CLOCK
UP/DOWN
CARRY IN
PRESET ENABLE
BINARY/DECADE
15
10
P0
Q0
CLK Q1
CLK Q0
P1
TE Q1
PE P1
12
TE Q0
PE P0
Q1
P2
14
CLK Q2
TE Q2
PE P2
13
Q2
P3
CLK Q3
TE Q3
PE P3
Q3
CARRY OUT
MC14029B
LOGIC DIAGRAM
MC14040B
12-Bit Binary Counter
The MC14040B 12stage binary counter is constructed with MOS
monolithic structure. This part is designed with an input wave shaping
circuit and 12 stages of ripplecarry binary counter. The device
advances the count on the negativegoing edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequencydriving circuits.
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MARKING
DIAGRAMS

Common Reset Line
16
PDIP16
P SUFFIX
CASE 648
MC14040BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14040B
AWLYWW
1

Symbol
VDD
Vin, Vout
Parameter
(DC or Transient)
16
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5
10
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
16
mA
may occur.
to the range VSS
(Vin or Vout)
VDD.
14
040B
ALYW
1

Iin, Iout
TSSOP16
DT SUFFIX
CASE 948F
SOEIAJ16
F SUFFIX
CASE 966
MC14040B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14040BCP
PDIP16
2000/Box
MC14040BD
SOIC16
2400/Box
MC14040BDR2
SOIC16
2500/Tape & Reel
MC14040BDT
TSSOP16
96/Rail
MC14040BF
SOEIAJ16
See Note 1.
MC14040BFEL
SOEIAJ16
See Note 1.

March, 2000 Rev. 3
126

MC14040B/D
MC14040B
PIN ASSIGNMENT
Q12
16
VDD
Q6
15
Q11
Q5
14
Q10
Q7
13
Q8
Q4
12
Q9
Q3
11
Q2
10
VSS
Q1
TRUTH TABLE
Clock
Reset
Output State
0
0
1
No Change
Advance to next state
All Outputs are low
X = Dont Care
LOGIC DIAGRAM
Q1
Q2
9
CLOCK
10
C
C
Q3
6
RESET
11
Q4 = PIN 5
Q5 = PIN 3
Q6 = PIN 2
Q7 = PIN 4
Q8 = PIN 13
Q9 = PIN 12
http://onsemi.com
127
Q10
14
VDD = PIN 16
VSS = PIN 8
Q11
15
Q12
1
MC14040B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

http://onsemi.com
128
Adc
MC14040B
VDD
Characteristic
Symbol

TTLH, TTHL = (1.5 ns/pF) CL + 25 ns
TTLH, TTHL = (0.75 ns/pF) CL + 12.5 ns
TTLH, TTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL

Clock to Q1
tPLH,
tPHL
Clock to Q12
Vdc
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
260
115
80
520
230
160
5.0
10
15
1625
720
500
3250
1440
1000
Unit
ns
ns
ns

Reset to Qn
tPHL = (0.86 ns/pF) CL + 182 ns
tPHL
Clock Pulse Width
ns
5.0
10
15
370
155
115
740
310
230
tWH
5.0
10
15
385
150
115
140
55
38
ns
fcl
5.0
10
15
2.1
7.0
10.0
1.5
3.5
4.5
MHz
tTLH, tTHL
5.0
10
15
ns
No Limit
Reset Pulse Width
tWH
5.0
10
15
960
360
270
320
120
80
ns
Reset Removal Time
trem
5.0
10
15
130
50
30
65
25
15
ns
VDD
VDD
500 F
0.01 F
CERAMIC
ID
PULSE
GENERATOR
C Q1
Q2
Q
R n
C Q1
Q2
Q
R n
CL
CL
VSS
CL
CL
CL
VSS
20 ns
CLOCK
PULSE
GENERATOR
90%
50%
10%
CL
CLOCK
20 ns
20 ns
20 ns
tPLH
VDD
90%
50%
10%
tWH
tPHL
50% DUTY CYCLE
90%
50%
10%
tTLH

and Waveform

and Waveforms
VSS
http://onsemi.com
129
tTHL
MC14040B
1
16
32
64
128
256
512
1024
2048
4096
CLOCK
RESET
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
TIMEBASE GENERATOR
outputs Q5, Q10, Q11, and Q12 division by 3600 is

accomplished. The MC14012B decodes the counter
outputs, produces a single output pulse, and resets the binary
counter. The resulting output frequency is 1.0 pulse/minute.
A 60 Hz sinewave obtained through a 1.0 Megohm

resistor connected directly to a standard 120 Vac power line
is applied to the clock input of the MC14040B. By selecting
VDD
1.0 M
MC14040B
Q5
C
20 pF
Q10
120 Vac
60 Hz
1/2
MC14012B
Q11
R
Q12
VSS
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130
1/2
MC14012B
1.0 PULSE/MINUTE
OUTPUT
MC14042B
Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS
monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity
input. Information present at the data input is transferred to outputs Q
and Q during the clock level which is determined by the polarity input.
When the polarity input is in the logic 0 state, data is transferred
during the low clock level, and when the polarity input is in the logic
1 state the transfer occurs during the high clock level.
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
Buffered Data Inputs

Common Clock
Clock Polarity Control
Q and Q Outputs
Supply Voltage Range = 3.0 Vdc to 1 8 Vdc
MC14042BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14042B
AWLYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966

Symbol
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
VDD
Vin, Vout
Iin, Iout
Parameter
(DC or Transient)
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
may occur.
MC14042B
AWLYWW
131
Device
Package
Shipping
MC14042BCP
PDIP16
2000/Box
MC14042BD
SOIC16
2400/Box
MC14042BDR2
SOIC16
2500/Tape & Reel
MC14042BF
SOEIAJ16
See Note 1.
MC14042BFEL
SOEIAJ16
See Note 1.
MC14042BFR1
SOEIAJ16
See Note 1.
MC14042BFR2
SOEIAJ16
See Note 1.


MC14042B/D
MC14042B
PIN ASSIGNMENT
Q3
16
VDD
Q0
15
Q3
Q0
14
D3
D0
13
D2
CLOCK
12
Q2
POLARITY
11
Q2
D1
10
Q1
VSS
Q1
TRUTH TABLE
Clock
Polarity
0
1
1
0
0
0
1
1
Data
Latch
Data
Latch
LOGIC DIAGRAM
5
D0
LATCH
1
CLOCK
POLARITY
Q0
2
Q0
3
6
D1
LATCH
2
Q1
10
Q1
9
D2
LATCH
3
13
VDD = PIN 16
VSS = PIN 8
Q2
11
Q2
12
D3
LATCH
4
14
Q3
1
Q3
15
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132
MC14042B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
(CL = 50 pF on all outputs all
buffers switching)
mAdc

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133
Adc
MC14042B

Characteristic
Symbol

tTLH,
tTHL
Propagation Delay Time, D to Q, Q

tPLH,
tPHL
Propagation Delay Time, Clock to Q, Q

tPLH,
tPHL
Clock Pulse Width
tWH
tTLH,
tTHL
Hold Time
VDD
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
220
90
60
440
180
120
5.0
10
15
220
90
60
440
180
120
5.0
10
15
300
100
80
150
50
40
5.0
10
15
15
5.0
4.0
5.0
10
15
100
50
40
50
25
20
5.0
10
15
50
30
25
0
0
0
ns
no
ns
ns
th
Setup Time
ns
tsu
ns
VDD
1
f
16
20 ns
5
6
PULSE
GENERATOR 1
4
7
13
CLOCK
POLARITY
D0
D1
D2
14
D3
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
20 ns
90%
50%
2
3
10
9
11
12
1
15
DATA INPUT
tPLH
90%
Q OUTPUT
50%
10%
tTLH
Q OUTPUT
VSS
Figure 1. AC and Power Dissipation Test Circuit and Timing Diagram

(Data to Output)
134
tTHL
tPHL
90%
tTHL
http://onsemi.com
10%
tPHL
10%
For Power Dissipation test, each output
is loaded with capacitance CL.
Unit
50%
tTLH
MC14042B
VDD
16
PULSE
GENERATOR 1
PULSE
GENERATOR 2
7
13
14
NOTE: CL connected to output under test.
20* ns
CLOCK
POLARITY
D0
D1
D2
D3
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
2
3
10
9
11
12
1
15
VSS
20 ns
90%
50%
CLOCK INPUT
P.G. 1
10%
tWH
20 ns
90%
50%
DATA INPUT
P.G. 2
tsu
th
tPLH
Q OUTPUT
90%
50%
10%
*Input clock rise time is 20 ns except for maximum rise time test.
Figure 2. AC Test Circuit and Timing Diagram

(Clock to Output)
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135
MC14043B, MC14044B
CMOS MSI
Quad RS Latches
The MC14043B and MC14044B quad RS latches are constructed
with MOS Pchannel and Nchannel enhancement mode devices in a
single monolithic structure. Each latch has an independent Q output
and set and reset inputs. The Q outputs are gated through threestate
buffers having a common enable input. The outputs are enabled with a
logical 1 or high on the enable input; a logical 0 or low
disconnects the latch from the Q outputs, resulting in an open circuit at
the Q outputs.
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648

ThreeState Outputs with Common Enable
Outputs Capable of Driving Two Lowpower TTL Loads or One
MC140XXBCP
AWLYYWW
1
16
LowPower Schottky TTL Load Over the Rated Temperature Range

SOIC16
D SUFFIX
CASE 751B
140XXB
AWLYWW
1
16

Parameter
Symbol
VDD
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Vin, Vout
Iin, Iout
Value

(DC or Transient)
may occur.
to the range VSS
(Vin or Vout)
VDD.
SOEIAJ16
F SUFFIX
CASE 966
MC140XXB
AWLYWW
1
XX
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14043BCP
PDIP16
2000/Box
MC14043BD
SOIC16
2400/Box
MC14043BDR2
SOIC16
2500/Tape & Reel
MC14043BF
SOEIAJ16
See Note 1.
MC14043BFEL
SOEIAJ16
See Note 1.
MC14044BCP
PDIP16
2000/Box
MC14044BD
SOIC16
2400/Box
MC14044BDR2
SOIC16
2500/Tape & Reel

March, 2000 Rev. 3
136

MC14043B/D
MC14043B, MC14044B
PIN ASSIGNMENT
MC14043B
MC14044B
Q3
16
VDD
Q3
16
VDD
Q0
15
R3
NC
15
S3
R0
14
S3
S0
14
R3
S0
13
NC
R0
13
Q0
12
S2
12
R2
S1
11
R2
R1
11
S2
R1
10
Q2
S1
10
Q2
VSS
Q1
VSS
Q1
NC = NO CONNECTION
MC14043B
S0
R0
S1
R1
S2
R2
S3
MC14044B
2
R0
Q0
3
S0
6
R1
Q1
7
12
VDD = PIN 16
VSS = PIN 8
NC = PIN 13
10
S1
R2
Q2
11
S2
14
TRUTH TABLE
1
Q3
S R E
X X 0
High
Impedance
15
R3
5
ENABLE
0
0
1
1
0
1
0
1
R3
13
Q0
3
6
Q1
7
12
VDD = PIN 16
VSS = PIN 8
NC = PIN 2
10
Q2
11
14
TRUTH TABLE
1
Q3
S R E
X X 0
High
Impedance
15
S3
1 No Change
1
0
1
1
1
1
5
ENABLE
X = Dont Care
0
0
1
1
0
1
0
1
1
0
1
1
1
0
1 No Change
X = Dont Care
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137
MC14043B, MC14044B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc

Per Package)
(CL = 50 pF on all outputs all
buffers switching)
IT
5.0
10
15
ThreeState Output Leakage

Current
ITL
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
0.1
Adc
3.0
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138
Adc
MC14043B, MC14044B

Characteristic
Symbol
VDD
Vdc
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
100
50
40
200
100
80
5.0
10
15
175
75
60
350
175
120
Unit
Output Rise Time

tTLH = (1.35 ns/pF) CL + 32.5 ns
tTLH
Output Fall Time

tTHL = (1.35 ns/pF) CL + 32.5 ns
tTHL

tPLH = (0.90 ns/pF) CL + 130 ns
tPLH
tPHL = (0.90 ns/pF) CL + 130 ns

tPHL
5.0
10
15
175
75
60
350
175
120
ns
Set, Set Pulse Width
tW
5.0
10
15
200
100
70
80
40
30
ns
Reset, Reset Pulse Width
tW
5.0
10
15
200
100
70
80
40
30
ns
tPLZ,
tPHZ,
tPZL,
tPZH
5.0
10
15
150
80
55
300
160
110
ns
ThreeState Enable/Disable Delay
ns
ns
ns
AC WAVEFORMS
MC14043B
MC14044B
20 ns
50%
10%
VSS
20 ns
RESET
SET
20 ns
50%
tPHL
VDD
90%
10%
VSS
20 ns
90% VDD
VDD
10%
10%
50%
20 ns
90%
tTHL
20 ns
VDD
90%
SET
20 ns
20 ns
VSS
50%
RESET
tTLH
tTHL
tTLH
VOH
90%
50%
10%
50%
VOL
90%
10%
tPLH
tPLH
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139
tPHL
VSS
VOH
VOL
MC14043B, MC14044B
THREESTATE ENABLE/DISABLE DELAYS
Set, Reset, Enable, and Switch Conditions for 3State Tests
MC14043B
Test
Enable
VDD
MC14044B
S1
S2
tPZH
Open
Closed
VDD
VSS
VSS
VDD
tPZL
Closed
Open
VSS
VDD
VDD
VSS
tPHZ
Open
Closed
VDD
VSS
VSS
VDD
tPLZ
Closed
Open
VSS
VDD
VDD
VSS
S1
TO
OUTPUT
UNDER
TEST
1k
CL
50 pF
S2
VSS
VDD
ENABLE
50%
VSS
tPZH
VDD
90%
QA
10%
tPZL
tPHZ
VOL
tPLZ
VOH
QB
10%
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140
VSS
MC14046B
Phase Locked Loop
The MC14046B phase locked loop contains two phase comparators,
a voltagecontrolled oscillator (VCO), source follower, and zener
diode. The comparators have two common signal inputs, PCAin and
PCBin. Input PCAin can be used directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to small voltage
signals. The selfbias circuit adjusts small voltage signals in the linear
region of the amplifier. Phase comparator 1 (an exclusive OR gate)
provides a digital error signal PC1out, and maintains 90 phase shift at
the center frequency between PCAin and PCBin signals (both at 50%
duty cycle). Phase comparator 2 (with leading edge sensing logic)
provides digital error signals, PC2out and LD, and maintains a 0
phase shift between PCA in and PCBin signals (duty cycle is
immaterial). The linear VCO produces an output signal VCOout
whose frequency is determined by the voltage of input VCOin and the
capacitor and resistors connected to pins C1A, C1B, R1, and R2. The
sourcefollower output SFout with an external resistor is used where
the VCOin signal is needed but no loading can be tolerated. The inhibit
input Inh, when high, disables the VCO and source follower to
minimize standby power consumption. The zener diode can be used to
assist in power supply regulation.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltagetofrequency conversion and motor speed control.
Buffered Outputs Compatible with MHTL and LowPower TTL

Supply Voltage Range = 3.0 to 18 V
Phase Comparator 1 is an Exclusive Or Gate and is Duty Cycle Limited
Phase Comparator 2 switches on Rising Edges and is not Duty Cycle
Limited

Parameter
Symbol
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5
VDD
Vin
Input Voltage Range (All Inputs)
Iin
DC Input Current, per Pin
10
mA
PD
Power Dissipation,
500
mW
TA
Operating Temperature Range
55 to +125
Tstg
65 to +150
may occur.
March, 2000 Rev. 5
141
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MC14046BCP
AWLYYWW
1
16
14046B
SOIC16
DW SUFFIX
CASE 751G
AWLYYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966
MC14046B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14046BCP
PDIP16
2000/Box
MC14046BDW
SOIC16
2350/Box
MC14046BDWR2
SOIC16
1000/Tape & Reel
MC14046BF
SOEIAJ16
See Note 1.
MC14046BFEL
SOEIAJ16
See Note 1.

This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this highimpedance circuit. For proper
operation, Vin and Vout should be constrained to the
range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

MC14046B/D
MC14046B
PIN ASSIGNMENT
BLOCK DIAGRAM
SELF BIAS
CIRCUIT
PCAin 14
PCBin 3
PHASE
COMPARATOR 1
2 PC1out
PHASE
COMPARATOR 2
13 PC2out
1 LD
4
11
12
6
7
VOLTAGE
CONTROLLED
OSCILLATOR
(VCO)
VCOin 9
VDD = PIN 16
VSS = PIN 8
SOURCE FOLLOWER
INH 5
VCOout
R1
R2
C1A
C1B
LD
16
VDD
PC1out
15
ZENER
PCBin
14
PCAin
VCOout
13
PC2out
INH
12
R2
C1A
11
R1
C1B
10
SFout
VSS
VCOin
10 SFout
15 ZENER
VSS
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage (4.)

(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
0 Level
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
1 Level
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Iin
15
0.1
0.00001
0.1
1.0
Adc
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
Vin = 0 or VDD
Vdc
VIH
IOH

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
mAdc
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Input Current
Vdc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
(Per Package) Inh = PCAin = VDD,
Zener = VCOin = 0 V, PCBin = VDD
or 0 V, Iout = 0 A
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
Total Supply Current (5.)

(Inh = 0, fo = 10 kHz, CL = 50 pF,
R1 = 1.0 M, R2 =
RSF = ,
and 50% Duty Cycle)
IT
5.0
10
15

4. Noise immunity specified for worstcase input combination.

Noise Margin for both 1 and 0 level = 1.0 Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
5. To Calculate Total Current in General:
VCOin 1.65
VDD 1.35 3/4
VCOin 1.65 3/4
2.2 x VDD
+
+ 1.6 x
+ 1 x 103 (CL + 9) VDD f +
IT
R1
R2
RSF
1 x 101 VDD2
100% Duty Cycle of PCAin

100
+ IQ
where: IT in A, CL in pF, VCOin, VDD in Vdc, f in kHz, and

R1, R2, RSF in M, CL on VCOout.
http://onsemi.com
142
mAdc
MC14046B
ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25C)

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL
VDD
Vdc
Minimum
Maximum
Device
Typical
Device
5.0
10
15
180
90
65
350
150
110
5.0
10
15
100
50
37
175
75
55
Units
ns
ns
PHASE COMPARATORS 1 and 2

Input Resistance PCAin
Rin
5.0
10
15
1.0
0.2
0.1
2.0
0.4
0.2
PCBin
Rin
15
150
1500
Minimum Input Sensitivity

AC Coupled PCAin
C series = 1000 pF, f = 50 kHz
Vin
5.0
10
15
200
400
700
300
600
1050
mV pp
DC Coupled PCAin, PCBin
5 to 15
fmax
5.0
10
15
0.5
1.0
1.4
0.7
1.4
1.9
MHz
Temperature Frequency Stability

(R2 = )
5.0
10
15
0.12
0.04
0.015
%/_C
Linearity (R2 = )
(VCOin = 2.5 V 0.3 V, R1 > 10 k)
(VCOin = 5.0 V 2.5 V, R1 > 400 k)
(VCOin = 7.5 V 5.0 V, R1 1000 k)
5.0
10
15
1.0
1.0
1.0
See Noise Immunity
VOLTAGE CONTROLLED OSCILLATOR (VCO)

Maximum Frequency
(VCOin = VDD, C1 = 50 pF
R1 = 5.0 k, and R2 = )
Output Duty Cycle
5 to 15
50
Input Resistance VCOin
Rin
15
150
1500
Offset Voltage
(VCOin minus SFout, RSF > 500 k)
5.0
10
15
1.65
1.65
1.65
2.2
2.2
2.2
Linearity
(VCOin = 2.5 V 0.3 V, RSF > 50 k)
(VCOin = 5.0 V 2.5 V, RSF > 50 k)
(VCOin = 7.5 V 5.0 V, RSF > 50 k)
5.0
10
15
0.1
0.6
0.8
SOURCEFOLLOWER
ZENER DIODE
Zener Voltage (Iz = 50 A)
VZ
6.7
7.0
7.3
Dynamic Resistance (Iz = 1.0 mA)
RZ
100
6. The formula given is for the typical characteristics only.
http://onsemi.com
143
MC14046B
PHASE COMPARATOR 1
Input Stage
00
01
11
10
X X
PCAin
PCBin
PC1out
PHASE COMPARATOR 2
Input Stage
X X
PCAin
00
01
PCBin
00
10
10
00
01
01
10
11
11
11
PC2out
3State
Output Disconnected
LD (Lock Detect)
Refer to Waveforms in Figure 3.
Figure 1. Phase Comparators State Diagrams
v v
v v
v v
Characteristic
Using Phase Comparator 1
Using Phase Comparator 2
No signal on input PCAin.
VCO in PLL system adjusts to center

frequency (f0).
VCO in PLL system adjusts to minimum

frequency (fmin).
Phase angle between PCAin and PCBin.
90 at center frequency (f0), approaching

0_ and 180 at ends of lock range (2fL)
Always 0_ in lock (positive rising edges).
Locks on harmonics of center frequency.
Yes
No
Signal input noise rejection.
High
Low
Lock frequency range (2fL).
The frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2fL = full VCO frequency range = fmax fmin.
Capture frequency range (2fC).
The frequency range of the input signal on which the loop will lock if it was initially
out of lock.
Depends on lowpass filter characteristics
(see Figure 3). fC
fL
Center frequency (f0).
VCO output frequency (f).
Note: These equations are intended to be

a design guide. Since calculated component
values may be in error by as much as a
factor of 4, laboratory experimentation may
be required for fixed designs. Part to part
frequency variation with identical passive
components is typically less than 20%.
The frequency of VCOout, when VCOin = 1/2 VDD

fmin =
fmax =
(VCO input = VSS)
R2(C1 + 32 pF)
1
R1(C1 + 32 pF)
+ fmin
Where: 10K
R1
1M
1M
10K
R2
100pF
C1
.01 F
Figure 2. Design Information
http://onsemi.com
144
(VCO input = VDD)
fC = fL
MC14046B
9
SOURCE
FOLLOWER
VCOin
PCAin
@ FREQUENCY f
14
3
PCBin
2 OR 13
PHASE
COMPARATOR PC1out
OR
PC2out
EXTERNAL
LOWPASS
FILTER
SFout
10
RSF
9
11
12
7
CIA
R1
VCOout
@ FREQUENCY Nf = f
VCO
6
CIB
R2
CI
EXTERNAL
N
COUNTER
Typical LowPass Filters

(a)
INPUT
R3
OUTPUT
C2
2fC
[p
1
(a)
INPUT
2 p fL
R3 C2
Typically:
R3
OUTPUT
R4 C2
R4
(R3
C2
6N
+ fmax
pD
Df
) 3, 000W) C2 + 100N
fmax2
R4 C2
f = fmax fmin
NOTE: Sometimes R3 is split into two series resistors each R3 2. A capacitor CC is then placed from the midpoint to ground. The value for
CC should be such that the corner frequency of this network does not significantly affect n. In Figure B, the ratio of R3 to R4 sets the
damping, R4
(0.1)(R3) for optimum results.
LOWPASS FILTER
Filter A
Definitions: N = Total division ratio in feedback loop
K = VDD/ for Phase Comparator 1
K = VDD/4 for Phase Comparator 2
2 p D fVCO
KVCO
VDD 2 V
2 p fr
for a typical design n
(at phase detector input)
10
0.707
wn +
KfKVCO
NR3C2
z + 2K NKwn
f VCO
F(s)
+ R3C21S ) 1
wn +
Filter B
KfKVCO
NC2(R3 R4)
z + 0.5 wn
) KfKNVCO)
R3C2S ) 1
F(s) +
S(R3C2 ) R4C2) ) 1
(R3C2
Waveforms
Phase Comparator 1
PCAin
Phase Comparator 2
VDD
PCAin
VSS
VOH
PCBin
PC1out
VCOin
VDD
VSS
VOH
PCBin
VOL
VOH
LD
VOL
VOH
PC2out
VOL
VCOin
VOL
VOH
VOL
VOH
VOL
VOH
VOL
Note: for further information, see:

(1) F. Gardner, PhaseLock Techniques, John Wiley and Son, New York, 1966.
(2) G. S. Moschytz, Miniature RC Filters Using PhaseLocked Loop, BSTJ, May, 1965.
(3) Garth Nash, PhaseLock Loop Design Fundamentals, AN535, Motorola Inc.
(4) A. B. Przedpelski, PhaseLocked Loop Design Articles, AR254, reprinted by Motorola Inc.
Figure 3. General PhaseLocked Loop Connections and Waveforms
http://onsemi.com
145
MC14049B, MC14050B
Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting
Hex Buffer are constructed with MOS PChannel and NChannel
enhancement mode devices in a single monolithic structure. These
complementary MOS devices find primary use where low power
dissipation and/or high noise immunity is desired. These devices
provide logic level conversion using only one supply voltage, VDD.
The inputsignal high level (VIH) can exceed the VDD supply
voltage for logic level conversions. Two TTL/DTL loads can be driven
when the devices are used as a CMOStoTTL/DTL converter (VDD
= 5.0 V, VOL 0.4 V, IOL 3.2 mA).
Note that pins 13 and 16 are not connected internally on these
devices; consequently connections to these terminals will not affect
circuit operation.
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
1
16
SOIC16
D SUFFIX
CASE 751B
High Source and Sink Currents

HightoLow Level Converter
Supply Voltage Range = 3.0 V to 18 V
VIN can exceed VDD
Meets JEDEC B Specifications
Improved ESD Protection On All Inputs
Parameter
140XXB
AWLYWW
1 16
TSSOP16
DT SUFFIX
CASE 948F

Symbol
MC140XXBCP
AWLYYWW
14
0XXB
ALYW
16
Value
Unit
VDD
0.5 to +18.0
Vin
Input Voltage Range

(DC or Transient)
0.5 to +18.0
Vout
Output Voltage Range

(DC or Transient)
0.5 to VDD + 0.5
Iin
Input Current
10
mA
Iout
Output Current
45
mA
PD
Power Dissipation,
(Plastic)
(SOIC)
SOEIAJ16
F SUFFIX
CASE 966
1
MC140XXB
AWLYWW
1
XX
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14049BCP
PDIP16
2000/Box
MC14049BD
SOIC16
2400/Box
SOIC16
2500/Tape & Reel
SOEIAJ16
See Note 1.
mW
825
740
TA
55 to +125
MC14049BDR2
Tstg
65 to +150
MC14049BF
TL
Lead Temperature
(8Second Soldering)
260
MC14050BCP
PDIP16
2000/Box
may occur.
3. Temperature Derating: See Figure 3.
MC14050BD
SOIC16
2400/Box
MC14050BDR2
SOIC16
2500/Tape & Reel
This device contains protection circuitry to protect the inputs against damage
due to high static voltages or electric fields referenced to the VSS pin only. Extra
precautions must be taken to avoid applications of any voltage higher than the
maximum rated voltages to this highimpedance circuit. For proper operation, the
ranges VSS Vin 18 V and VSS Vout VDD are recommended.
MC14050BDTEL
MC14050BF
SOEIAJ16
See Note 1.
MC14050BFEL
SOEIAJ16
See Note 1.
March, 2000 Rev. 3
146


MC14049B/D
MC14049B, MC14050B
PIN ASSIGNMENT
VDD
16
NC
OUTA
15
OUTF
INA
14
INF
OUTB
13
NC
INB
12
OUTE
OUTC
11
INE
INC
10
OUTD
VSS
IND
LOGIC DIAGRAM
MC14049B
MC14050B
10
10
11
12
11
12
14
15
14
15
NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1
NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1
http://onsemi.com
147
MC14049B, MC14050B

Characteristic
Output Voltage
Vin = VDD
Symbol
+ 25_C
+ 125_C
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
10
15
1.6
1.6
4.7
1.25
1.30
3.75
2.5
2.6
10
1.0
1.0
3.0
IOL
5.0
10
15
3.75
10
30
3.2
8.0
24
6.0
16
40
2.6
6.6
19
mAdc
Iin
15
0.1
0.00001
0.1
1.0
Adc
Vin = 0
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
55_C
VDD
Vdc
1 Level
VIH
(VO = 0.5 Vdc)

(VO = 1.0 Vdc)
(VO = 1.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
Input Current
mAdc
Cin
10
20
pF
Quiescent Current (Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc

per package)
buffers switching
IT
5.0
10
15

5. The formulas given are for the typical characteristics only at + 25_C
Where: IT is in A (per Package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency and k = 0.002.
http://onsemi.com
148
Adc
MC14049B, MC14050B
AC SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = + 25_C)

Characteristic
Symbol
Output Rise Time

tTLH = (0.25 ns/pF) CL + 37.5 ns
tTLH
Output Fall Time

tTHL

tPLH = (0.33 ns/pF) CL + 63.5 ns
tPLH = (0.19 ns/pF) CL + 30.5 ns
tPLH

tPHL = (0.05 ns/pF) CL + 12.5 ns
tPHL
VDD
Vdc
Min
Typ (8.)
Max
5.0
10
15
100
50
40
160
80
60
5.0
10
15
40
20
15
60
40
30
5.0
10
15
80
40
30
140
80
60
5.0
10
15
40
20
15
80
40
30
Unit
ns
ns
ns
ns
8. Data labeled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
MC14049B
VDD
MC14050B
VDD
1
IOH
MC14049B
VDD
1
IOL
VOH
8
VSS
1
IOL
VOL
8
VSS
VDS = VOH VDD
IOH
VOL
VSS
VOH
VSS
VDD = VOL
160
I OL, OUTPUT SINK CURRENT (mAdc)
0
I OH , OUTPUT SOURCE CURRNT (mAdc)
MC14050B
VDD
VGS = 5.0 Vdc

10
VGS = 15 Vdc
120
20
VGS = 10 Vdc
30
40
VGS = 15 Vdc
50
10
MAXIMUM CURRENT LEVEL
8.0
6.0
4.0
2.0

40
VGS = 5.0 Vdc
0
VGS = 10 Vdc
80
2.0
4.0
6.0
8.0
http://onsemi.com
149
10
PD , MAXIMUM POWER DISSIPATION (mW)

PER PACKAGE
MC14049B, MC14050B
1200
1100
1000
900
825
800
740
700
600
(P) PDIP
500
400
300
(D) SOIC
200
100
0
25
175 mW (P)
120 mW (D)
50
75
100
125
TA, AMBIENT TEMPERATURE (C)
150
175
Figure 3. Ambient Temperature Power Derating
20 ns
20 ns
INPUT
VDD
10%
#
Vin
Vout
VSS
tPLH
CL
tTHL
tPHL
10%
tTLH
http://onsemi.com
150
tTLH
tPHL
90%
50%
OUTPUT
MC14050B
# Invert on MC14049B only
VOH
90%
50%
10%
OUTPUT
MC14049B
VSS
tPLH
tPHL
1
PULSE
GENERATOR
VDD
90%
50%
VOL
VOH
VOL
tTHL
MC14049UB
Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logiclevel conversion using only one
supply voltage, VDD. The inputsignal high level (VIH) can exceed the
VDD supply voltage for logiclevel conversions. Two TTL/DTL
Loads can be driven when the device is used as CMOStoTTL/DTL
converters (VDD = 5.0 V, VOL 0.4 V, IOL 3.2 mA). Note that pins
13 and 16 are not connected internally on this device; consequently
connections to these terminals will not affect circuit operation.
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
High Source and Sink Currents

HightoLow Level Converter
Meets JEDEC UB Specifications
VIN can exceed VDD
Improved ESD Protection on All Inputs
MC14049UBCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14049U
AWLYWW
1
16

Parameter
Symbol
Value
Unit
VDD
0.5 to +18.0
Vin
Input Voltage Range

(DC or Transient)
0.5 to +18.0
Vout

(DC or Transient)
TSSOP16
DT SUFFIX
CASE 948F
1
16
0.5 to VDD +0.5
Iin
Input Current
10
mA
Iout
Output Current
+45
mA
PD
Power Dissipation,
Plastic
SOIC
SOEIAJ16
F SUFFIX
CASE 966
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
825
740
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Device
may occur.
All Packages: See Figure 4.
March, 2000 Rev. 3
151
Package
Shipping
MC14049UBCP
PDIP16
2000/Box
MC14049UBD
SOIC16
2400/Box
MC14049UBDR2
SOIC16
2500/Tape & Reel
TSSOP16
96/Rail
MC14049UBDT
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields referenced to the VSS pin, only. Extra precautions
must be taken to avoid applications of any voltage higher than the maximum rated
voltages to this highimpedance circuit. For proper operation, the ranges VSS
Vin
18 V and VSS
Vout
VDD are recommended.
MC14049U
AWLYWW
1
mW
TA
14
049U
ALYW
MC14049UBDTR2 TSSOP16 2500/Tape & Reel

MC14049UBF
SOEIAJ16
See Note 1.
MC14049UBFEL
SOEIAJ16
See Note 1.


MC14049UB/D
MC14049UB
PIN ASSIGNMENT
LOGIC DIAGRAM
MC14049UB
VDD
16
NC
OUTA
15
OUTF
INA
14
INF
OUTB
13
NC
INB
12
OUTE
OUTC
11
INE
INC
10
OUTD
VSS
10
11
12
14
15
CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN)
VDD
MC14049UB
IND
NC = NO CONNECTION
NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1
VSS

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5
5.0
10
15
1.6
1.6
4.7
1.25
1.3
3.75
2.5
2.6
10
1.0
1.0
3.0
IOL
5.0
10
15
3.75
10
30
3.2
8.0
24
6.0
16
40
2.6
6.6
19
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Cin
10
20
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
1 Level
VIH
(VO = 0.5 Vdc)

(VO = 1.0 Vdc)
(VO = 1.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

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152
Adc
MC14049UB

Characteristic
Symbol
Output Rise Time

tTLH = (0.27 ns/pF) CL + 26.5 ns
tTLH
Output Fall Time

tTHL

tPLH = (0.11 ns/pF) CL + 24.5 ns
tPLH

tPHL = (0.12 ns/PF) CL + 9 ns
tPHL = (0.11 ns/pF) CL + 4.5 ns
tPHL
VDD
Vdc
Min
Typ (8.)
Max
5.0
10
15
100
50
40
160
100
60
5.0
10
15
40
20
15
60
40
30
5.0
10
15
80
40
30
120
65
50
5.0
10
15
30
15
10
60
30
20
ns
ns
ns
ns
18
15
10
VDD = 15 Vdc
VDD = 10 Vdc
55C
VDD = 5 Vdc
+125C
10
15
18
Figure 1. Typical Voltage Transfer Characteristics versus Temperature
http://onsemi.com
153
Unit
MC14049UB
VDD
VDD
1
IOH
IOL
VOH
VSS
8
VDS = VOH VDD
VDD = VOL
160
I OL, OUTPUT SINK CURRENT (mAdc)
0
I OH , OUTPUT SOURCE CURRNT (mAdc)
VOL
VSS
VGS = 5.0 Vdc

10
VGS = 15 Vdc
120
20
VGS = 10 Vdc
30
40
VGS = 15 Vdc
50
10
8.0
6.0
4.0
2.0

40
VGS = 5.0 Vdc
0
VGS = 10 Vdc
80
2.0
4.0
6.0
8.0
10

VDD
PD , MAXIMUM POWER DISSIPATION (mW)

PER PACKAGE
1
PULSE
GENERATOR
1200
1100
1000
Vout
Vin
8
900
825
800
740
700
600
20 ns
CL
20 ns
VDD
90%
50%
INPUT
(P) PDIP
500
400
VSS
10%
300
200
100
0
25
175 mW (P)
120 mW (D)
50
75
100
125
VSS
tPLH
tPHL
(D) SOIC
150
175
Figure 4. Ambient Temperature Power Derating
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154
OUTPUT
VOH
90%
50%
10%
tTHL
tTLH

and Waveforms
VOL
MC14051B, MC14052B,
MC14053B
Analog
Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers
are digitallycontrolled analog switches. The MC14051B effectively
implements an SP8T solid state switch, the MC14052B a DP4T, and
the MC14053B a Triple SPDT. All three devices feature low ON
impedance and very low OFF leakage current. Control of analog
signals up to the complete supply voltage range can be achieved.
Triple Diode Protection on Control Inputs

Switch Function is Break Before Make
Analog Voltage Range (VDD VEE) = 3.0 to 18 V
Note: VEE must be VSS
Lownoise 12 nV/Cycle, f 1.0 kHz Typical
PinforPin Replacement for CD4051, CD4052, and CD4053
For 4PDT Switch, See MC14551B
For Lower RON, Use the HC4051, HC4052, or HC4053 HighSpeed
CMOS Devices
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MAXIMUM RATINGS (Note 1.)

Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage (Referenced

to VEE, VSS VEE)
0.5 to +18.0
Vin, Vout

(DC or Transient) (Referen
ced to VSS for Control Inputs
and VEE for Switch I/O)
0.5 to VDD + 0.5
Iin

per Control Pin
10
mA
ISW
25
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
MC140XXBCP
AWLYYWW
16
SOIC16
D SUFFIX
CASE 751B
140XXB
AWLYWW
1
16
TSSOP16
DT SUFFIX
CASE 948F
14
0XXB
ALYW
1
16
SOEIAJ16
F SUFFIX
CASE 966
MC140XXB
AWLYWW
1
XX
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
may occur.
See detailed ordering and shipping information in the package

dimensions section on page 163 of this data sheet.
to the range VSS
(Vin or Vout)
VDD.
either VSS, VEE or VDD). Unused outputs must be left open.
March, 2000 Rev. 3
155

MC14051B/D
MC14051B, MC14052B, MC14053B

MC14051B
8Channel Analog
Multiplexer/Demultiplexer
CONTROLS
SWITCHES
IN/OUT
6
11
10
9
13
14
15
12
1
5
2
4
INHIBIT
A
B
C
X0
X1
X
3
X2
COMMON
X3
OUT/IN
X4
X5
X6
X7
MC14052B
Dual 4Channel Analog
CONTROLS
SWITCHES
IN/OUT
6
10
9
12
14
15
11
1
5
2
4
INHIBIT
A
X
B
X0
X1
X2
X3
Y0
Y
Y1
MC14053B
Triple 2Channel Analog
CONTROLS
13
COMMONS
OUT/IN
3
Y2
Y3
SWITCHES
IN/OUT
6
11
10
9
12
13
2
1
5
3
INHIBIT
X
A
B
C
X0
Y
X1
Y0
Y1
Z
Z0
Z1
COMMONS
OUT/IN
15
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
14
Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be VSS.
PIN ASSIGMENT
MC14051B
MC14052B
MC14053B
X4
16
VDD
Y0
16
VDD
Y1
16
VDD
X6
15
X2
Y2
15
X2
Y0
15
14
X1
14
X1
Z1
14
X7
13
X0
Y3
13
13
X1
X5
12
X3
Y1
12
X0
Z0
12
X0
INH
11
INH
11
X3
INH
11
VEE
10
VEE
10
VEE
10
VSS
VSS
VSS
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156
MC14051B, MC14052B, MC14053B
55_C
Characteristic
Symbol
VDD
Test Conditions
25_C
125_C
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

Power Supply Voltage
Range
VDD
VDD 3.0 VSS VEE
3.0
18
3.0
18
3.0
18
Quiescent Current Per

Package
IDD
5.0
10
15
Control Inputs:
Vin = VSS or VDD,
VI/O
Switch I/O: VEE
VDD, and Vswitch
500 mV (4.)
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
ID(AV)
5.0
10
15
TA = 25_C only (The

channel component,
(Vin Vout)/Ron, is
not included.)
Total Supply Current

(Dynamic Plus
Quiescent, Per Package
(0.07 A/kHz) f + IDD

Typical
CONTROL INPUTS INHIBIT, A, B, C (Voltages Referenced to VSS)

LowLevel Input Voltage
VIL
5.0
10
15
Ron = per spec,

Ioff = per spec
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
HighLevel Input Voltage
VIH
5.0
10
15
Ron = per spec,

Ioff = per spec
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Input Leakage Current
Iin
15
Vin = 0 or VDD
0.1
0.00001
0.1
1.0
Input Capacitance
Cin
5.0
7.5
pF
SWITCHES IN/OUT AND COMMONS OUT/IN X, Y, Z (Voltages Referenced to VEE)

Recommended
PeaktoPeak Voltage
Into or Out of the Switch
VI/O
Channel On or Off
VDD
VDD
VDD
VPP
Recommended Static or
Dynamic Voltage Across
the Switch (4.) (Figure 5)
Vswitch
Channel On
600
600
300
mV
VOO
Vin = 0 V, No Load
10
Ron
5.0
10
15
Vswitch
500 mV
Vin = VIL or VIH
(Control), and Vin =
0 to VDD (Switch)
800
400
220
250
120
80
1050
500
280
1200
520
300
Ron
5.0
10
15
70
50
45
25
10
10
70
50
45
135
95
65
Ioff
15
Vin = VIL or VIH

(Control) Channel to
Channel or Any One
Channel
100
0.05
100
1000
nA
Capacitance, Switch I/O
CI/O
Inhibit = VDD
10
pF
Capacitance, Common O/I
CO/I
Inhibit = VDD
(MC14051B)
(MC14052B)
(MC14053B)
60
32
17
Pins Not Adjacent

Pins Adjacent
0.15
0.47
Output Offset Voltage

ON Resistance
ON Resistance Between
Any Two Channels in the
Same Package
OffChannel Leakage
Current (Figure 10)
Capacitance, Feedthrough
(Channel Off)
CI/O
(4.)
pF
pF
3. Data labeled Typ is not to be used for design purposes, but is intended as an indication of the ICs potential performance.
4. For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the
Maximum Ratings are exceeded. (See first page of this data sheet.)
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157
MC14051B, MC14052B, MC14053B
ELECTRICAL CHARACTERISTICS (5.) (CL = 50 pF, TA = 25_C) (VEE

Characteristic
Propagation Delay Times (Figure 6)

Switch Input to Switch Output (RL = 10 k)
MC14051
tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns
VSS unless otherwise indicated)
Symbol
VDD VEE
Vdc
Typ (6.)
All Types
Max
tPLH, tPHL
ns
5.0
10
15
35
15
12
90
40
30
MC14052
5.0
10
15
30
12
10
75
30
25
MC14053
5.0
10
15
25
8.0
6.0
65
20
15
Inhibit to Output (RL = 10 k, VEE = VSS)

Output 1 or 0 to High Impedance, or
High Impedance to 1 or 0 Level
MC14051B
Unit
ns
ns
tPHZ, tPLZ,
tPZH, tPZL
ns
5.0
10
15
350
170
140
700
340
280
MC14052B
5.0
10
15
300
155
125
600
310
250
ns
MC14053B
5.0
10
15
275
140
110
550
280
220
ns
5.0
10
15
360
160
120
720
320
240
MC14052B
5.0
10
15
325
130
90
650
260
180
ns
MC14053B
5.0
10
15
300
120
80
600
240
160
ns
10
0.07
BW
10
17
MHz
Off Channel Feedthrough Attenuation (Figure 7)

RL = 1K, Vin = 1/2 (VDD VEE) pp
fin = 4.5 MHz MC14051B
fin = 30 MHz MC14052B
10
50
dB
Channel Separation (Figure 8)

(RL = 1 k, Vin = 1/2 (VDDVEE) pp,
fin = 3.0 MHz
10
50
dB
Crosstalk, Control Input to Common O/I (Figure 9)

(R1 = 1 k, RL = 10 k
Control tTLH = tTHL = 20 ns, Inhibit = VSS)
10
75
mV
Control Input to Output (RL = 10 k, VEE = VSS)

MC14051B
Second Harmonic Distortion

(RL = 10K, f = 1 kHz) Vin = 5 VPP
Bandwidth (Figure 7)
(RL = 1 k, Vin = 1/2 (VDDVEE) pp, CL = 50pF
20 Log (Vout/Vin) = 3 dB)
tPLH, tPHL
ns
6. Data labelled Typ is not lo be used for design purposes but In intended as an indication of the ICs potential performance.
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158
MC14051B, MC14052B, MC14053B
VDD
VDD
VDD
IN/OUT
OUT/IN
VEE
VDD
LEVEL
CONVERTED
CONTROL
IN/OUT
OUT/IN
CONTROL
VEE
Figure 1. Switch Circuit Schematic
TRUTH TABLE
16
Control Inputs
INH
A
B
C
ON Switches
Select
Inhibit
C*
MC14051B
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
X0
X1
X2
X3
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
X4
X5
X6
X7
None
MC14052B
Y0
Y1
Y2
Y3
X0
X1
X2
X3
MC14053B
Z0
Z0
Z0
Z0
Y0
Y0
Y1
Y1
X0
X1
X0
X1
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
X0
X1
X0
X1
None
6
11
10
9
VDD
BINARY TO 1OF8
DECODER WITH
INHIBIT
LEVEL
CONVERTER
8
X0 13
X1 14
VSS
VEE
X2 15
X3 12
3 X
X4 1
X5 5
None
X6 2
X7 4
*Not applicable for MC14052

x = Dont Care
Figure 2. MC14051B Functional Diagram
16
VDD
16
INH 6
BINARY TO 1OF4
DECODER WITH
INHIBIT
LEVEL
CONVERTER
A 10
B 9
8
X0 12
X1 14
VSS
INH
A
B
C
VEE
X2 15
X3 11
Y0 1
Y1 5
Y2 2
Y3 4
6
11
10
9
BINARY TO 1OF2
DECODER WITH
INHIBIT
LEVEL
CONVERTER
8
13 X
VDD
VSS
VEE
X0 12
X1 13
Y0 2
Y1 1
Z0 5
3 Y
Z1 3
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159
14 X
15 Y
4 Z
MC14051B, MC14052B, MC14053B

TEST CIRCUITS
ON SWITCH
CONTROL
SECTION
OF IC
A
B
C
PULSE
GENERATOR
Vout
LOAD
V
INH
CL
RL
SOURCE
VDD
VEE
VEE VDD
Figure 6. Propagation Delay Times,

Control and Inhibit to Output
A, B, and C inputs used to turn ON

or OFF
the switch under test.
A
B
C
VSS
RL
Vout
INH
RL
A
B
C
ON
INH
OFF
CL = 50 pF
Vout
Vin
RL
CL = 50 pF
VDD VEE
VDD VEE
Vin
Figure 7. Bandwidth and OffChannel

Feedthrough Attenuation
Figure 8. Channel Separation

(Adjacent Channels Used For Setup)
OFF CHANNEL UNDER TEST

VDD
A
B
C
CONTROL
SECTION
OF IC
Vout
RL
INH
VEE
OTHER
CHANNEL(S)
VEE
VDD
CL = 50 pF
R1
COMMON
VEE
VDD
Figure 9. Crosstalk, Control Input to

Common O/I
Figure 10. Off Channel Leakage
NOTE: See also Figures 7 and 8 in the MC14016B

data sheet.
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160
MC14051B, MC14052B, MC14053B

VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 k
RANGE
VDD
XY
PLOTTER
VEE = VSS
Figure 11. Channel Resistance (RON) Test Circuit
300
300
250
200
150
TA = 125C
100
25C
55C
50
0
10
RON , ON RESISTANCE (OHMS)
R ON , ON RESISTANCE (OHMS)
350
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
250
200
150
25C
55C
50
8.0 6.0 4.0 2.0
0.2
4.0
6.0
Vin, INPUT VOLTAGE (VOLTS)
Figure 12. VDD = 7.5 V, VEE = 7.5 V
700
350
600
300
500
400
300
TA = 125C
200
25C
100
0
10
TA = 125C
100
0
10
10
TYPICAL RESISTANCE CHARACTERISTICS

350
55C
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
VDD = 2.5 V
200
150
5.0 V
100
7.5 V
50
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
Figure 15. Comparison at 25C, VDD = VEE
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161
10
TA = 25C
250
0
10
10
8.0
10
MC14051B, MC14052B, MC14053B

Figure A illustrates use of the onchip level converter
detailed in Figures 2, 3, and 4. The 0to5 V Digital Control
signal is used to directly control a 9 Vpp analog signal.
voltage is logic low. For the example, VDD = + 5 V = logic
high at the control inputs; VSS = GND = 0 V = logic low.
and VEE. The VDD voltage determines the maximum
recommended peak above VSS. The VEE voltage
determines the maximum swing below VSS. For the
example, VDD VSS = 5 V maximum swing above VSS ;
VSS VEE = 5 V maximum swing below VSS. The example
shows a 4.5 V signal which allows a 1/2 volt margin at each
peak. If voltage transients above VDD and/or below VEE are

anticipated on the analog channels, external diodes (Dx) are
recommended as shown in Figure B. These diodes should be
small signal types able to absorb the maximum anticipated
current surges during clipping.
VDD and VEE is 18.0 V. Most parameters are specified up to
between VDD and V EE.
Balanced supplies are not required. However, VSS must
be greater than or equal to VEE. For example, VDD = + 10
V, VSS = + 5 V, and VEE 3 V is acceptable. See the Table
below.
+5 V
5 V
VDD
VSS
VEE
+ 4.5 V
9 Vpp
+5 V
ANALOG SIGNAL
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
SWITCH
I/O
COMMON
O/I
MC14051B
9 Vpp
ANALOG SIGNAL
MC14052B
MC14053B
0TO5 V DIGITAL
CONTROL SIGNALS
GND
4.5 V
INHIBIT,
A, B, C

VDD
VDD
DX
DX
ANALOG
I/O
COMMON
O/I
DX
DX
VEE
VEE
POSSIBLE SUPPLY CONNECTIONS

VDD
In Volts
VSS
In Volts
VEE
In Volts
Control Inputs
Logic High/Logic Low
In Volts
+8
+ 8/0
+ 8 to 8 = 16 Vpp
+5
12
+ 5/0
+ 5 to 12 = 17 Vpp
+5
+ 5/0
+ 5 to 0 = 5 Vpp
+5
+ 5/0
+ 5 to 5 = 10 Vpp
+ 10
+5
+ 10/ + 5
+ 10 to 5 = 15 Vpp
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162
Maximum Analog Signal Range

In Volts
MC14051B, MC14052B, MC14053B

Device
Package
Shipping
MC14051BCP
PDIP16
2000 Units per Box
MC14053BCP
PDIP16
2000 Units per Box
MC14053BD
SOIC16
48 Units per Rail
MC14051BD
SOIC16
48 Units per Rail
MC14053BDR2
SOIC16
MC14051BDR2
SOIC16
MC14053BDT
TSSOP16
96 Units per Rail
MC14051BDT
TSSOP16
96 Units per Rail
MC14053BDTEL
TSSOP16
MC14051BDTEL
TSSOP16
MC14053BDTR2
TSSOP16
MC14051BDTR2
TSSOP16
MC14053BF
SOEIAJ16
See Note 7.
MC14051BF
SOEIAJ16
See Note 7.
MC14053BFEL
SOEIAJ16
See Note 7.
MC14051BFEL
SOEIAJ16
See Note 7.
MC14052BCP
PDIP16
2000 Units per Box
MC14052BD
SOIC16
48 Units per Rail
MC14052BDR2
7. For ordering information on the EIAJ version of the SOIC

packages, please contact your local ON Semiconductor representative.
SOIC16
MC14052BDT
TSSOP16
96 Units per Rail
MC14052BDTR2
TSSOP16
MC14052BF
SOEIAJ16
See Note 7.
MC14052BFEL
SOEIAJ16
See Note 7.
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163
MC14060B
14-Bit Binary Counter and
Oscillator
The MC14060B is a 14stage binary ripple counter with an onchip
oscillator buffer. The oscillator configuration allows design of either
RC or crystal oscillator circuits. Also included on the chip is a reset
function which places all outputs into the zero state and disables the
oscillator. A negative transition on Clock will advance the counter to
the next state. Schmitt trigger action on the input line permits very
slow input rise and fall times. Applications include time delay circuits,
counter controls, and frequency dividing circuits.
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
Fully static operation

Buffered Outputs Available from Stages 4 Through 10 and
12 Through 14
Common Reset Line
MC14060BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14060B
AWLYWW
1
16
TSSOP16
DT SUFFIX
CASE 948F
14
060B
ALYW
1

Parameter
Symbol
VDD
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Iin, Iout

(DC or Transient)
SOEIAJ16
F SUFFIX
CASE 966
MC14060B
AWLYWW
1
may occur.
to the range VSS
(Vin or Vout)
VDD.
16
Unit
0.5 to +18.0
Vin, Vout
Value
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14060BCP
PDIP16
2000/Box
MC14060BD
SOIC16
2400/Box
MC14060BDR2
SOIC16
2500/Tape & Reel
MC14060BDT
TSSOP16
96/Rail
MC14060BDTR2
MC14060BF
SOEIAJ16
See Note 1.
MC14060BFEL
SOEIAJ16
See Note 1.

March, 2000 Rev. 3
164

MC14060B/D
MC14060B
PIN ASSIGNMENT
Q12
16
VDD
Q13
15
Q10
Q14
14
Q8
Q6
13
Q9
Q5
12
RESET
Q7
11
CLOCK
Q4
10
OUT 1
VSS
OUT 2
TRUTH TABLE
Clock
Reset
Output State
L
L
H
No Change
Advance to next state
All Outputs are low
X = Dont Care
LOGIC DIAGRAM
OUT 2
9
Q4
OUT 1
Q5
7
10
Q12
1
Q13
2
Q14
3
CLOCK
11
C
C
RESET
12
Q6 = PIN 4
Q7 = PIN 6
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165
Q8 = PIN 14
Q9 = PIN 13
Q10 = PIN 15
VDD = PIN 16
VSS = PIN 8
MC14060B

Characteristic
Symbol
VDD
Vdc
55_C
Min
Max
Min
25_C
Typ (4.)
Max
125_C
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Input Voltage
(VO = 4.5 or 0.5 V)
(VO = 9.0 or 1.0 V)
(VO = 13.5 or 1.5 V)
0 Level
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
(VO = 0.5 or 4.5 V)

(VO = 1.0 or 9.0 V)
(VO = 1.5 or 13.5 V)
1 Level
VIH
5.0
10
15
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
0 Level
(For Input 11
and Output 10)
VIL
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
1 Level
VIH
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5

(VOH = 2.5 V)
(Except Source
(VOH = 4.6 V)
Pins 9 and 10)
(VOH = 9.5 V)
(VOH = 13.5 V)
IOH
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mA
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
IT
5.0
10
15
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)

Per Package)
(CL = 50 pF on all outputs,
all buffers switching)
Sink
Vdc
Vdc
mA

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166
MC14060B
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

Characteristic
Symbol
VDD
Vdc
Min
Typ (7.)
Max
Unit
Output Rise Time (Counter Outputs)
tTLH
5.0
10
15
40
25
20
200
100
80
ns
Output Fall Time (Counter Outputs)
tTHL
5.0
10
15
50
30
20
200
100
80
ns

Clock to Q4
tPLH
tPHL
5.0
10
15
415
175
125
740
300
200
ns
5.0
10
15
1.5
0.7
0.4
2.7
1.3
1.0
twH
5.0
10
15
100
40
30
65
30
20
ns
5.0
10
15
5
14
17
3.5
8
12
MHz
tTLH
tTHL
5.0
10
15
tw
5.0
10
15
120
60
40
40
15
10
5.0
10
15
170
80
60
350
160
100
Clock to Q14
Clock Pulse Width
Reset Pulse Width

Reset to On
tPHL
ns
No Limit
ns
ns
VDD
VDD
500 F
PULSE
GENERATOR
CLOCK
NC
NC
CLOCK
NC
NC
Q4
OUT1 Q5
OUT2 Qn
R
VSS
20 ns
CLOCK
PULSE
GENERATOR
0.01 F
ID
90%
50%
10%
Q4
OUT1 Q5
OUT2
Qn
R
CL
VSS
CL
CL
20 ns
CL
CL
20 ns
90%
50%
10%
CLOCK
20 ns
tPLH
VDD
Q
VSS
tTLH
50% DUTY CYCLE

and Waveform
tWH
tPHL
90%
50%
10%
tTHL

and Waveforms
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167
CL
MC14060B
CLOCK 11
f
10 OUT 1
RESET
if 1 kHz f 100 kHz

and 2Rtc < RS < 10Rtc
(f in Hz, R in ohms, C in farads)
9 OUT 2
Rtc
The formula may vary for other frequencies. Recommended

maximum value for the resistors in 1 M.
Ctc
RS
[ 2.3 R1tcCtc
Figure 3. Oscillator Circuit Using RC Configuration
TYPICAL RC OSCILLATOR CHARACTERISTICS

100
VDD = 15 V
4.0
f, OSCILLATOR FREQUENCY (kHz)
FREQUENCY DEVIATION (%)
8.0
0
1.0 V
4.0
8.0
5.0 V
12
RTC = 56 k
C = 1000 pF
16
55
25
100
10
5
2
1
0.5
0.1
1.0 k
125
0.0001
Figure 4. RC Oscillator Stability
f AS A FUNCTION
OF C
(RTC = 56 k)
(RS = 120 k)
10 k
100 k
RTC, RESISTANCE (OHMS)
0.001
0.01
C, CAPACITANCE (F)
10 OUT 1
9 OUT 2
18M
RO
CT
Figure 6. Typical Crystal Oscillator Circuit
0.1
Characteristic
RESET
1.0 M
Figure 5. RC Oscillator Frequency as a

Function of RTC and C
CLOCK
11
CS
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS 2RTC)
20
0.2
RS = 0, f = 10.15 kHz @ VDD = 10, TA = 25C

RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C
0
25
50
75
VDD = 10 V
50
500 kHz 32 kHz

Circuit Circuit Unit
Crystal Characteristics
Resonant Frequency
Equivalent Resistance, RS
500
1.0
32
6.2
kHz
k
External Resistor/Capacitor Values

RO
CT
CS
47
82
20
750
82
20
k
pF
pF
+ 6.0
+ 2.0
+ 2.0
+ 2.0
ppm
ppm
+ 100
+ 120
ppm
160
560
ppm
Frequency Stability
Frequency Changes as a
Function of VDD (TA = 25_C)
VDD Change from 5.0 V to 10 V
VDD Change from 10 V to 15 V
Frequency Change as a Function
of Temperature (VDD = 10 V)
TA Change from 55_C to
+ 25_C Complete Oscillator (8.)
TA Change from + 25_C to
+ 125_C Complete Oscillator (8.)
8. Complete oscillator includes crystal, capacitors, and resistors.
Figure 7. Typical Data for Crystal Oscillator Circuit
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168
MC14066B
Quad Analog Switch/Quad

Multiplexer
The MC14066B consists of four independent switches capable of
controlling either digital or analog signals. This quad bilateral switch
is useful in signal gating, chopper, modulator, demodulator and
CMOS logic implementation.
The MC14066B is designed to be pinforpin compatible with the
MC14016B, but has much lower ON resistance. Input voltage swings
as large as the full supply voltage can be controlled via each
independent control input.
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MARKING
DIAGRAMS
14
PDIP14
P SUFFIX
CASE 646
Triple Diode Protection on All Control Inputs

Low Noise 12 nV/Cycle, f 1.0 kHz typical
PinforPin Replacement for CD4016, CD4016, MC14016B
For Lower RON, Use The HC4066 HighSpeed CMOS Device
MC14066BCP
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A
14066B
AWLYWW
1
14
TSSOP14
DT SUFFIX
CASE 948G

Symbol
VDD
Parameter
Value
Unit
0.5 to +18.0
Vin, Vout

(DC or Transient)
0.5 to VDD + 0.5
Iin

per Control Pin
10
mA
ISW
25
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
to the range VSS
(Vin or Vout)
VDD.
1
14
SOEIAJ14
F SUFFIX
CASE 965
MC14066B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
may occur.
14
066B
ALYW
Package
Shipping
MC14066BCP
PDIP14
2000/Box
MC14066BD
SOIC14
55/Rail
MC14066BDR2
SOIC14
2500/Tape & Reel
MC14066BDT
TSSOP14
96/Rail
MC14066BDTEL
MC14066BDTR2
MC14066BF
SOEIAJ14
See Note 1.
MC14066BFEL
SOEIAJ14
See Note 1.

March, 2000 Rev. 3
169

MC14066B/D
MC14066B
PIN ASSIGNMENT
IN 1
14
VDD
OUT 1
13
CONTROL 1
OUT 2
12
CONTROL 4
IN 2
11
IN 4
CONTROL 2
10
OUT 4
CONTROL 3
OUT 3
VSS
IN 3
LOGIC DIAGRAM AND TRUTH TABLE

(1/4 OF DEVICE SHOWN)
BLOCK DIAGRAM
CONTROL 1
13
2
OUT 1
IN/OUT
IN 1
OUT/IN
5
CONTROL 2
IN 2
CONTROL 3
IN 3
CONTROL 4
IN 4
CONTROL
3
OUT 2
4
6
9
8
OUT 3
Control
Switch
0 = VSS
OFF
1 = VDD
ON
12
10
OUT 4
11
VDD = PIN 14
VSS = PIN 7
CIRCUIT SCHEMATIC
VDD VDD
VDD
VSS
VDD
CMOS
INPUT
VDD
VDD
VDD
300
VSS
VSS
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170
Logic Diagram Restrictions

VSS Vin VDD
VSS Vout VDD
MC14066B
55_C
Characteristic
Symbol
VDD
Test Conditions
25_C
125_C
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
3.0
18
3.0
18
3.0
18
0.25
0.5
1.0
0.005
0.010
0.015
0.25
0.5
1.0
7.5
15
30

Range
VDD

Package
IDD
5.0
10
15
Control Inputs:
Vin = VSS or VDD,
VI/O
Switch I/O: VSS
VDD, and
Vswitch
500 mV (5.)
ID(AV)
5.0
10
15
TA = 25_C only The

channel component,
(Vin Vout)/Ron, is
not included.)

(Dynamic Plus Quiescent,
Per Package
Typical

CONTROL INPUTS (Voltages Referenced to VSS)

VIL
5.0
10
15
Ron = per spec,

Ioff = per spec
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
VIH
5.0
10
15
Ron = per spec,

Ioff = per spec
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Iin
15
Vin = 0 or VDD
0.1
0.00001
0.1
1.0
Input Capacitance
Cin
5.0
7.5
pF
SWITCHES IN AND OUT (Voltages Referenced to VSS)

Recommended Peakto
Peak Voltage Into or Out
of the Switch
VI/O
Channel On or Off
VDD
VDD
VDD
Vpp
Vswitch
Channel On
600
600
300
mV
VOO
Vin = 0 V, No Load
10
Ron
5.0
10
15
Vswitch
500 mV
Vin = VIL or VIH
0 to VDD (Switch)
800
400
220
250
120
80
1050
500
280
1200
520
300
Ron
5.0
10
15
70
50
45
25
10
10
70
50
45
135
95
65
Ioff
15
Vin = VIL or VIH

Channel or Any One
Channel
100
0.05
100
1000
nA
CI/O
Switch Off
10
15
pF
(Switch Off)
CI/O
0.47
pF

ON Resistance
Any Two Channels
in the Same Package
OffChannel Leakage
Current (Figure 6)
(5.),
5. For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
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171
MC14066B
ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C unless otherwise noted.)

Characteristic
Propagation Delay Times

Input to Output (RL = 10 k)
Symbol
VSS = 0 Vdc
Control to Output (RL = 1 k) (Figure 2)

Output 1 to High Impedance
VDD
Vdc
Min
Typ (7.)
Max
tPLH, tPHL
Unit
ns
5.0
10
15
20
10
7.0
40
20
15
5.0
10
15
40
35
30
80
70
60
tPHZ
ns
tPLZ
5.0
10
15
40
35
30
80
70
60
ns
High Impedance to Output 1
tPZH
5.0
10
15
60
20
15
120
40
30
ns
High Impedance to Output 0
tPZL
5.0
10
15
60
20
15
120
40
30
ns

VSS = 5 Vdc
(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,
RL = 10 k, f = 1.0 kHz)
5.0
0.1
Bandwidth (Switch ON) (Figure 3)

VSS = 5 Vdc
(RL = 1 k, 20 Log (Vout/Vin) = 3 dB, CL = 50 pF,
Vin = 5 Vpp)
5.0
65
MHz
Feedthrough Attenuation (Switch OFF)

VSS = 5 Vdc
(Vin = 5 Vpp, RL = 1 k, fin = 1.0 MHz) (Figure 3)
5.0
50
dB

(Vin = 5 Vpp, RL = 1 k, fin = 8.0 MHz)
(Switch A ON, Switch B OFF)
VSS = 5 Vdc
5.0
50
dB
Crosstalk, Control Input to Signal Output (Figure 5)

VSS = 5 Vdc
(R1 = 1 k, RL = 10 k, Control tTLH = tTHL = 20 ns)
5.0
300
mVpp
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172
MC14066B
TEST CIRCUITS
Vout
VC
RL
ON SWITCH
CONTROL
SECTION
OF IC
20 ns
Vout
VSS
tPHZ
90%
tPZL
tPLZ
10%
90%
Vout
SOURCE
VDD
tPZH
LOAD
V
Vx
Vin
90%
50%
10%
VC
CL
Vin = VDD
Vx = VSS
Vin = VSS
Vx = VDD
10%
Figure 2. TurnOn Delay Time Test Circuit

and Waveforms
VDD VSS
2
VC = VDD FOR BANDWIDTH TEST

VC = VSS FOR FEEDTHROUGH TEST
Vin
VDD VSS
2
VDD
Vin
CL
RL
CL
Vout
RL
CL
VC
VSS
VDD
RL
VSS
Figure 3. Bandwidth and


VDD
Vin
Vout
1k
RL
10 k
CONTROL
SECTION
OF IC
CL = 50 pF
VSS
VSS
VDD
VC = 5.0 V TO + 5.0 V SWING
Figure 5. Crosstalk,
Control to Output
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173
MC14066B
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 k
RANGE
VDD
XY
PLOTTER
VSS
350
300
300
250
200
150
TA = 125C
100
25C
55C
50
0
10
350
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
250
200
150
25C
55C
50
8.0 6.0 4.0 2.0
0.2
4.0
6.0
Figure 8. VDD = 7.5 V, VSS = 7.5 V
700
350
600
300
500
400
300
TA = 125C
200
25C
100
0
10
TA = 125C
100
0
10
10
55C
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
VDD = 2.5 V
200
150
5.0 V
100
7.5 V
50
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
Figure 11. Comparison at 25C, VDD = VSS
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174
10
TA = 25C
250
0
10
10
8.0
10
MC14066B
Figure A illustrates use of the Analog Switch. The 0
to5 volt digital control signal is used to directly control a
5 volt peaktopeak analog signal.
and VSS. The VDD voltage is the logic high voltage, the VSS
and VSS. The analog voltage must not swing higher than
VDD or lower than VSS.
The example shows a 5 volt peaktopeak signal which
allows no margin at either peak. If voltage transients above
VDD and/or below VSS are anticipated on the analog

channels, external diodes (Dx) are recommended as shown
in Figure B. These diodes should be small signal types able
to absorb the maximum anticipated current surges during
clipping.
VDD and VSS is 18.0 volts. Most parameters are specified up
to 15 volts which is the recommended maximum difference
between VDD and V SS.
+5 V
VDD
VSS
+ 5.0 V
5 Vpp
SWITCH
IN
ANALOG SIGNAL
SWITCH
OUT
+5 V
5 Vpp
ANALOG SIGNAL
+ 2.5 V
GND
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
0TO5 V DIGITAL
MC14066B
CONTROL SIGNALS
VDD
VDD
DX
DX
SWITCH
IN
SWITCH
OUT
DX
DX
VSS
VSS
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175
MC14067B
Analog Multiplexers /
Demultiplexers
The MC14067 multiplexer/demultiplexer is a digitally controlled
analog switch featuring low ON resistance and very low leakage
current. This device can be used in either digital or analog
applications.
The MC14067 is a 16channel multiplexer/demultiplexer with an
inhibit and four binary control inputs A, B, C, and D. These control
inputs select 1of16 channels by turning ON the appropriate analog
switch (see MC14067 truth table.)
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MARKING
DIAGRAMS
24
PDIP24
P SUFFIX
CASE 709
Low OFF Leakage Current

Matched Channel Resistance
Low Quiescent Power Consumption
Low Crosstalk Between Channels
Wide Operating Voltage Range: 3 to 18 V
Low Noise
Pin for Pin Replacement for CD4067B
MC14067BCP
AWLYYWW
1
24
SOIC24
DW SUFFIX
CASE 751E
14067B
AWLYYWW
1

Symbol
VDD
Vin, Vout
Parameter

(DC or Transient)
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Package
Shipping
MC14067BCP
PDIP24
15/Rail
mA
MC14067BDW
SOIC24
30/Rail
500
mW
MC14067BDWR2
SOIC24
1000/Tape & Reel
55 to + 125
_C
Tstg
65 to + 150
_C
TL
Lead Temperature
(8Second Soldering)
260
_C
Iin
Input Current (DC or Transient),

per Control Pin
10
mA
Isw
25
PD
Power Dissipation,
TA
Device
may occur.
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
176

MC14067B/D
MC14067B
MC14067 TRUTH TABLE
Control Inputs
A
Inh
Selected
Channel
X
0
1
0
X
0
0
1
X
0
0
0
X
0
0
0
1
0
0
0
None
X0
X1
X2
1
0
1
0
1
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
X3
X4
X5
X6
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
X7
X8
X9
X10
1
0
1
0
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
X11
X12
X13
X14
X15
MC14067B
PIN ASSIGNMENT
X
24
VDD
X7
23
X8
X6
22
X9
X5
21
X10
X4
20
X11
X3
19
X12
X2
18
X13
X1
17
X14
X0
16
X15
10
15
INHIBIT
11
14
VSS
12
13
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177
MC14067B
MC14067B
16Channel Analog
CONTROLS
SWITCHES
IN/OUT
15
10
11
14
13
9
8
7
6
5
4
3
2
23
22
21
20
19
18
17
16
INHIBIT
A
B
C
D
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
COMMON
OUT/IN
VDD = PIN 24
VSS = PIN 12
MC14067 FUNCTIONAL DIAGRAM
CONTROL
INPUTS
INHIBIT
A
B
C
D
X
IN/OUT
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
1OF16 DECODER
X
OUT/IN
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178
MC14067B
v
v
25_C
55C
Characteristic
Symbol
VDD
Test Conditions
125_C
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
3.0
18
3.0
18
3.0
18
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
SUPPLY REQUIREMENTS (Voltages Referenced to VSS)

Range
VDD

Package
IDD
5.0
10
15
Control Inputs: Vin =

VSS or VDD,
Switch I/O: VSS
VI/O
VDD, and
Vswitch 500 mV (4.)
ID(AV)
5.0
10
15
TA = 25_C only (The

channel component,
(Vin Vout)/Ron, is
not included.)

(Dynamic Plus
Quiescent,
Per Package

Typical
CONTROL INPUTS INHIBIT, A, B, C, D (Voltages Referenced to VSS)

VIL
5.0
10
15
Ron = per spec,

Ioff = per spec
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
VIH
5.0
10
15
Ron = per spec,

Ioff = per spec
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Iin
15
Vin = 0 or VDD
0.1
0.00001
0.1
1.0
Input Capacitance
Cin
5.0
7.5
pF
SWITCHES IN/OUT AND COMMONS OUT/IN X, Y (Voltages Referenced to VSS)

Recommended Peakto
Peak Voltage Into or
Out of the Switch
VI/O
Channel On or Off
VDD
VDD
VDD
Vpp
Dynamic Voltage
Across the Switch (4.)
(Figure 1)
Vswitch
Channel On
600
600
300
mV
VOO
Vin = 0 V, No Load
10
Ron
5.0
10
15
Vswitch
500 mV
Vin = VIL or VIH
(Control), and Vin
0 to VDD (Switch)
800
400
220
250
120
80
1050
500
280
1300
550
320
Ron
5.0
10
15
70
50
45
25
10
10
70
50
45
135
95
65
Ioff
15
Vin = VIL or VIH

Channel or Any One
Channel
100
0.05
100
1000
nA
CI/O
Inhibit = VDD
10
pF
CO/I
Inhibit = VDD
(MC14067B)
(MC14097B)
100
60
0.47

ON Resistance
Any Two Channels
in the Same Package
OffChannel Leakage
Current (Figure 2)
(Channel Off)
CI/O
(4.),
pF
Pins Not Adjacent

Pins Adjacent
pF
4. For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e.
the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
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179
MC14067B
ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C)
VDD VSS
Characteristic
Symbol

Channel InputtoChannel Output (RL = 200 k)
MC14067B
Typ (5.)
Max
tPLH, tPHL
(Figure 3)
(Figure 4)
Channel TurnOff Time (RL = 300 k)

MC14067B
5.0
10
15
35
15
12
90
40
30
ns
5.0
10
15
240
115
75
600
290
190
tPHZ, tPLZ
(Figure 4)
Any Pair of Address Inputs to Output

MC14067B
ns
5.0
10
15
250
120
75
625
300
190
tPLH, tPHL

(RL = 10 k, f = 1 kHz, Vin = 5 Vpp)
ns
5.0
10
15
280
115
85
700
290
215
10
0.3
BW
MC14067B
Off Channel Feedthrough Attenuation

[RL = 1 k, Vin = 1/2 (VDDVSS) pp(sinewave)]
Channel Separation
[RL = 1 k, Vin = 1/2 (VDDVSS) pp (sinewave)]
Crosstalk, Control InputstoCommon O/I
(R1 = 1 k, RL = 10 k,
Control tr = tf = 20 ns, Inhibit = VSS)
MHz
10
15
10
40
dB
10
40
dB
10
30
mV
(Figure 5)
(Figure 6)
(Figure 7)
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180
(Figure 5)
fin = 20 MHz
Unit
ns
tPZH, tPZL
Control InputtoChannel Output

Channel TurnOn Time (RL = 10 k)
MC14067B
ON Channel Bandwidth
[RL = 1 k, Vin = 1/2 (VDD VSS) pp(sinewave)]
20 Log10 (Vout/Vin) = 3 dB
Vdc
MC14067B
VDD
ON SWITCH
CONTROL
SECTION
OF IC
CONTROL
SECTION
OF IC
VSS
OTHER
CHANNEL(S)
LOAD
VSS
VDD
SOURCE
VSS
VDD
VC
PULSE
GENERATOR
VDD
A
B
C
D
Vout
RL
CL = 50 pF
VDD VSS
20 ns
90%
50%
tPLH
VC
20 ns
VX
VSS VDD
20 ns
90%
50%
10%
VDD
10%
tPHL
Vout
VSS
90%
50%
tPZH, tPZL
Vout
CL = 50 pF
RL
Vin
Vin
Vin
Vout
INH
INH
20 ns
A
B
C
D
50%
Vout
Figure 3. Propagation Delay Test Circuit

and Waveforms Vin to Vout
tPHZ, tPLZ
50%
10%
Figure 4. TurnOn and Delay TurnOff

Test Circuit and Waveforms
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181
Vin = VDD
VX = VSS
Vin = VSS
VX = VDD
MC14067B
VDD
A, B, and C inputs used to turn ON or OFF

A
B
C
D
RL
A
B
C
D
ON
INH
OFF
Vout
Vout
INH
RL
RL
CL = 50 pF
CL = 50 pF
Vin
Vin


(Adjacent Channels Used for Setup)
A
B
C
D
VC
Vout
RL
INH
CL = 50 pF
R1
Figure 7. Crosstalk, Control to Common O/I
VA
VB
A
B
C
D
INH
CL
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
VDD
1 k
RANGE
XY
PLOTTER
VDD
Vout
VA
50%
VB
50%
tPHL
VSS
Vout
tPLH
50%
Figure 9. Propagation Delay, Any Pair of

Address Inputs to Output
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182
MC14067B
350
300
300
250
200
150
TA = 125C
100
25C
55C
50
0
10
350
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
250
200
150
25C
55C
50
8.0 6.0 4.0 2.0
0.2
4.0
6.0
700
350
600
300
500
400
300
TA = 125C
200
25C
100
0
10
TA = 125C
100
0
10
10
55C
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
VDD = 2.5 V
200
150
5.0 V
100
7.5 V
50
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
Figure 13. Comparison at 25C, VDD = VSS
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183
10
TA = 25C
250
0
10
10
8.0
10
MC14067B
Figure A illustrates use of the Analog
Multiplexer/Demultiplexer. The 0to5 volt Digital Control
signal is used to directly control a 5 Vpp analog signal.
voltage is logic low. For the example. VDD = + 5 V = logic
and VSS. The analog voltage must swing neither higher than
VDD nor lower than VSS. The example shows a 5 Vpp
signal which allows no margin at either peak. If voltage

transients above VDD and/or below VSS are anticipated on
the analog channels, external diodes (Dx) are recommended
as shown in Figure B. These diodes should be small signal
types able to absorb the maximum anticipated current surges
during clipping.
The absolute maximum potential difference between VDD
and VSS is 18.0 volts. Most parameters are specified up to
between VDD and VSS.
+5 V
VDD
VSS
+ 5.0 V
5 Vpp
SWITCH
I/O
ANALOG SIGNAL
COMMON
O/I
+5 V
5 Vpp
ANALOG SIGNAL
GND
MC14067B
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
+ 2.5 V
0TO5 V DIGITAL
CONTROL SIGNALS
VDD
VDD
DX
DX
SWITCH
I/O
COMMON
O/I
DX
DX
VSS
VSS
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184
MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS Pchannel
and Nchannel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
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Capable of Driving Two LowPower TTL Loads or One LowPower
MARKING
DIAGRAMS

PinforPin Replacement for CD4069UB
Meets JEDEC UB Specifications
14
PDIP14
P SUFFIX
CASE 646
MC14069UBCP
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A

Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Symbol
VDD
Vin, Vout
Iin, Iout

(DC or Transient)
1
14
TSSOP14
DT SUFFIX
CASE 948G
14
069U
ALYW
1
may occur.
to the range VSS
(Vin or Vout)
VDD.
14069U
AWLYWW
14
SOEIAJ14
F SUFFIX
CASE 965
MC14069U
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14069UBCP
PDIP14
2000/Box
MC14069UBD
SOIC14
2750/Box
MC14069UBDR2
SOIC14
2500/Tape & Reel
TSSOP14
96/Rail
MC14069UBDT
MC14069UBDTEL TSSOP14 2000/Tape & Reel

MC14069UBDTR2 TSSOP14 2500/Tape & Reel
MC14069UBF
SOEIAJ14
See Note 1.
MC14069UBFEL
SOEIAJ14
See Note 1.

March, 2000 Rev. 3
185

MC14069UB/D
MC14069UB
PIN ASSIGNMENT
IN 1
14
VDD
OUT 1
13
IN 6
IN 2
12
OUT 6
OUT 2
11
IN 5
IN 3
10
OUT 5
OUT 3
IN 4
VSS
OUT 4
LOGIC DIAGRAM
CIRCUIT SCHEMATIC
1
3
11
10
13
12
VDD
VDD = PIN 14
VSS = PIN 7
INPUT*
OUTPUT
VSS
*Double diode protection on all
inputs not shown.
20 ns
20 ns
VDD
14
PULSE
GENERATOR
OUTPUT
INPUT
7
VSS
VDD
90%
50%
10%
INPUT
tPHL
CL
tPLH
90%
50%
10%
OUTPUT
tTHL
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186
VSS
VOH
VOL
tTLH
MC14069UB
55_C
25_C
125_C
Symbo
l
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Characteristic
Output Voltage
Vin = VDD
Vin = 0
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
1 Level
VIH
(VO = 0.5 Vdc)

(VO = 1.0 Vdc)
(VO = 1.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Gate) (CL = 50 pF)
Output Rise and Fall Times (5.)

(CL = 50 pF)
tTLH,
tTHL
Propagation Delay Times (5.)

(CL = 50 pF)
tPLH,
tPHL
mAdc
IT = (0.3 A/kHz) f + IDD/6

IT = (0.6 A/kHz) f + IDD/6
IT = (0.9 A/kHz) f + IDD/6
Adc
ns
5.0
10
15
100
50
40
200
100
80
ns
5.0
10
15
65
40
30
125
75
55
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187
MC14070B, MC14077B
CMOS SSI
Quad Exclusive OR and NOR Gates

The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS Pchannel and
Nchannel enhancement mode devices in a single monolithic
structure. These complementary MOS logic gates find primary use
where low power dissipation and/or high noise immunity is desired.
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MARKING
DIAGRAMS

14
PDIP14
P SUFFIX
CASE 646

MC14070B Replacement for CD4030B and CD4070B Types
MC14077B Replacement for CD4077B Type
MC140XXBCP
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A
140XXB
AWLYWW
1

Parameter
14
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Symbol
VDD
Vin, Vout
Iin, Iout

(DC or Transient)
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
188
MC140XXB
AWLYWW
1
XX
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
may occur.
SOEIAJ14
F SUFFIX
CASE 965
Package
Shipping
MC140XXBCP
PDIP14
2000/Box
MC140XXBD
SOIC14
2750/Box
MC140XXBDR2
SOIC14
2500/Tape & Reel
MC140XXBF
SOEIAJ14
See Note 1.
MC140XXBFEL
SOEIAJ14
See Note 1.


MC14070B/D
MC14070B, MC14077B
PIN ASSIGNMENT
IN 1A
14
VDD
IN 2A
13
IN 2D
OUTA
12
IN 1D
OUTB
11
OUTD
IN 1B
10
OUTC
IN 2B
IN 2C
VSS
IN 1C
MC14070B
QUAD Exclusive OR
Gate
MC14077B
QUAD Exclusive NOR
Gate
1
3
2
5
4
6
8
3
2
5
4
6
8
10
9
12
10
9
12
11
13
11
13
VDD = PIN 14
VSS = PIN 7
(BOTH DEVICES)
20 ns
VDD
Vin
VDD
90%
50%
10%
Vin
IDD
20 ns
VSS
1/f
50% DUTY CYCLE
*
CL
*Inverted output on MC14077B only.
PULSE
GENERATOR
INPUT
*
#
VSS
20 ns
20 ns
VDD
CL
tPHL
OUTPUT
tPLH
90%
50%
10%
tTHL
*Inverted output on MC14077B only.
#Connect unused input to VDD for MC14070B, to VSS for MC14077B.
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189
VDD
90%
50%
10%
tTLH
VSS
VOH
VOL
MC14070B, MC14077B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink

Per Package)
buffers switching)
Output Rise and Fall Times (5.)

(CL = 50 pF)
tTLH,
tTHL
Propagation Delay Times (5.)

(CL = 50 pF)
tPLH,
tPHL
mAdc

Adc
ns
5.0
10
15
100
50
40
200
100
80
ns
5.0
10
15
175
75
55
350
150
110
where: IT is in H (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.002.
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190
MC14076B
4-Bit D-Type Register
with Three-State Outputs
The MC14076B 4Bit Register consists of four Dtype flipflops
operating synchronously from a common clock. OR gated
outputdisable inputs force the outputs into a highimpedance state
for use in bus organized systems. OR gated datadisable inputs cause
the Q outputs to be fed back to the D inputs of the flipflops. Thus they
are inhibited from changing state while the clocking process remains
undisturbed. An asynchronous master root is provided to clear all four
flipflops simultaneously independent of the clock or disable inputs.
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MARKING
DIAGRAMS
16
ThreeState Outputs with Gated Control Lines

Fully Independent Clock Allows Unrestricted Operation for the Two
PDIP16
P SUFFIX
CASE 648
Modes: Parallel Load and Do Nothing

Asynchronous Master Reset
Four Bus Buffer Registers
Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
VDD
Vin, Vout
Iin, Iout

(DC or Transient)
1
16
SOIC16
D SUFFIX
CASE 751B
14076B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Symbol
MC14076BCP
AWLYYWW
Device
Package
Shipping
MC14076BCP
PDIP16
2000/Box
MC14076BD
SOIC16
2400/Box
MC14076BDR2
SOIC16
2500/Tape & Reel
may occur.
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
191

MC14076B/D
MC14076B
PIN ASSIGNMENT
OUTPUT
DISABLE
{B
16
VDD
15
Q0
14
D0
Q1
13
D1
Q2
12
D2
Q3
11
D3
10
VSS
} DATA
DISABLE
BLOCK DIAGRAM
15
14
13
12
11
10
9
7
2
1
Q0
Q1
DATA
DISABLE
Q2
CLOCK
B OUTPUT
A DISABLE
Q3
RESET
D0
D1
D2
D3
B
A
VDD = PIN 16
VSS = PIN 8
FUNCTION TABLE
Inputs
Data Disable
Reset
Clock
Data
D
Output
Q
Qn
Qn
Qn
When either output disable A or B (or both) is (are) high the

output is disabled to the highimpedance state; however
sequential operation of the flipflops is not affected.
X = Dont Care.
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192
MC14076B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
ThreeState Leakage Current
ITL
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
0.1
Adc
3.0
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193
Adc
MC14076B

Characteristic
Symbol

tTLH, tTHL

Clock to Q
tPLH, tPHL
Reset to Q
VDD
Vdc
Min
Typ (7.)
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
300
125
90
600
250
180
5.0
10
15
300
125
90
600
250
180
3State Propagation Delay, Output 1 or 0

to High Impedance
tPHZ, tPLZ
5.0
10
15
150
60
45
300
120
90
ns
3State Propagation Delay, High Impedance

to 1 or 0 Level
tPZH, tPZL
5.0
10
15
200
80
60
400
160
120
ns
Clock Pulse Width
tWH
5.0
10
15
260
110
80
130
55
40
ns
Reset Pulse Width
tWH
5.0
10
15
370
150
110
185
75
55
ns
Data Setup Time
tsu
5.0
10
15
30
10
4
15
5
2
ns
Data Hold Time
th
5.0
10
15
130
60
50
65
30
25
ns
Data Disable Setup Time
tsu
5.0
10
15
220
80
50
110
40
25
ns
tTLH, tTHL
5.0
10
15
15
5
4
fcl
5.0
10
15
3.6
9.0
12
1.8
4.5
6.0
MHz
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194
MC14076B
20 ns
OUTPUT
DISABLE
A OR B
INPUT RISE AND FALL 20 ns

90%
50%
10%
th
tsu
INPUT
INFORMATION
tsu
tWL
fcl
OUTPUT
VDD
10%
90%
10%
tPHZ
90%
OUTPUTS
CONNECTED
OUTPUTS
DISCONNECTED
VOH
VOL
tTHL
tTLH
ANY Q
OUTPUT
RL = 1 k
OTHER
INPUTS
RESET = 0
DATA DISABLE A AND B = 0
OUTPUT DISABLE A AND B = 0
MC14076B
1
2
D0 14
C
DATA DISABLE A
DATA DISABLE B
9
10
D1 13
C
CLOCK
VOH
2.5 V @ VDD = 5 V,
10 V, AND 15 V
2 V @ VDD = 5 V
6 V @ VDD = 10 V
10 V @ VDD = 15 V
VOL
OUTPUTS
CONNECTED
VDD FOR tPLZ AND tPZL

VSS FOR tPHZ AND tPZH
Figure 2. ThreeState Propagation Delay

Waveshape and Circuit
EQUIVALENT
FUNCTIONAL BLOCK DIAGRAM
OUTPUT DISABLE A
OUTPUT DISABLE B
VSS
CL
OUTPUT
DISABLE
A OR B
tPZH
10%
50%
10%
tPZL
90%
ANY Q
OUTPUT
VSS
tPHL
tPLH
Q
ANY Q
OUTPUT
VSS
90%
VDD
10%
tPLZ
20 ns
50%
tWH
50%
VDD
th
20 ns
90%
50%
Q
R Q
3 Q0
Q
R Q
4 Q1
D2 12
D3 11
R Q
RESET 15
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195
R Q
5 Q2
6 Q3
MC14093B
Quad 2-Input NAND"
Schmitt Trigger
The MC14093B Schmitt trigger is constructed with MOS
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14093B
may be used in place of the MC14011B quad 2input NAND gate for
enhanced noise immunity or to square up slowly changing
waveforms.
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MARKING
DIAGRAMS

14
PDIP14
P SUFFIX
CASE 646

PinforPin Compatible with CD4093
Can be Used to Replace MC14011B
Independent SchmittTrigger at each Input
MC14093BCP
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A
14093B
AWLYWW
1
14
TSSOP14
DT SUFFIX
CASE 948G

Symbol
VDD
Vin, Vout
Parameter
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Iin, Iout

(DC or Transient)
Value
1
14
SOEIAJ14
F SUFFIX
CASE 965
MC14093B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
may occur.
to the range VSS
(Vin or Vout)
VDD.
14
093B
ALYW
Device
Package
Shipping
MC14093BCP
PDIP14
2000/Box
MC14093BD
SOIC14
2750/Box
MC14093BDR2
SOIC14
2500/Tape & Reel
MC14093BDT
TSSOP14
96/Rail
MC14093BDTEL
MC14093BDTR2
MC14093BF
SOEIAJ14
See Note 1.
MC14093BFEL
SOEIAJ14
See Note 1.

March, 2000 Rev. 3
196

MC14093B/D
MC14093B
PIN ASSIGNMENT
IN 1A
14
VDD
IN 2A
13
IN 2D
OUTA
12
IN 1D
OUTB
11
OUTD
IN 1B
10
OUTC
IN 2B
IN 2C
VSS
IN 1C
LOGIC DIAGRAM
1
2
5
6
8
9
10
12
13
11
VDD = PIN 14
VSS = PIN 7
EQUIVALENT CIRCUIT SCHEMATIC

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197
MC14093B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Hysteresis Voltage
VH
5.0
10
15
0.3
1.2
1.6
2.0
3.4
5.0
0.3
1.2
1.6
1.1
1.7
2.1
2.0
3.4
5.0
0.3
1.2
1.6
2.0
3.4
5.0
Threshold Voltage
PositiveGoing
VT+
5.0
10
15
2.2
4.6
6.8
3.6
7.1
10.8
2.2
4.6
6.8
2.9
5.9
8.8
3.6
7.1
10.8
2.2
4.6
6.8
3.6
7.1
10.8
VT
5.0
10
15
0.9
2.5
4.0
2.8
5.2
7.4
0.9
2.5
4.0
1.9
3.9
5.8
2.8
5.2
7.4
0.9
2.5
4.0
2.8
5.2
7.4
Vin = 0 or VDD

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOH
Source
Sink

Per Package)
buffers switching)
NegativeGoing
mAdc

Adc
Vdc
Vdc
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198
Vdc
MC14093B

Characteristic
Symbol
VDD
Vdc
Min
Typ (7.)
Max
Unit
Output Rise Time
tTLH
5.0
10
15
100
50
40
200
100
80
ns
Output Fall Time
tTHL
5.0
10
15
100
50
40
200
100
80
ns
tPLH, tPHL
5.0
10
15
125
50
40
250
100
80
ns
7. Data labeled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
VDD
20 ns
14
PULSE
GENERATOR
INPUT
OUTPUT
20 ns
VDD
90%
50%
10%
tPHL
INPUT
7
VSS
CL
tPLH
90%
50%
10%
OUTPUT
tTHL
VSS
VOH
VOL
tTLH
VH
VDD
VH
Vin
VDD
Vin
VSS
VSS
VDD
VDD
Vout
Vout
VSS
VSS
(a) Schmitt Triggers will square up

(a) inputs with slow rise and fall times.
(b) A Schmitt trigger offers maximum

(b) noise immunity in gate applications.
Figure 2. Typical Schmitt Trigger Applications
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199
MC14093B
14
14
IOH
VGS
Vout
All unused inputs
connected to ground.
VGS
10
VGS = 5.0 Vdc

a
b
b
TA = 55C
TA = + 25C
TA = + 125C
c
6.0
10 Vdc
8.0
10
10
IOL , DRAIN CURRENT (mAdc)
4.0
7
All unused inputs
connected to ground.
c
b
2.0
15 Vdc
a
8.0
Vout
6.0
4.0
b c
15 Vdc
a
8.0
VGS = 10 Vdc
b
c
6.0
a
b
c
4.0
a
2.0
2.0
4.0
6.0
8.0

VDD
5.0 Vdc

TA = 55C
TA = + 25C
TA = + 125C
2.0
IOH, DRAIN CURRENT (mAdc)
IOL
VT
VT+
VH
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200
VDD
10
MC14094B
8-Stage Shift/Store Register
with Three-State Outputs
The MC14094B combines an 8stage shift register with a data latch
for each stage and a threestate output from each latch.
Data is shifted on the positive clock transition and is shifted from the
seventh stage to two serial outputs. The QS output data is for use in
highspeed cascaded systems. The QS output data is shifted on the
following negative clock transition for use in lowspeed cascaded
systems.
Data from each stage of the shift register is latched on the negative
transition of the strobe input. Data propagates through the latch while
strobe is high.
Outputs of the eight data latches are controlled by threestate
buffers which are placed in the highimpedance state by a logic Low
on Output Enable.
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
1
16
ThreeState Outputs
SOIC16
D SUFFIX
CASE 751B
16
TSSOP16
DT SUFFIX
CASE 948F
Negative Clock Transitions

Useful for SerialtoParallel Data Conversion
PinforPin Compatible with CD4094B
16
SOEIAJ16
F SUFFIX
CASE 966
MC14094B
AWLYWW
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Device
Package
Shipping
Tstg
65 to +150
MC14094BCP
PDIP16
2000/Box
TL
Lead Temperature
(8Second Soldering)
260
MC14094BD
SOIC16
48/Rail
MC14094BDR2
SOIC16
2500/Tape & Reel
MC14094BDT
TSSOP16
96/Rail
MC14094BDTR2
TSSOP16
2500/Tape & Reel
MC14094BF
SOEIAJ16
See Note 1.
VDD
Vin, Vout
Iin, Iout
Parameter
14
094B
ALYW
1

Symbol
14094B
AWLYWW
1
Input Diode Protection

Data Latch
Dual Outputs for Data Out on Both Positive and
MC14094BCP
AWLYYWW

(DC or Transient)
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
may occur.
201
1. For ordering information on the EIAJ version of the

SOIC packages, please contact your local ON
Semiconductor representative.

MC14094B/D
MC14094B
PIN ASSIGNMENT
Clock
DATA
15
CLOCK
14
VDD
OUTPUT
ENABLE
Q5
Q1
13
Q6
Q2
12
Q7
STROBE
16
Q3
11
Q8
Q4
10
QS
VSS
QS
Parallel Outputs
Serial Outputs
Output
Enable
Strobe
Data
Q1
QN
QS *
QS
Q7
No Chg.
No Chg.
Q7
No Chg.
No Chg.
Q7
No Chg.
QN1
Q7
No Chg.
QN1
Q7
No Chg.
No Chg.
No Chg.
No Chg.
Q7
Z = High Impedance
X = Dont Care
* At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS.
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202
MC14094B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
3State Output Leakage Current
ITL
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
mAdc

IT = (14 A/kHz) f + IDD
0.1
0.0001
0.1
Adc
3.0
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203
MC14094B

Characteristic
Symbol

tTLH,
tTHL

Clock to Serial out QS
tPLH, tPHL = (0.26 ns/pF) C L + 82 ns
tPLH,
tPHL
VDD
Vdc
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
350
125
95
600
250
190
Clock to Serial out QS

5.0
10
15
230
110
75
460
220
150
Clock to Parallel out

5.0
10
15
420
195
135
840
390
270
Strobe to Parallel out

tPLH, tPHL = (0.36 ns/pF) C L + 127 ns
5.0
10
15
290
145
100
580
290
200
tPHZ,
tPZL
5.0
10
15
140
75
55
280
150
110
tPLZ,
tPZH
5.0
10
15
225
95
70
450
190
140
Setup Time
Data in to Clock
tsu
5.0
10
15
125
55
35
60
30
20
ns
Hold Time
Clock to Data
th
5.0
10
15
0
20
20
40
10
0
ns
Clock Pulse Width, High
tWH
5.0
10
15
200
100
83
100
50
40
ns
tr(cl)
tf(cl)
5
10
15
15
5.0
4.0
fcl
5.0
10
15
2.5
5.0
6.0
1.25
2.5
3.0
MHz
tWL
5.0
10
15
200
80
70
100
40
35
ns
Output Enable to Output

tPHZ, tPZL = (0.90 ns/pF) CL + 95 ns
tPHZ, tPZL = (0.36 ns/PF) CL + 57 ns
tPHZ, tPZL = (0.26 ns/pF) CL + 42 ns
tPLZ, tPZH = (0.90 ns/pF) CL + 180 ns

Strobe Pulse Width
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204
MC14094B
3STATE TEST CIRCUIT
FOR tPHZ AND tPZH
VSS
O.E.
FOR tPLZ AND tPZL

VDD
1k
DATA
OUTPUT
ST
50 pF
CLOCK
BLOCK DIAGRAM
REGISTER STAGE 1
CLOCK
2
VDD
CLOCK
CLOCK
STROBE STROBE
CLOCK
CLOCK
STROBE
Q1
*
2
OUTPUT
ENABLE
3
4
5
6
7
REGISTER STAGE 2
LATCH 2
3STATE BUFFER 2
Q2
REGISTER STAGE 3
LATCH 3
3STATE BUFFER 3
Q3
REGISTER STAGE 4
LATCH 4
3STATE BUFFER 4
Q4
REGISTER STAGE 5
LATCH 5
3STATE BUFFER 5
14
Q5
REGISTER STAGE 6
LATCH 6
3STATE BUFFER 6
13
Q6
REGISTER STAGE 7
LATCH 7
3STATE BUFFER 7
12
Q7
LATCH 8
3STATE BUFFER 8
11
Q8
10
QS
QS
REGISTER STAGE 8
CLOCK
3STATE BUFFER 1
STROBE
*
SERIAL
DATA IN
15
LATCH 1
CLOCK
STROBE STROBE
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
1
*
STROBE
STROBE
*Input Protection Diodes
STROBE
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205
CLOCK
MC14094B
DYNAMIC TIMING DIAGRAM
tWH
tf
tr
CLOCK
50%
90%
50%
10%
th
tsu
2
DATA IN
tWL
STROBE
15
OUTPUT
ENABLE
50%
tPLH
Q1
Q7
tTLH
QS
tPHL
tPLH
tPHZ
90%
90%
50%
10%
10%
tTHL
tPLZ
tPZL
90%
10%
10%
tPHL
tPLH
50%
50%
tPLH
10 QS
tPZH
90%
50%
tPHL
50%
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206
MC14099B
8-Bit Addressable Latches
The MC14099B is an 8bit addressable latch. Data is entered in
serial form when the appropriate latch is addressed (via address pins
A0, A1, A2) and write disable is in the low state. For the MC14099B
the input is a unidirectional write only port.
The data is presented in parallel at the output of the eight latches
independently of the state of Write Disable, Write/Read or Chip
Enable.
A Master Reset capability is available on both parts.
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MARKING
DIAGRAMS
Serial Data Input

Parallel Output
Master Reset
Capable of Driving Two Lowpower TTL Loads or One LowPower
Schottky TTL Load over the Rated Temperature Range
MC14099B pin for pin compatible with CD4099B
16
PDIP16
P SUFFIX
CASE 648
1
16
Parameter
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Vin, Vout
Iin, Iout

(DC or Transient)
March, 2000 Rev. 3
SOEIAJ16
F SUFFIX
CASE 966
MC14099B
AWLYWW
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
to the range VSS
(Vin or Vout)
VDD.
16
may occur.
AWLYYWW
1
Value
VDD
14099B
SOIC16
DW SUFFIX
CASE 751G

Symbol
MC14099BCP
AWLYYWW
207
Package
Shipping
MC14099BCP
PDIP16
2000/Box
MC14099BDW
SOIC16
2350/Box
MC14099BDWR2
SOIC16
1000/Tape & Reel
MC14099BF
SOEIAJ16
See Note 1.
MC14099BFEL
SOEIAJ16
See Note 1.


MC14099B/D
MC14099B
PIN ASSIGNMENT
Q7
16
VDD
RESET
15
Q6
DATA
WRITE
DISABLE
A0
14
Q5
WRITE DISABLE
DATA
13
Q4
12
Q3
A0
A1
A2
A1
11
Q2
RESET
A2
10
Q1
MC14099B
4
3
5
6
DECODER
7
9
10
11
12
8
13
LATCHES 14
15
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
VDD = 16
VSS = 8
VSS
Q0

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Cin
5.0
7.5
pF
Input Capacitance
MC14599B Data (pin 3)
(Vin = 0)
Cin
15
22.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink

Per Package)
buffers switching)
mAdc

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208
Adc
MC14099B
VDD
Vdc
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
200
75
50
400
150
100
Write Disable to Output Q
5.0
10
15
200
80
60
400
160
120
ns
Reset to Output Q
5.0
10
15
175
80
65
350
160
130
ns
CE to Output Q (MC14599B only)
5.0
10
15
225
100
75
450
200
150
ns
5.0
10
15
200
80
65
400
160
130
5.0
10
15
200
90
75
400
180
150
5.0
10
15
150
75
50
75
40
25
5.0
10
15
320
160
120
160
80
60
5.0
10
15
100
50
35
50
25
20
5.0
10
15
150
75
50
75
40
25
Characteristic
Symbol

tTLH,
tTHL

Data to Output Q
tPHL,
tPLH
Propagation Delay Time, MC14599B only

Chip Enable, Write/Read to Data
tPHL,
tPLH
Address to Data
Pulse Widths
Reset
tw(H)
tw(L)
Write Disable
Unit
ns
ns
ns
ns
ns
ns
Set Up Time
Data to Write Disable
tsu
ns
Hold Time
Write Disable to Data
th
Set Up Time
Address to Write Disable
tsu
5.0
10
15
100
80
40
45
30
10
ns
Removal Time
Write Disable to Address
trem
5.0
10
15
0
0
0
80
40
40
ns
ns
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209
MC14099B
MC14099B
FUNCTION DIAGRAM
RESET 2
9 Q0
DATA 3
WRITE
4
DISABLE
EACH LATCH
TO
OTHER
LATCHES
ZERO
SELECT
10 Q1
A0 5
11 Q2
12 Q3
ADDRESS
DECODER
A1 6
OTHER LATCHES
13 Q4
14 Q5
15 Q6
A2 7
(M.S.B.)
1 Q7
TRUTH TABLE
Write
Disable
Reset
Addressed
Latch
Unaddressed
Latches
Data
Qn*
Data
Reset {
Qn*
Qn*
Reset
Reset
CAUTION: To avoid unintentional data changes in the latches, Write

Disable must be active (high) during transitions on the
address inputs A0, A1, and A2.
*Qn is previous state of latch.

Reset to zero state.
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210
MC14099B
SWITCHING WAVEFORMS
VDD
DATA OR
WRITE DISABLE
50%
VSS
tPHL
tPLH
OUTPUT Q
VDD
90%
50%
10%
ADDRESS
50%
VSS
tw(L)
tsu
tTLH
tTHL
VDD
WRITE
DISABLE
50%
VSS
tw(H)
tsu
VDD
RESET
trem
VDD
DATA
50%
VSS
tPHL
OUTPUT Q
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211
th
50%
VSS
MC14106B
Hex Schmitt Trigger
The MC14106B hex Schmitt Trigger is constructed with MOS
may be used in place of the MC14069UB hex inverter for enhanced
noise immunity or to square up slowly changing waveforms.
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Increased Hysteresis Voltage Over the MC14584B

MARKING
DIAGRAMS
14
PDIP14
P SUFFIX
CASE 646

PinforPin Replacement for CD40106B and MM74C14
Can Be Used to Replace the MC14584B or MC14069UB
MC14106BCP
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A

Symbol
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
VDD
Vin, Vout
Iin, Iout
Parameter
(DC or Transient)
may occur.
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
212
14106B
AWLYWW
1
14
TSSOP14
DT SUFFIX
CASE 948G
14
106B
ALYW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14106BCP
PDIP14
2000/Box
MC14106BD
SOIC14
55/Rail
MC14106BDR2
SOIC14
2500/Tape & Reel
MC14106BDT
TSSOP14
96/Rail
MC14106BDTR2

MC14106B/D
MC14106B
LOGIC DIAGRAM
1
11
10
13
12
VDD = PIN 14
VSS = PIN 7
EQUIVALENT CIRCUIT SCHEMATIC

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213
MC14106B

Characteristic
Output Voltage
Vin = VDD
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Hysteresis Voltage
VH (6.)
5.0
10
15
0.3
1.2
1.6
2.0
3.4
5.0
0.3
1.2
1.6
1.1
1.7
2.1
2.0
3.4
5.0
0.3
1.2
1.6
2.0
3.4
5.0
Vdc
Threshold Voltage
PositiveGoing
VT+
5.0
10
15
2.2
4.6
6.8
3.6
7.1
10.8
2.2
4.6
6.8
2.9
5.9
8.8
3.6
7.1
10.8
2.2
4.6
6.8
3.6
7.1
10.8
Vdc
VT
5.0
10
15
0.9
2.5
4.0
2.8
5.2
7.4
0.9
2.5
4.0
1.9
3.9
5.8
2.8
5.2
7.4
0.9
2.5
4.0
2.8
5.2
7.4
Vdc
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Vin = 0
NegativeGoing

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

where IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001.
6. VH = VT+ VT (But maximum variation of VH is specified as less that VT+ max VT min).
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214
Adc
MC14106B

Characteristic
Symbol
VDD
Vdc
Min
Typ (7.)
Max
Unit
Output Rise Time
tTLH
5.0
10
15
100
50
40
200
100
80
ns
Output Fall Time
tTHL
5.0
10
15
100
50
40
200
100
80
ns
tPLH, tPHL
5.0
10
15
125
50
40
250
100
80
ns
INPUT
INPUT
7
VSS
20 ns
tPHL
CL
tPLH
90%
50%
10%
OUTPUT
tf
VDD
0
0
VDD
90%
50%
10%
PULSE
GENERATOR
20 ns
VDD
14
OUTPUT
VT+
VT
VH
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215
VDD
tr
VSS
VOH
VOL
MC14106B
APPLICATIONS
Vout
Vin
VDD
VH
Vin
VDD
VH
Vin
VSS
VSS
VDD
VDD
Vout
Vout
VSS
VSS
(a) Schmitt Triggers will square up

inputs with slow rise and fall times.
(b) A Schmitt trigger offers maximum

noise immunity in gate applications.
Figure 3.
VDD
VDD
R
C
tw
Rs
tw
Rs
Vout
Vout
R
tw = RC IN
Useful as Pushbutton/Keyboard Debounce Circuit.
Figure 4. Monostable Multivibrator
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216
VDD
VT+
MC14106B
1
f
t1
Vin
Vout
C
t2
C
* t1
[ RC ln VTT)
* t2
[ RC ln VVDDDD VTT)
VDD
Vin VT+
VSS
1
f
[ RC ln
*t1 + t2
VDD VT
VDD VT )
VDD
VT+
VSS
VT )
VDD
Vout VT+
VSS
VT
& tPHL + tPLH
Useful in discriminating against short pulse durations.
Figure 5. Astable Multivibrator
Figure 6. Integrator
C
Vin
Vin
R
+ EDGE
EDGE
EDGE
+ EDGE
Vin
VDD
tw
VDD
tw = RC ln
VT+
Useful as an edge detector circuit.
Figure 7. Differentiator
Figure 8. Positive Edge Time Delay Circuit
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217
MC14174B
Hex Type D Flip-Flop
The MC14174B hex type D flipflop is constructed with MOS
monolithic structure. Data on the D inputs which meets the setup time
requirements is transferred to the Q outputs on the positive edge of the
clock pulse. All six flipflops share common clock and reset inputs.
The reset is active low, and independent of the clock.
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Static Operation
All Inputs and Outputs Buffered
Functional Equivalent to TTL 74174
MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MC14174BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B

Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Symbol
VDD
Vin, Vout
Iin, Iout

(DC or Transient)
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
16
SOEIAJ16
F SUFFIX
CASE 966
218
MC14174B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
may occur.
14174B
AWLYWW
Package
Shipping
MC14174BCP
PDIP16
2000/Box
MC14174BD
SOIC16
48/Rail
MC14174BDR2
SOIC16
2500/Tape & Reel
MC14174BF
SOEIAJ16
See Note 1.
MC14174BFEL
SOEIAJ16
See Note 1.


MC14174B/D
MC14174B
PIN ASSIGNMENT
R
16
Q0
15
Q5
D0
14
D5
D1
13
D4
Q1
12
Q4
VDD
D2
11
D3
Q2
10
Q3
VSS
BLOCK DIAGRAM
Q0
Q1
D1
Q2
D2
Q3
10
11
D3
13
D4
Q4
12
14
D5
Q5
15
CLOCK
RESET
D0
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
(Positive Logic)
Inputs
Clock
Output
Data
Reset
0
1
X
X
1
1
1
0
0
1
Q
0
X
X = Dont Care
http://onsemi.com
219
No
Change
MC14174B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

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220
Adc
MC14174B

Characteristic
Symbol
All Types
VDD
Vdc
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
210
85
65
400
160
120
5.0
10
15
250
100
75
500
200
150
Unit

tTLH, tTHL
Propagation Delay Time Clock to Q

tPLH, tPHL
Propagation Delay Time Reset to Q

tPHL
Clock Pulse Width
tWH
5.0
10
15
150
90
70
75
45
35
ns
Reset Pulse Width
tWL
5.0
10
15
200
100
80
100
50
40
ns
fcl
5.0
10
15
7.0
12
15.5
2.0
5.0
6.5
mHz
tTLH, tTHL
5.0
10
15
15
5.0
4.0
ms
Data Setup Time
tsu
5.0
10
15
40
20
15
20
10
0
ns
Data Hold Time
th
5.0
10
15
80
40
30
40
20
15
ns
trem
5.0
10
15
250
100
80
125
50
40
ns
Reset Removal Time
ns
ns
ns
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221
MC14174B
TIMING DIAGRAM
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222
MC14175B
Quad Type D Flip-Flop
The MC14175B quad type D flipflop is constructed with MOS
monolithic structure. Each of the four flipflops is positiveedge
triggered by a common clock input (C). An activelow reset input (R)
asynchronously resets all flipflops. Each flipflop has independent
Data (D) inputs and complementary outputs (Q and Q). These devices
may be used as shift register elements or as type T flipflops for
counter and toggle applications.
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MARKING
DIAGRAMS
Complementary Outputs
Static Operation
All Inputs and Outputs Buffered
Output Compatible with Two LowPower TTL Loads or One
LowPower Schottky TTL Load
Functional Equivalent to TTL 74175
16
PDIP16
P SUFFIX
CASE 648
MC14175BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14175B
AWLYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966

Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Symbol
VDD
Vin, Vout
Iin, Iout

(DC or Transient)
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
may occur.
MC14175B
AWLYWW
223
Device
Package
Shipping
MC14175BCP
PDIP16
2000/Box
MC14175BD
SOIC16
48/Rail
MC14175BDR2
SOIC16
2500/Tape & Reel
MC14175BF
SOEIAJ16
See Note 1.
MC14175BFEL
SOEIAJ16
See Note 1.


MC14175B/D
MC14175B
PIN ASSIGNMENT
R
16
Q0
15
Q3
Q0
14
Q3
D0
13
D3
D1
12
D2
Q1
11
Q2
Q1
10
Q2
VSS
VDD
BLOCK DIAGRAM
9
CLOCK
RESET
D0
D1
12
D2
13
D3
Q0
Q0
Q1
Q1
Q2
10
Q2
11
Q3
15
Q3
14
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Inputs
Clock
Outputs
Data
Reset
0
1
X
X
1
1
1
0
0
1
Q
0
1
0
Q
1
X
X = Dont Care
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224
No
Change
MC14175B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

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225
Adc
MC14175B

Characteristic
Symbol

tTLH, tTHL
Propagation Delay Time Clock to Q, Q

tPLH, tPHL
Propagation Delay Time Reset to Q, Q

tPHL = (0.36 ns/pF) CL + 112 ns
tPHL, tPLH
All Types
VDD
Vdc
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
220
90
70
400
160
120
5.0
10
15
325
130
100
500
200
150
Unit
ns
ns
ns
Clock Pulse Width
tWH
5.0
10
15
250
100
75
110
45
35
ns
Reset Pulse Width
tWL
5.0
10
15
200
80
60
100
40
30
ns
fcl
5.0
10
15
4.5
11
14
2.0
5.0
6.5
mHz
tTLH, tTHL
5.0
10
15
15
5.0
4.0
ms
Data Setup Time
tsu
5.0
10
15
120
50
40
60
25
20
ns
Data Hold Time
th
5.0
10
15
80
40
30
40
20
15
ns
trem
5.0
10
15
250
100
80
125
50
40
ns
Reset Removal Time
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226
MC14175B
TIMING DIAGRAM
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227
MC14490
Hex Contact Bounce
Eliminator
The MC14490 is constructed with complementary MOS
enhancement mode devices, and is used for the elimination of
extraneous level changes that result when interfacing with mechanical
contacts. The digital contact bounce eliminator circuit takes an input
signal from a bouncing contact and generates a clean digital signal
four clock periods after the input has stabilized. The bounce eliminator
circuit will remove bounce on both the make and the break of a
contact closure. The clock for operation of the MC14490 is derived
from an internal RC oscillator which requires only an external
capacitor to adjust for the desired operating frequency (bounce delay).
The clock may also be driven from an external clock source or the
oscillator of another MC14490 (see Figure 5).
NOTE: Immediately after powerup, the outputs of the MC14490
are in indeterminate states.

Six Debouncers Per Package
Internal Pullups on All Data Inputs
Can Be Used as a Digital Integrator, System Synchronizer, or Delay
Line
Internal Oscillator (RC), or External Clock Source
TTL Compatible Data Inputs/Outputs
Single Line Input, Debounces Both Make and Break Contacts
Does Not Require Form C (Single Pole Double Throw) Input
Signal
Cascadable for Longer Time Delays
Schmitt Trigger on Clock Input (Pin 7)
Chip Complexity: 546 FETs or 136.5 Equivalent Gates

Symbol
VDD
Vin, Vout
Parameter
(DC or Transient)
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MC14490P
AWLYYWW
1
16
14490
SOIC16
DW SUFFIX
CASE 751G
AWLYYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966
MC14490
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14490DW
SOIC16
47/Rail
MC14490DWR2
SOIC16
1000/Tape & Reel
MC14490F
SOEIAJ16
See Note 1.
MC14490FEL
SOEIAJ16
See Note 1.
PDIP16
25/Rail
Iin
Input Current
10
mA
MC14490P
PD
Power Dissipation,
500
mW

TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
may occur.
March, 2000 Rev. 3
228

range VSS
(Vin or Vout)
VDD.

MC14490/D
MC14490
PIN ASSIGNMENT
Ain
16
VDD
Bout
15
Aout
Cin
14
Bin
Dout
13
Cout
Ein
12
Din
Fout
11
Eout
OSCin
10
Fin
VSS
OSCout
BLOCK DIAGRAM
+VDD
DATA
4BIT STATIC SHIFT REGISTER
Ain 1
SHIFT
OSCin 7
OSCout 9
Bin 14
Cin 3
Din 12
OSCILLATOR
AND
TWOPHASE
CLOCK GENERATOR
LOAD
1 2
IDENTICAL TO ABOVE STAGE
13 Cout
Fin 10
4 Dout
11 Eout
1
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229
VDD = PIN 16
VSS = PIN 8
1 2
2 Bout
Ein 5
15 Aout
1/2BIT
DELAY
2
6 Fout
MC14490

Characteristic
55_C
25_C
(4.)
125_C
Min
Max
Min
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Output Voltage
Vin = VDD or 0
Symbol
VDD
Vdc
Vin = 0 or VDD

Oscillator Output
(VOH = 2.5 V)
(VOH = 4.6 V)
(VOH = 9.5 V)
(VOH = 13.5 V)
Typ
Vdc
IOH
Vdc
mAdc
Source
Debounce Outputs
(VOH = 2.5 V)
(VOH = 4.6 V)
(VOH = 9.5 V)
(VOH = 13.5 V)
Oscillator Output
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
Sink
5.0
5.0
10
15
0.6
0.12
0.23
1.4
0.5
0.1
0.2
1.2
1.5
0.3
0.8
3.0
0.4
0.08
0.16
1.0
5.0
5.0
10
15
0.9
0.19
0.6
1.8
0.75
0.16
0.5
1.5
2.2
0.46
1.2
4.5
0.6
0.12
0.4
1.2
5.0
10
15
0.36
0.9
4.2
0.3
0.75
3.5
0.9
2.3
10
0.24
0.6
2.8
5.0
10
15
2.6
4.0
12
2.2
3.3
10
4.0
9.0
35
1.8
2.7
8.1
IOL
Debounce Outputs
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
mAdc
Input Current
Debounce Inputs (Vin = VDD)
IIH
15
2.0
0.2
2.0
11
Adc
Input Current Oscillator Pin 7

(Vin = VSS or VDD)
Iin
15
620
255
400
250
Adc
Pullup Resistor Source Current

Debounce Inputs
(Vin = VSS)
IIL
5.0
10
15
175
340
505
375
740
1100
140
280
415
190
380
570
255
500
750
70
145
215
225
440
660
Adc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
(Vin = VSS or VDD, Iout = 0 A)
ISS
5.0
10
15
150
280
840
40
90
225
100
225
650
90
180
550
Adc
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230
MC14490
VDD
Vdc
Min
Typ (6.)
Max
Unit
5.0
10
15
180
90
65
360
180
130
ns
5.0
10
15
100
50
40
200
100
80
ns
tTHL
5.0
10
15
60
30
20
120
60
40
tPHL
5.0
10
15
285
120
95
570
240
190
tPLH
5.0
10
15
370
160
120
740
320
240
Clock Frequency (50% Duly Cycle)

(External Clock)
fcl
5.0
10
15
2.8
6
9
1.4
3.0
4.5
MHz
Setup Time (See Figure 1)
tsu
5.0
10
15
100
80
60
50
40
30
ns
Maximum External Clock Input

Rise and Fall Time
Oscillator Input
tr, tf
5.0
10
15
Characteristic
Symbol
Output Rise Time

All Outputs
Output Fall Time
tTLH
Oscillator Output
tTHL
Debounce Outputs

Oscillator Input to Debounce Outputs
Oscillator Frequency
OSCout
Cext 100 pF*
ns
ns
No Limit
fosc, typ
Hz
5.0
10
Note: These equations are intended to be a design guide.

Laboratory experimentation may be required. Formulas
are typically 15% of actual frequencies.
15
*POWERDOWN CONSIDERATIONS
Large values of Cext may cause problems when powering down the MC14490 because of the amount of energy stored in the
capacitor. When a system containing this device is powered down, the capacitor may discharge through the input protection
diodes at Pin 7 or the parasitic diodes at Pin 9. Current through these internal diodes must be limited to 10 mA, therefore the
turnoff time of the power supply must not be faster than t = (VDD VSS) Cext / (10 mA). For example, If VDD VSS = 15
V and Cext = 1 F, the power supply must turn off no faster than t = (15 V) (1 F) / 10 mA = 1.5 ms. This is usually not a problem
because power supplies are heavily filtered and cannot discharge at this rate.
When a more rapid decrease of the power supply to zero volts occurs, the MC14490 may sustain damage. To avoid this
possibility, use external clamping diodes, D1 and D2, connected as shown in Figure 2.
0V
tPLH
Aout
VDD
50%
OSCin
50%
90%
10%
D1
tr
tPHL
Aout
90%
10%
D2
VDD
7
OSCin
50%
tf
OSCin
Cext
VDD
50%
VDD
9
OSCout
MC14490
0V
tsu
Ain
50%
VDD
0V
Figure 1. Switching Waveforms
Figure 2. Discharge Protection During Power Down

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231
MC14490
THEORY OF OPERATION
After some time period of N clock periods, the contact is
opened and at N +1 a low is loaded into the first bit. Just after
N+1, when the input bounces low, all bits are set to a high.
At N +2 nothing happens because the input and output are
low and all bits of the shift register are high. At time N +3
and thereafter the input signal is a high, clean signal. At the
positive edge of N +6 the output goes high as a result of four
lows being shifted into the shift register.
Assuming the input signal is long enough to be clocked
through the Bounce Eliminator, the output signal will be no
longer or shorter than the clean input signal plus or minus
one clock period.
The amount of time distortion between the input and
output signals is a function of the difference in bounce
characteristics on the edges of the input signal and the clock
frequency. Since most relay contacts have more bounce
when making as compared to breaking, the overall delay,
counting bounce period, will be greater on the leading edge
of the input signal than on the trailing edge. Thus, the output
signal will be shorter than the input signal if the leading
edge bounce is included in the overall timing calculation.
The only requirement on the clock frequency in order to
obtain a bounce free output signal is that four clock periods
do not occur while the input signal is in a false state.
Referring to Figure 3, a false state is seen to occur three times
at the beginning of the input signal. The input signal goes
low three times before it finally settles down to a valid low
state. The first three low pulses are referred to as false states.
If the user has an available clock signal of the proper
frequency, it may be used by connecting it to the oscillator
input (pin 7). However, if an external clock is not available
the user can place a small capacitor across the oscillator
input and output pins in order to start up an internal clock
source (as shown in Figure 4). The clock signal at the
oscillator output pin may then be used to clock other
MC14490 Bounce Eliminator packages. With the use of the
MC14490, a large number of signals can be cleaned up, with
the requirement of only one small capacitor external to the
Hex Bounce Eliminator packages.
The MC14490 Hex Contact Bounce Eliminator is

basically a digital integrator. The circuit can integrate both
up and down. This enables the circuit to eliminate bounce on
both the leading and trailing edges of the signal, shown in the
timing diagram of Figure 3.
Each of the six Bounce Eliminators is composed of a
41/2bit register (the integrator) and logic to compare the
input with the contents of the shift register, as shown in
Figure 4. The shift register requires a series of timing pulses
in order to shift the input signal into each shift register
location. These timing pulses (the clock signal) are
represented in the upper waveform of Figure 3. Each of the
six Bounce Eliminator circuits has an internal resistor as
shown in Figure 4. A pullup resistor was incorporated rather
than a pulldown resistor in order to implement switched
ground input signals, such as those coming from relay
contacts and push buttons. By switching ground, rather than
a power supply lead, system faults (such as shorts to ground
on the signal input leads) will not cause excessive currents
in the wiring and contacts. Signal lead shorts to ground are
much more probable than shorts to a power supply lead.
When the relay contact is closed, (see Figure 4) the low
level is inverted, and the shift register is loaded with a high
on each positive edge of the clock signal. To understand the
operation, we assume all bits of the shift register are loaded
with lows and the output is at a high level.
At clock edge 1 (Figure 3) the input has gone low and a
high has been loaded into the first bit or storage location of
the shift register. Just after the positive edge of clock 1, the
input signal has bounced back to a high. This causes the shift
register to be reset to lows in all four bits thus starting the
timing sequence over again.
During clock edges 3 to 6 the input signal has stayed low.
Thus, a high has been shifted into all four shift register bits
and, as shown, the output goes low during the positive edge
of clock pulse 6.
It should be noted that there is a 31/2 to 41/2 clock
period delay between the clean input signal and output
signal. In this example there is a delay of 3.8 clock periods
from the beginning of the clean input signal.
N+1
N+3
N+5
OSCin OR OSCout
INPUT
OUTPUT
CONTACT
OPEN
CONTACT
BOUNCING
CONTACT CLOSED
(VALID TRUE SIGNAL)
CONTACT OPEN
CONTACT
BOUNCING

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232
N+7
MC14490
+VDD
PULLUP RESISTOR
(INTERNAL)
Ain
1
FORM A
CONTACT
OSCin 7
Cext
OSCout
DATA
4BIT STATIC SHIFT REGISTER
SHIFT
OSCILLATOR
AND
TWOPHASE
CLOCK GENERATOR
1/2 BIT
DELAY
15
Aout
LOAD
1 2
1 2
Figure 4. Typical Form A Contact Debounce Circuit

(Only One Debouncer Shown)
OPERATING CHARACTERISTICS
The single most important characteristic of the MC14490
is that it works with a single signal lead as an input, making
it directly compatible with mechanical contacts (Form A
and B).
The circuit has a builtin pullup resistor on each input.
The worst case value of the pullup resistor (determined from
the Electrical Characteristics table) is used to calculate the
contact wetting current. If more contact current is required,
an external resistor may be connected between VDD and the
input.
Because of the builtin pullup resistors, the inputs cannot
be driven with a single standard CMOS gate when VDD is
below 5 V. At this voltage, the input should be driven with
paralleled standard gates or by the MC14049 or MC14050

buffers.
The clock input circuit (pin 7) has Schmitt trigger shaping
such that proper clocking will occur even with very slow
clock edges, eliminating any need for clock preshaping. In
addition, other MC14490 oscillator inputs can be driven
from a single oscillator output buffered by an MC14050 (see
Figure 5). Up to six MC14490s may be driven by a single
buffer.
The MC14490 is TTL compatible on both the inputs and
the outputs. When VDD is at 4.5 V, the buffered outputs can
sink 1.6 mA at 0.4 V. The inputs can be driven with TTL as
a result of the internal input pullup resistors.
OSCin 7
Cext
OSCin
FROM CONTACTS
MC14490
NO CONNECTION
9 OSCout
1/6 MC14050
FROM
CONTACTS
OSCout
TO SYSTEM
LOGIC
TO SYSTEM
LOGIC
MC14490
NO CONNECTION
9 OSCout
OSCin 7
FROM CONTACTS
MC14490
Figure 5. Typical Single Oscillator Debounce System
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233
TO SYSTEM
LOGIC
MC14490
ASYMMETRICAL TIMING
MULTIPLE TIMING SIGNALS
In applications where different leading and trailing edge

delays are required (such as a fast attack/slow release timer.)
Clocks of different frequencies can be gated into the
MC14490 as shown in Figure 6. In order to produce a slow
attack/fast release circuit leads A and B should be
interchanged. The clock out lead can then be used to feed
clock signals to the other MC14490 packages where the
asymmetrical input/output timing is required.
As shown in Figure 8, the Bounce Eliminator circuits can

be connected in series. In this configuration each output is
delayed by four clock periods relative to its respective input.
This configuration may be used to generate multiple timing
signals such as a delay line, for programming other timing
operations.
One application of the above is shown in Figure 9, where
it is required to have a single pulse output for a single
operation (make) of the push button or relay contact. This
only requires the series connection of two Bounce
Eliminator circuits, one inverter, and one NOR gate in order
to generate the signal AB as shown in Figures 9 and 10. The
signal AB is four clock periods in length. If the inverter is
switched to the A output, the pulse AB will be generated
upon release or break of the contact. With the use of a few
additional parts many different pulses and waveshapes may
be generated.
IN
OSCin
OUT
MC14490
OSCout
MC14011B
15
1
B.E. 1
A
EXTERNAL
CLOCK
Ain
B
fC
fC/N
14
B.E. 2
Bin
Aout
Bout
Figure 6. Fast Attack/Slow Release Circuit

13
3
B.E. 3
LATCHED OUTPUT
Cout
Cin
The contents of the Bounce Eliminator can be latched by

using several extra gates as shown in Figure 7. If the latch
lead is high the clock will be stopped when the output goes
low. This will hold the output low even though the input has
returned to the high state. Any time the clock is stopped the
outputs will be representative of the input signal four clock
periods earlier.
12
B.E. 4
Dout
Din
5
B.E. 5
11
Eout
Ein
IN
OUT
10
Fout
Fin
MC14490
OSCin
B.E. 6
OSCout
MC14011B
CLOCK
OSCin
LATCH = 1
UNLATCH = 0
CLOCK
OSCout
Figure 8. Multiple Timing Circuit Connections
Figure 7. Latched Output Circuit
http://onsemi.com
234
MC14490
IN
OUT
BE 1
A
IN
OUT
BE 2
AB
A ACTIVE LOW
B ACTIVE LOW
Figure 9. Single Pulse Output Circuit
OSCin OR
OSCout
INPUT
AB
AB
Figure 10. Multiple Output Signal Timing Diagram
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235
MC14503B
Hex Non-Inverting 3-State
Buffer
The MC14503B is a hex noninverting buffer with 3state outputs,
and a high current source and sink capability. The 3state outputs
make it useful in common bussing applications. Two disable controls
are provided. A high level on the Disable A input causes the outputs of
buffers 1 through 4 to go into a high impedance state and a high level
on the Disable B input causes the outputs of buffers 5 and 6 to go into a
high impedance state.
http://onsemi.com
MARKING
DIAGRAMS
3State Outputs
TTL Compatible Will Drive One TTL Load Over Full
16
PDIP16
P SUFFIX
CASE 648
Temperature Range

Two Disable Controls for Added Versatility
Pin for Pin Replacement for MM80C97 and 340097
MC14503BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14503B
AWLYWW
1

Parameter
Symbol
VDD
Vin, Vout

(DC or Transient)
16
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5
Iin
Input Current
10
mA
Iout
Output Current
25
mA
PD
Power Dissipation,
500
mW
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
may occur.
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
MC14503B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
TA
SOEIAJ16
F SUFFIX
CASE 966
236
Device
Package
Shipping
MC14503BCP
PDIP16
2000/Box
MC14503BD
SOIC16
48/Rail
MC14503BDR2
SOIC16
2500/Tape & Reel
MC14503BF
SOEIAJ16
See Note 1.
MC14503BFEL
SOEIAJ16
See Note 1.


MC14503B/D
MC14503B
PIN ASSIGNMENT
DIS A
16
VDD
IN 1
15
DIS B
OUT 1
14
IN 6
IN 2
13
OUT 6
OUT 2
12
IN 5
IN 3
11
OUT 5
OUT 3
10
IN 4
VSS
OUT 4
TRUTH TABLE
LOGIC DIAGRAM
Inn
Appropriate
Disable
Input
Outn
High
Impedance
DISABLE B
IN 5
IN 6
IN 1
X = Dont Care
IN 2
IN 3
IN 4
DISABLE A
15
12
11
14
13
10
1
VDD = PIN 16
VSS = PIN 8
CIRCUIT DIAGRAM
ONE OF TWO/FOUR BUFFERS

VDD
* INn
OUTn
* DISABLE
* INPUT
VSS
TO OTHER BUFFERS
*Diode protection on all inputs (not shown)
http://onsemi.com
237
OUT 5
OUT 6
OUT 1
OUT 2
OUT 3
OUT 4
MC14503B

Characteristic
Output Voltage
Vin = 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 3.6 or 1.4 Vdc)
(VO = 7.2 or 2.8 Vdc)
(VO = 11.5 or 3.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
4.5
5.0
5.0
10
15
4.3
5.8
1.2
3.1
8.2
3.6
4.8
1.02
2.6
6.8
5.0
6.1
1.4
3.7
14.1
2.5
3.0
0.7
1.8
4.8
IOL
4.5
5.0
10
15
2.2
2.6
6.5
19.2
1.8
2.1
5.5
16.1
2.1
2.3
6.2
25
1.2
1.3
3.8
11.2
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IQ
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc

Per Package)
(CL = 50 pF on all outputs)
(All outputs switching,
50% Duty Cycle)
IT
5.0
10
15
ThreeState Output Leakage

Current
ITL
15
Vin = VDD
(VO = 1.4 or 3.6 Vdc)

(VO = 2.8 or 7.2 Vdc)
(VO = 3.5 or 11.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
0.1
Adc
3.0
http://onsemi.com
238
Adc
MC14503B

Characteristic
Symbol
All Types
VDD
VCC
Typ (8.)
Max
5.0
10
15
45
23
18
90
45
35
5.0
10
15
45
23
18
90
45
35
5.0
10
15
75
35
25
150
70
50
5.0
10
15
75
35
25
150
70
50
Unit
Output Rise Time

tTLH = (0.3 ns/pF) CL + 8.0 ns
tTLH = (0.2 ns/pF) CL + 8.0 ns
tTLH
ns
Output Fall Time

tTHL = (0.3 ns/pF) CL + 8.0 ns
tTHL = (0.2 ns/pF) CL + 8.0 ns
tTHL
TurnOff Delay Time, all Outputs

tPLH
TurnOn Delay Time, all Outputs

tPHL
3State Propagation Delay Time

tPHZ
5.0
10
15
75
40
35
150
80
70
ns
tPLZ
5.0
10
15
80
40
35
160
80
70
ns
High Impedance to 1 Level
tPZH
5.0
10
15
65
25
20
130
50
40
ns
High Impedance to 0 Level
tPZL
5.0
10
15
100
35
25
200
70
50
ns
ns
ns
ns
DISABLE
INPUT
20 ns
20 ns
VDD
90%
VDD
16
50%
INPUT
INPUT
OUTPUT
VSS
90%
OUTPUT
CL
tTLH
tPLH

(tTLH, tTHL, tPHL, and tPLH)
http://onsemi.com
239
VSS
tPHL
tPLH
PULSE
GENERATOR
10%
VOH
50%
10%
VOL
tTHL
tPHL
MC14503B
DISABLE INPUT
DISABLE INPUT
PULSE
GENERATOR
VDD
tPHZ, tPZH CIRCUIT
tPLZ, tPZL CIRCUIT
PULSE
GENERATOR
VDD
16
16
OUTPUT
INPUT
1k
8
VSS
OUTPUT
INPUT
CL
20 ns
VSS
20 ns
VDD
90%
50%
DISABLE INPUT
1k
10%
tPZL
tPLZ
VOH
90%
10%
OUTPUT FOR tPZH, tPZL CIRCUIT
VSS
VOL + 0.05 V
tPHZ
tPZH
OUTPUT FOR tPHZ, tPLZ CIRCUIT
VOH 0.15 V
90%
10%
Figure 2. 3State AC Test Circuit and Waveforms

(tPLZ, tPHZ, tPZH, tPZL)
http://onsemi.com
240
VOL
CL
MC14504B
Hex Level Shifter for TTL to
CMOS or CMOS to CMOS
The MC14504B is a hex noninverting level shifter using CMOS
technology. The level shifter will shift a TTL signal to CMOS logic
levels for any CMOS supply voltage between 5 and 15 volts. A control
input also allows interface from CMOS to CMOS at one logic level to
another logic level: Either up or down level translating is
accomplished by selection of power supply levels VDD and VCC. The
VCC level sets the input signal levels while VDD selects the output
voltage levels.
http://onsemi.com
MARKING
DIAGRAMS
16
UP Translates from a Low to a High Voltage or DOWN Translates
PDIP16
P SUFFIX
CASE 648
from a High to a Low Voltage

Input Threshold Can Be Shifted for TTL Compatibility
No Sequencing Required on Power Supplies or Inputs for Power Up
or Power Down
3 to 18 Vdc Operation for VDD and VCC
Diode Protected Inputs to VSS
MC14504BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14504B
AWLYWW
1
16
TSSOP16
DT SUFFIX
CASE 948F
14
504B
ALYW

Symbol
Parameter
Value
Unit
VCC
0.5 to +18.0
VDD
0.5 to +18.0
Vin
Input Voltage Range

(DC or Transient)
0.5 to +18.0
Vout

(DC or Transient)
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Iin, Iout
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
16
SOEIAJ16
F SUFFIX
CASE 966
MC14504B
AWLYWW
1
may occur.
241
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14504BCP
PDIP16
2000/Box
MC14504BD
SOIC16
48/Rail
MC14504BDR2
SOIC16
2500/Tape & Reel
MC14504BDT
TSSOP16
96/Rail
MC14504BF
SOEIAJ16
See Note 1.
MC14504BFEL
SOEIAJ16
See Note 1.


MC14504B/D
MC14504B
PIN ASSIGNMENT
VCC
16
VDD
Aout
15
Fout
Ain
14
Fin
Bout
13
MODE
Bin
12
Eout
Cout
11
Ein
Cin
10
Dout
VSS
Din
LOGIC DIAGRAM
VCC
VDD
LEVEL
SHIFTER
INPUT
OUTPUT
TTL/CMOS
MODE SELECT
MODE
Mode Select
Input Logic
Levels
Output Logic
Levels
1 (VCC)
TTL
CMOS
0 (VSS)
CMOS
CMOS
1/6 of package shown.
http://onsemi.com
242
MC14504B
55_C
25_C
VCC
Vdc
VDD
Vdc
Min
Max
Min
VOL
5.0
10
15
0.05
0.05
0.05
VOH
5.0
10
15
4.95
9.95
14.95
5.0
5.0
5.0
5.0
10
10
15
10
15
15
5.0
5.0
5.0
5.0
10
10
15
10
15
15
IOL
Input Current
125_C
Max
Min
Max
Unit
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0.8
0.8
1.5
1.5
3.0
1.3
1.3
2.25
2.25
4.5
0.8
0.8
1.5
1.5
3.0
0.8
0.8
1.4
1.5
2.9
2.0
2.0
3.6
3.6
7.1
2.0
2.0
3.5
3.5
7.0
1.5
1.5
2.75
2.75
5.5
2.0
2.0
3.5
3.5
7.0
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Iin
15
0.1
0.00001
0.1
1.0
Adc
Cin
5.0
7.5
pF
IDD or
ICC
5.0
10
15
0.05
0.10
0.20
0.0005
0.0010
0.0015
0.05
0.10
0.20
1.5
3.0
6.0
Adc
Quiescent Current
(Per Package)
TTLCMOS Mode
IDD
5.0
5.0
5.0
5.0
10
15
0.5
1.0
2.0
0.0005
0.0010
0.0015
0.5
1.0
2.0
3.8
7.5
15
Adc
Quiescent Current
(Per Package)
TTLCMOS Mode
ICC
5.0
5.0
5.0
5.0
10
15
5.0
5.0
5.0
2.5
2.5
2.5
5.0
5.0
5.0
6.0
6.0
6.0
mAdc
Characteristic
Output Voltage
Vin = 0 V
Symbol
0 Level
1 Level
Vin = VCC
Input Voltage
0 Level
(VOL = 1.0 Vdc) TTLCMOS
(VOL = 1.5 Vdc) TTLCMOS
(VOL = 1.0 Vdc) CMOSCMOS
VIL
Input Voltage
1 Level
(VOH = 9.0 Vdc) TTLCMOS
(VOH = 13.5 Vdc) TTLCMOS
(VOH = 9.0 Vdc) CMOSCMOS
VIH

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Quiescent Current
(Per Package)
CMOSCMOS Mode
Source
Sink
Typ
(4.)
Vdc
Vdc
mAdc
http://onsemi.com
243
MC14504B

Characteristic
Propagation Delay, High to Low
Propagation Delay, Low to High
Limits
Symbol
Shifting Mode
VCC
Vdc
VDD
Vdc
Min
Typ (5.)
Max
Unit
tPHL
TTL CMOS
VDD > VCC
5.0
5.0
10
15
140
140
280
280
ns
CMOS CMOS
VDD > VCC
5.0
5.0
10
10
15
15
120
120
70
240
240
140
CMOS CMOS
VCC > VDD
10
15
15
5.0
5.0
10
185
185
175
370
370
350
TTL CMOS
VDD > VCC
5.0
5.0
10
15
170
160
340
320
CMOS CMOS
VDD > VCC
5.0
5.0
10
10
15
15
170
170
100
340
340
200
CMOS CMOS
VCC > VDD
10
15
15
5.0
5.0
10
275
275
145
550
550
290
ALL
5.0
10
15
100
50
40
200
100
80
tPLH
tTLH, tTHL
http://onsemi.com
244
ns
ns
MC14504B
7
VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)
VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)
7
6
VCC = 10 V
5
4
3
VCC = 5 V
2
1
6
5
4
3
2
1
0
0
5
10
15
VDD, SUPPLY VOLTAGE (Vdc)
20
Figure 1. Input Switchpoint CMOS to CMOS Mode

20
20
15
10
5
10
15
20
Figure 2. Input Switchpoint TTL to CMOS Mode
VCC = 5 V
15
10
0
0
5
10
15
VCC, SUPPLY VOLTAGE (Vdc)
20
Figure 3. Operating Boundary CMOS to CMOS Mode
5
10
15
VCC, SUPPLY VOLTAGE (Vdc)
20
Figure 4. Operating Boundary TTL to CMOS Mode
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245
MC14511B
BCD-To-Seven Segment
Latch/Decoder/Driver
The MC14511B BCDtoseven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output drivers in a single monolithic structure.
The circuit provides the functions of a 4bit storage latch, an 8421
BCDtoseven segment decoder, and an output drive capability. Lamp
test (LT), blanking (BI), and latch enable (LE) inputs are used to test the
display, to turnoff or pulse modulate the brightness of the display, and
to store a BCD code, respectively. It can be used with sevensegment
lightemitting diodes (LED), incandescent, fluorescent, gas discharge,
or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.
Low Logic Circuit Power Dissipation

HighCurrent Sourcing Outputs (Up to 25 mA)
Latch Storage of Code
Blanking Input
Lamp Test Provision
Readout Blanking on all Illegal Input Combinations
Lamp Intensity Modulation Capability
Time Share (Multiplexing) Facility
Capable of Driving Two Lowpower TTL Loads, One Lowpower
Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range
Chip Complexity: 216 FETs or 54 Equivalent Gates
Triple Diode Protection on all Inputs
MAXIMUM RATINGS (Voltages Referenced to VSS) (2.)

Symbol
Parameter
Value
Unit
0.5 to +18.0
VDD
Vin
Input Voltage Range, All Inputs
0.5 to VDD + 0.5
DC Current Drain per Input Pin
10
mA
PD
Power Dissipation,
per Package (3.)
500
mW
TA
55 to +125
Tstg
16
PDIP16
P SUFFIX
CASE 648
MC14511BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14511B
AWLYWW
1
16
14511B
SOIC16
DW SUFFIX
CASE 751G
AWLYYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966
MC14511B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Shipping
MC14511BCP
PDIP16
2000/Box
MC14511BD
SOIC16
48/Rail
65 to +150
MC14511BDW
SOIC16
47/Rail
MC14511BDWR2
SOIC16
1000/Tape & Reel
MC14511BF
SOEIAJ16
See Note 1.
MC14511BFEL
SOEIAJ16
See Note 1.
Maximum Output Drive Current

(Source) per Output
25
mA
POHmax
Maximum Continuous Output

Power (Source) per Output (4.)
50
mA
may occur.
4. POHmax = IOH (VDD VOH)
March, 2000 Rev. 3
MARKING
DIAGRAMS
Package
IOHmax
http://onsemi.com
246
Device


MC14511B/D
MC14511B
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this highimpedance circuit. A
(Vin or Vout)
VDD.
destructive high current mode may occur if Vin and Vout are not constrained to the range VSS
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to VSS and are at a
logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
PIN ASSIGNMENT
B
16
VDD
15
LT
14
BI
13
LE
12
11
10
VSS
a
f
b
c
DISPLAY
TRUTH TABLE
LE BI LT
X X 0
X 0 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
1
1 1
Inputs
D
C
X
X
X
X
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
X
X
B
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
A
X
X
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
X
a
1
0
1
0
1
1
0
1
0
1
1
1
0
0
0
0
0
0
b
1
0
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
c
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
d
1
0
1
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
*
Outputs
e
f
1
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
1
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
X = Dont Care
* Depends upon the BCD code previously applied when LE = 0
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247
g
1
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
Display
8
Blank
0
1
2
3
4
5
6
7
8
9
Blank
Blank
Blank
Blank
Blank
Blank
*
MC14511B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (5.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.1
9.1
14.1
4.1
9.1
14.1
4.57
9.58
14.59
4.1
9.1
14.1
Vdc
Input Voltage #
0 Level
(VO = 3.8 or 0.5 Vdc)
(VO = 8.8 or 1.0 Vdc)
(VO = 13.8 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
4.1
3.9
3.4
4.1
3.9
3.4
4.57
4.24
4.12
3.94
3.70
3.54
4.1
3.5
3.0
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
10
9.1
9.0
8.6
9.1
9.0
8.6
9.58
9.26
9.17
9.04
8.90
8.70
9.1
8.6
8.2
Vdc
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
15
14.1
14
13.6
14.1
14
13.6
14.59
14.27
14.18
14.07
13.95
13.70
14.1
13.6
13.2
Vdc
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
Vin = 0 or VDD
(VO = 0.5 or 3.8 Vdc)

(VO = 1.0 or 8.8 Vdc)
(VO = 1.5 or 13.8 Vdc)
Output Drive Voltage
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)

(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
Vdc
Vdc
VOH
Source
Vdc
IOL
Sink
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
(Per Package) Vin = 0 or VDD,
Iout = 0 A
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15


Noise Margin for both 1 and 0 level =
1.0 Vdc min @ VDD = 5.0 Vdc
IT(CL) = IT(50 pF) + 3.5 x 103 (CL 50) VDDf
where: IT is in A (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
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248
Adc
MC14511B

Characteristic
Symbol
VDD
Vdc
Min
Typ
Max
5.0
10
15
40
30
25
80
60
50
5.0
10
15
125
75
65
250
150
130
5.0
10
15
640
250
175
1280
500
350
5.0
10
15
720
290
200
1440
580
400
5.0
I0
15
600
200
150
750
300
220
5.0
10
15
485
200
160
970
400
320
5.0
10
15
313
125
90
625
250
180
Unit
Output Rise Time

tTLH = (0.25 ns/pF) CL + 17.5 ns
tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 37.5 ns
tTHL = (0.55 ns/pF) CL + 37.5 ns
tTHL
Data Propagation Delay Time

tPLH = (0.40 ns/pF) CL + 620 ns
tPLH = (0.25 ns/pF) CL + 237.5 ns
tPLH = (0.20 ns/pF) CL + 165 ns
tPLH

tPHL = (0.60 ns/pF) CL + 260 ns
tPHL = (0.35 ns/pF) CL + 182.5 ns
tPHL
Blank Propagation Delay Time

tPLH = (0.30 ns/pF) CL + 585 ns
tPLH = (0.25 ns/pF) CL + 187.5 ns
tPLH = (0.15 ns/pF) CL + 142.5 ns
tPLH
tPHL = (0.85 ns/pF) CL + 442.5 ns

tPHL = (0.45 ns/pF) CL + 177.5 ns
tPHL = (0.35 ns/pF) CL + 142.5 ns
tPHL
Lamp Test Propagation Delay Time

tPLH = (0.45 ns/pF) CL + 290.5 ns
tPLH = (0.25 ns/pF) CL + 112.5 ns
tPLH

tPHL = (0.45 ns/pF) CL + 102.5 ns
tPHL = (0.35 ns/pF) CL + 72.5 ns
tPHL
5.0
10
15
313
125
90
625
250
180
Setup Time
tsu
5.0
10
15
100
40
30
ns
Hold Time
th
5.0
10
15
60
40
30
ns
tWL
5.0
10
15
520
220
130
260
110
65
ns
Latch Enable Pulse Width
ns
ns
ns
ns
ns
8. The formulas given are for the typical characteristics only.
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249
MC14511B
Input LE low, and Inputs D, BI and LT high.
f in respect to a system clock.
All outputs connected to respective CL loads.
20 ns
20 ns
90%
50%
1
2f
A, B, AND C
VDD
10%
VSS
50% DUTY CYCLE
VOH
50%
ANY OUTPUT
VOL
Figure 1. Dynamic Power Dissipation Signal Waveforms
20 ns
20 ns
VDD
90%
50%
10%
INPUT C
VSS
tPHL
tPLH
VOH
90%
50%
OUTPUT g
10%
VOL
tTHL
tTLH
(a) Inputs D and LE low, and Inputs A, B, BI and LT high.
20 ns
LE
VDD
90%
50%
10%
th
VSS
tsu
VDD
INPUT C
50%
VSS
VOH
OUTPUT g
VOL
(b) Input D low, Inputs A, B, BI and LT high.
20 ns
20 ns
LE
VDD
90%
50%
10%
tWL
(c) Data DCBA strobed into latches.

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250
VSS
MC14511B
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIGHT EMITTING DIODE (LED) READOUT
VDD
VDD
COMMON
ANODE LED
COMMON
CATHODE LED
1.7 V
1.7 V
VSS
VSS
INCANDESCENT READOUT
VDD
FLUORESCENT READOUT
VDD
VDD
**
DIRECT
(LOW BRIGHTNESS)
FILAMENT
SUPPLY
VSS
VSS
VSS OR APPROPRIATE
VOLTAGE BELOW VSS.
(CAUTION: Maximum working voltage = 18.0 V)
GAS DISCHARGE READOUT
VDD
LIQUID CRYSTAL (LCD) READOUT
APPROPRIATE
VOLTAGE
EXCITATION
(SQUARE WAVE,
VSS TO VDD)
VDD
1/4 OF MC14070B
VSS
VSS
** A filament prewarm resistor is recommended to reduce filament

thermal shock and increase the effective cold resistance of the
filament.
Direct dc drive of LCDs not recommended for life of

LCD readouts.
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251
MC14511B
LOGIC DIAGRAM
BI 4
13 a
A 7
12 b
11 c
B 1
10 d
9 e
15 f
C 2
14 g
LT 3
D 6
LE 5
VDD = PIN 16
VSS = PIN 8
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252
MC14512B
8-Channel Data Selector
The MC14512B is an 8channel data selector constructed with
single monolithic structure. This data selector finds primary
application in signal multiplexing functions. It may also be used for
data routing, digital signal switching, signal gating, and number
sequence generation.
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Single Supply Operation
3State Output (Logic 1, Logic 0, High Impedance)
MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MC14512BCP
AWLYYWW
1
16

Symbol
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
VDD
Vin, Vout
Iin, Iout
Parameter
(DC or Transient)
14512B
AWLYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966
MC14512B
AWLYWW
1
may occur.
to the range VSS
(Vin or Vout)
VDD.
SOIC16
D SUFFIX
CASE 751B
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14512BCP
PDIP16
2000/Box
MC14512BD
SOIC16
48/Rail
MC14512BDR2
SOIC16
2500/Tape & Reel
MC14512BF
SOEIAJ16
See Note 1.
MC14512BFL1
SOEIAJ16
See Note 1.

March, 2000 Rev. 3
253

MC14512B/D
MC14512B
TRUTH TABLE
C
Inhibit
Disable
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
X0
X1
X2
X3
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
X4
X5
X6
X7
X
X
X
X
X
X
1
X
0
1
0
High
Impedance
X = Dont Care
PIN ASSIGNMENT
X0
16
VDD
X1
15
DIS
X2
14
X3
13
X4
12
X5
11
X6
10
INH
VSS
X7
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254
MC14512B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
ITL
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
0.1
Adc
3.0
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255
Adc
MC14512B
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C, See Figure 1)
All Types
Characteristic
Symbol

tTLH,
tTHL
Propagation Delay Time (Figure 2)

Inhibit, Control, or Data to Z
tPLH
Propagation Delay Time (Figure 2)

Inhibit, Control, or Data to Z
tPHL
3State Output Delay Times (Figure 3)

1 or 0 to High Z, and
High Z to 1 or 0
tPHZ, tPLZ,
tPZH, tPZL
VDD
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
330
125
85
650
250
170
5.0
10
15
330
125
85
650
250
170
5.0
10
15
60
35
30
150
100
75
ns
ns
ns
ID
Vin
50%
50%
DUTY
CYCLE
PULSE
GENERATOR
DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
CL
256
VDD
VSS
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Unit
ns
MC14512B
VDD
20 ns
20 ns
PULSE
GENERATOR
tPLH
CL
VDD
90%
50%
10%
DATA
DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
VSS
tPHL
90%
50%
10%
VOL
tTLH
tTHL
TEST CONDITIONS:
INHIBIT = VSS
A, B, C = VSS
20 ns
INHIBIT,
A, B, OR C
VSS
20 ns
tPHL
Parameter
Test Conditions
Inhibit to Z
A, B, C = VSS, XO = VDD
A, B, C to Z
Inh = VSS, XO = VDD
VDD
90%
50%
10%
VSS
90%
50%
10%
tPLH
VDD
VDD
S3
S4
VSS
20 ns
VDD
DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
DISABLE
INPUT
CL
1k
S1
20 ns
90%
50%
10%
S2
tPZL
VOH
90%
VOL
tPZH
10%
OUTPUT
tPHZ
VSS
OUTPUT
VOH
90%
10%
Switch Positions for 3State Test
VSS
Test
S1
S2
S3
S4
tPHZ
tPLZ
tPZL
tPZH
Open
Closed
Closed
Open
Closed
Open
Open
Closed
Closed
Open
Open
Closed
Open
Closed
Closed
Open
Figure 3. 3State AC Test Circuit and Waveform
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257
VDD
VSS
tPLZ
VOL
VOH
VOL
tTLH
tTHL
Figure 2. AC Test Circuit and Waveforms
PULSE
GENERATOR
VOH
2.5 V @ VDD = 5 V,
10 V, AND 15 V
2 V @ VDD = 5 V
6 V @ VDD = 10 V
10 V @ VDD = 15 V
MC14512B
LOGIC DIAGRAM
C
B
A
X0
X1
X2
13
12
15
11
1
DISABLE
10
INHIBIT
VDD
X4
IOD
MC14512B
IL
14
X3
DATA
BUS
SELECTED
DEVICE
LOAD
ITL
Z
MC14512B
5
ITL
X5
X6
X7
MC14512B
VSS
7
9
1
OUT
IN
IN
2
TRANSMISSION
GATE
OUT
2
3STATE MODE OF OPERATION

Output terminals of several MC14512B 8Bit Data
Selectors can be connected to a single date bus as shown.
One MC14512B is selected by the 3state control, and the
remaining devices are disabled into a highimpedance off
state. The number of 8bit data selectors, N, that may be
connected to a bus line is determined from the output drive
current, IOD, 3state or disable output leakage current, ITL,
and the load current, IL, required to drive the bus line
(including fanout to other device inputs), and can be

calculated by:
N=
IOD IL
+1
ITL
N must be calculated for both high and low logic state of the
bus line.
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258
MC14513B
BCD-To-Seven Segment
Latch/Decoder/Driver
CMOS MSI
(LowPower Complementary MOS)
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constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output drivers in a single monolithic structure.
The circuit provides the functions of a 4bit storage latch, an 8421
BCDtoseven segment decoder, and has output drive capability. Lamp
test (LT), blanking (BI), and latch enable (LE) inputs are used to test the
display, to turnoff or pulse modulate the brightness of the display, and
to store a BCD code, respectively. The Ripple Blanking Input (RBI) and
Ripple Blanking Output (RBO) can be used to suppress either leading
or trailing zeroes. It can be used with sevensegment light emitting
diodes (LED), incandescent, fluorescent, gas discharge, or liquid crystal
readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display
Low Logic Circuit Power Dissipation

Highcurrent Sourcing Outputs (Up to 25 mA)
Latch Storage of Binary Input
Blanking Input
Lamp Test Provision
Readout Blanking on all Illegal Input Combinations
Lamp Intensity Modulation Capability
Time Share (Multiplexing) Capability
Adds Ripple Blanking In, Ripple Blanking Out to MC14511B
Capable of Driving Two LowPower TTL Loads, One Lowpower
Schottky TTL Load to Two HTL Loads Over the Rated Temperature
Range.
MAXIMUM RATINGS (Voltages Referenced to VSS) (1.)

Symbol
Parameter
VDD
Vin
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5
DC Current Drain per Input Pin
10
mA
PD
Power Dissipation,
per Package (2.)
500
mW
TA
55 to +125
Tstg
65 to +150
IOHmax

Drive Current (Source) per Output
25
mA
POHmax

Power (Source) per Output (3.)
50
mW
March, 2000 Rev. 3
259
MARKING
DIAGRAMS
18
PDIP18
P SUFFIX
CASE 707
MC14513BCP
AWLYYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
MC14513BCP
Package
Shipping
PDIP18
20/Rail
This device contains protection circuitry to protect

the inputs against damage due to high static voltages
or electric fields. However, it is advised that normal
precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high
impedance circuit. A destructive high current mode
may occur if Vin and Vout are not constrained to the
range VSS
(Vin or Vout)
VDD.
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the
outputs are shorted to VSS and are at a logical 1 (See
Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
1. Maximum Ratings are those values beyond which

damage to the device may occur.
Plastic P and D/DW Packages: 7.0 mW/_C
From 65_C To 125_C
3. POHmax = IOH (VDD VOH)

MC14513B/D
MC14513B
PIN ASSIGNMENT
B
18
VDD
17
LT
16
BI
15
LE
14
13
12
RBI
VSS
11
10
RBO
a
f
b
c
DISPLAY
TRUTH TABLE
Inputs
RBI
X
X
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
LE BI
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Outputs
LT
D C B A RBO a b c d e
Display
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
1
0
0
1
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
8
Blank
Blank
0
1
2
3
4
5
6
7
8
9
Blank
Blank
Blank
Blank
Blank
Blank
*
X
X
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
X
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
X
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
+
+
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
0
1
1
1
1
1
0
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0
*
1
0
0
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
0
X = Dont Care
RBO = RBI (D C B A), indicated by other rows of table
*Depends upon the BCD code previously applied when LE = 0
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2
MC14513B
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
5.0
10
15
4.1
9.1
14.1
4.1
9.1
14.1
5.0
10
15
4.1
9.1
14.1
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
4.1
3.9
3.4
4.1
3.9
3.4
4.57
4.24
4.12
3.94
3.70
3.54
4.1
3.5
3.0
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
10
9.1
9.0
8.6
9.1
9.0
8.6
9.58
9.26
9.17
9.04
8.90
8.75
9.1
8.6
8.2
Vdc
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
15
14.1
14
13.6
14.1
14
13.6
14.59
14.27
14.18
14.07
13.95
13.80
14.1
13.6
13.2
Vdc
Characteristic
Symbol
Output Voltage Segment Outputs

0 Level
Vin = VDD or 0
VOL
1 Level
VOH
Output Voltage RBO Output

0 Level
Vin = VDD or 0
VOL
1 Level
VOH
Input Voltage (4.)

0 Level
(VO = 3.8 or 0.5 Vdc)
(VO = 8.8 or 1.0 Vdc)
(VO = 13.8 or 1.5 Vdc)
VIL

(VO = 1.0 or 8.8 Vdc)
(VO = 1.5 or 13.8 Vdc)
VIH
Output Drive Voltage Segments

(IOH = 0 mA)
Source
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
VOH
Vin = 0 or VDD
Vin = 0 or VDD
Unit
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
(continued)
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261
MC14513B
ELECTRICAL CHARACTERISTICS continued (Voltages Referenced to VSS)

Characteristic
Symbol
Output Drive Current RBO Output

Source
(VOH = 2.5 V)
(VOH = 9.5 V)
(VOH = 13.5 V)
IOH
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
5.0
10
15
0.40
0.21
0.81
0.32
0.17
0.66
0.64
0.34
1.30
0.22
0.12
0.46
5.0
10
15
0.18
0.47
1.80
0.15
0.38
1.50
0.29
0.75
2.90
0.10
0.26
1.0
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
Unit
mAdc
Sink
IOL
Output Drive Current Segments

(VOL = 0.4 V)
Sink
(VOL = 0.5 V)
(VOL = 1.5 V)
IOL
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
Iout = 0 A
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
mAdc
mAdc


Noise Margin for both 1 and 0 level =
1.0 Vdc min @ VDD = 5.0 Vdc
where: IT is in A (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
Input LE and RBI low, and Inputs D, BI and LT high.

20 ns
20 ns
A, B, AND C
90%
50%
1
2f
VDD
10%
50% DUTY CYCLE

ANY OUTPUT
VSS
VOH
50%
VOL
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262
Adc
MC14513B

Characteristic
Symbol
Output Rise Time Segment Outputs
All Types
VDD
Vdc
Min
Typ
Max
5.0
10
15
40
30
25
80
60
50
5.0
10
15
480
240
190
960
480
380
5.0
10
15
125
75
65
250
150
130
5.0
10
15
270
135
110
540
270
220
5.0
10
15
640
250
175
1280
500
350
5.0
10
15
720
290
200
1440
580
400
5.0
10
15
600
200
150
750
300
220
5.0
10
15
485
200
160
970
400
320
5.0
10
15
313
125
90
625
250
180
tTLH
Output Rise Time RBO Output
ns
tTLH
Output Fall Time Segment Outputs (7.)

tTHL = (0.75 ns/pF) CL + 37.5 ns
tTHL = (0.55 ns/pF) CL + 37.5 ns
tTHL
Output Fall Time RBO Outputs

tTHL = (3.25 ns/pF) CL + 107.5 ns
tTHL = (1.35 ns/pF) CL + 67.5 ns
tTHL = (0.95 ns/pF) CL + 62.5 ns
tTHL
Propagation Delay Time A, B, C, D Inputs (7.)

tPLH = (0.40 ns/pF) CL + 620 ns
tPLH = (0.25 ns/pF) CL + 237.5 ns
tPLH = (0.20 ns/pF) CL + 165 ns
tPLH

tPHL = (0.60 ns/pF) CL + 260 ns
tPHL = (0.35 ns/pF) CL + 182.5 ns
tPHL
Propagation Delay Time RBI and BI Inputs (7.)

tPLH = (1.05 ns/pF) CL + 547.5 ns
tPLH = (0.45 ns/pF) CL + 177.5 ns
tPLH = (0.30 ns/pF) CL + 135 ns
tPLH
Unit
ns
ns
ns
ns
ns
ns
tPHL = (0.85 ns/pF) CL + 442.5 ns

tPHL = (0.45 ns/pF) CL + 177.5 ns
tPHL = (0.35 ns/pF) CL + 142.5 ns
tPHL
Propagation Delay Time LT Input (7.)

tPLH = (0.45 ns/pF) CL + 290.5 ns
tPLH = (0.25 ns/pF) CL + 112.5 ns
tPLH

tPHL = (0.45 ns/pF) CL + 102.5 ns
tPHL = (0.35 ns/pF) CL + 72.5 ns
tPHL
5.0
10
15
313
125
90
625
250
180
ns
Setup Time
tsu
5.0
10
15
100
40
30
ns
Hold Time
th
5.0
10
15
60
40
30
ns
tWL(LE)
5.0
10
15
520
220
130
260
110
65
ns
Latch Enable Pulse Width
ns
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263
ns
MC14513B
20 ns
VDD
20 ns
90%
50%
10%
INPUT C
VSS
tPHL
tPLH
VOH
OUTPUT g
VOL
tTHL
tTLH
a. Data Propagation Delay: Inputs RBI, D and LE low, and Inputs A, B, BI and LT high.
20 ns
20 ns
VDD
90%
50%
10%
INPUT C
tPLH
VSS
tPHL
VOH
90%
OUTPUT RBO
50%
10%
VOL
tTHL
tTLH
b. Inputs A, B, D and LE low, and Inputs RBI, BI and LT high.
20 ns
VDD
90%
50%
LE
10%
th
tsu
INPUT C
VSS
VDD
50%
VSS
VOH
OUTPUT g
VOL
c. Setup and Hold Times: Input RBI and D low, Inputs A, B, BI and LT high.
20 ns
20 ns
90%
50%
LE
VDD
10%
VSS
tWL(LE)
d. Pulse Width: Data DCBA strobed into latches.

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264
MC14513B
VDD
VDD
COMMON
ANODE LED
COMMON
CATHODE LED
1.7 V
1.7 V
VSS
VSS
VDD
FLUORESCENT READOUT
VDD
VDD
**
DIRECT
(LOW BRIGHTNESS)
FILAMENT
(SUPPLY)
VSS
VSS

VDD
VSS OR APPROPRIATE
VOLTAGE BELOW VSS.
LIQUID CRYSTAL (LC) READOUT
APPROPRIATE
VOLTAGE
EXCITATION
(SQUARE WAVE,
VSS TO VDD)
VDD
1/4 OF MC14070B
VSS
VSS
** A filament prewarm resistor is recommended to reduce

filament thermal shock and increase the effective cold
resistance of the filament.
Direct dc drive of LCs not recommended for life of LC readouts.
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265
MC14513B
LOGIC DIAGRAM
BI 4
15 a
A 7
14 b
13 c
B 1
12 d
11 e
17 f
C 2
16 g
LT 30
D 6
10 RBO
RBI 8
LE 5
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266
MC14513B
TYPICAL APPLICATIONS FOR RIPPLE BLANKING
LEADING EDGE ZERO SUPPRESSION
DISPLAYS
a g
a g
CONNECT TO
RBI
VDD (1) D C
RBI
D C
RBO
1
B A
RBI
D C
MC14513B
MC14513B
INPUT
CODE
a g
RBO
a g
RBO
RBI
D C
MC14513B
0
(0)
(0)
a g
RBO
D C
MC14513B
1
(5)
a g
RBO
RBI
B
D C
MC14513B
0
(0)
RBO
RBI
B
MC14513B
(1)
(3)
TRAILING EDGE ZERO SUPPRESSION

DISPLAYS
a g
RBO
RBI
B A
D C
a g
0
RBO
D C
0
(5)
RBO
D C
MC14513B
MC14513B
0
a g
RBI
0
(0)
a g
RBI
B
RBO
D C
MC14513B
0
a g
RBO
RBI
B
D C
MC14513B
1
(1)
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0
(0)
CONNECT TO
RBI
D C
MC14513B
1
(3)
267
a g
RBO
RBI
VDD (1)
MC14513B
0
0
(0)
0
INPUT CODE
MC14514B, MC14515B
4-Bit Transparent
Latch/4-to-16 Line Decoder
The MC14514B and MC14515B are two output options of a 4 to 16
line decoder with latched inputs. The MC14514B (output active high
option) presents a logical 1 at the selected output, whereas the
MC14515B (output active low option) presents a logical 0 at the
selected output. The latches are RS type flipflops which hold the
last input data presented prior to the strobe transition from 1 to 0.
These high and low options of a 4bit latch/4 to 16 line decoder are
constructed with Nchannel and Pchannel enhancement mode
devices in a single monolithic structure. The latches are RS type
flipflops and data is admitted upon a signal incident at the strobe
input, decoded, and presented at the output.
These complementary circuits find primary use in decoding
applications where low power dissipation and/or high noise immunity
is desired.
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MARKING
DIAGRAMS
24
PDIP24
P SUFFIX
CASE 709

MC145XXBCP
AWLYYWW
1
24

Parameter
Symbol
VDD
Vin, Vout

(DC or Transient)
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5
10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
(Vin or Vout)
VDD.
to the range VSS
March, 2000 Rev. 3
XX
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
may occur.
145XXB
AWLYYWW
1

Iin, Iout
SOIC24
DW SUFFIX
CASE 751E
268
Package
Shipping
MC14514BCP
PDIP24
15/Rail
MC14514BDW
SOIC24
30/Rail
MC14514BDWR2
SOIC24
1000/Tape & Reel
MC14515BCP
PDIP24
15/Rail
MC14515BDW
SOIC24
30/Rail
MC14515BDWR2
SOIC24
1000/Tape & Reel

MC14514B/D
MC14514B, MC14515B
PIN ASSIGNMENT
ST
24
VDD
D1
23
INH
D2
22
D4
S7
21
D3
S6
20
S10
S5
19
S11
S4
18
S8
S3
17
S9
S1
16
S14
S2
10
15
S15
S0
11
14
S12
VSS
12
13
S13
DECODE TRUTH TABLE (Strobe = 1)*

Selected Output
Data Inputs
Inhibit
MC14514 = Logic 1
MC14515 = Logic 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
S0
S1
S2
S3
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
S4
S5
S6
S7
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
S8
S9
S10
S11
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
S12
S13
S14
S15
All Outputs = 0, MC14514

All Outputs = 1, MC14515
X = Dont Care
*Strobe = 0, Data is latched
BLOCK DIAGRAM
VDD = PIN 24
VSS = PIN 12
DATA 1
DATA 2
DATA 3
DATA 4
STROBE
INHIBIT
B
TRANSPARENT
21
C
LATCH
22
4 TO 16
DECODER
23
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269
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
11
9
10
8
7
6
5
4
18
17
20
19
14
13
16
15
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
MC14514B, MC14515B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
ITL
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
mAdc

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270
Adc
MC14514B, MC14515B
All Types
Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL
Propagation Delay Time; Data, Strobe to S

tPLH,
tPHL
Inhibit Propagation Delay Times

tPLH,
tPHL
Setup Time
Data to Strobe
tsu
Hold Time
Strobe to Data
th
Strobe Pulse Width
VDD
Min
Typ (7.)
Max
5.0
10
15
180
90
65
360
180
130
5.0
10
15
100
50
40
200
100
80
5.0
10
15
550
225
150
1100
450
300
5.0
10
15
400
150
100
800
300
200
5.0
10
15
250
100
75
125
50
38
5.0
10
15
20
0
10
100
40
30
5.0
10
15
350
100
75
175
50
38
ns
ns
ns
ns
ns
tWH
VDD
VDS
STROBE
INHIBIT
For MC14514B
1. For Pchannel: Inhibit = VSS
1. and D1D4 constitute
1. binary code for output
1. under test.
2. For Nchannel: Inhibit = VDD
D1
D2
D3
D4
For MC14515B
1. For Pchannel: Inhibit = VDD
2. For Nchannel: Inhibit = VSS
2. and D1D4 constitute binary
2. code for output under test.
ID
EXTERNAL
POWER SUPPLY
VSS
Figure 1. Drain Characteristics Test Circuit
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271
ns
ns
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
Unit
MC14514B, MC14515B
VDD
0.01 F
CERAMIC
ID
24
500
F
VDD
20 ns
20 ns
PULSE
GENERATOR
D1
S0
D2
D3
D4
STROBE
INHIBIT S15
12
CL
VDD
90%
Vin
10%
VSS
CL
VSS
Figure 2. Dynamic Power Dissipation Test Circuit and Waveform
VDD
STROBE
OUTPUT S0
OUTPUT S1
S0
S1
INHIBIT
PROGRAMMABLE
PULSE
GENERATOR
CL
tTLH
tTHL
20 ns
CL
INPUT
D1
10%
VSS
tPHL
VDD
tPLH
D2
90%
50%
10%
OUTPUT
D3
D4
VDD
90%
50%
OUTPUT S15
S15
VSS
CL
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272
tTLH
VSS
tTHL
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273
INHIBIT 23
STROBE 1
DATA 4 22
DATA 3 21
DATA 2 3
DATA 1 2
R
S
R
S
LOGIC DIAGRAM
IN MC14515B ONLY
AB CD
AB CD
AB CD
AB CD
AB CD
AB CD
AB CD
AB CD
AB CD
AB CD
AB CD
AB CD
AB CD
AB CD
AB CD
AB CD
15 S15
16 S14
13 S13
14 S12
19 S11
20 S10
17 S9
18 S8
4 S7
5 S6
6 S5
7 S4
8 S3
10 S2
9 S1
11 S0
MC14514B, MC14515B
MC14514B, MC14515B
COMPLEX DATA ROUTING
times faster then the shift frequency of the input registers,
the most significant bit (MSB) from each register could be
selected for transfer to the data bus. Therefore, all of the
most significant bits from all of the registers can be
transferred to the data bus before the next most significant
bit is presented for transfer by the input registers.
Information from the 3state bus is redistributed by the
MC14514B fourbit latch/decoder. Using the fourbit
address, D1 thru D4, the information on the inhibit line can
be transferred to the addressed output line to the desired
output registers, A thru P. This distribution of data bits to the
output registers can be made in many complex patterns. For
example, all of the most significant bits from the input
registers can be routed into output register A, all of the next
most significant bits into register B, etc. In this way
horizontal, vertical, or other methods of data slicing can be
implemented.
Two MC14512 eightchannel data selectors are used here

with the MC14514B fourbit latch/decoder to effect a
complex data routing system. A total of 16 inputs from data
registers are selected and transferred via a 3state data bus
to a data distributor for rearrangement and entry into 16
output registers. In this way sequential data can be rerouted
or intermixed according to patterns determined by data
select and distribution inputs.
Data is placed into the routing scheme via the eight inputs
on both MC14512 data selectors. One register is assigned to
each input. The signals on A0, A1, and A2 choose one of
eight inputs for transfer out to the 3state data bus. A fourth
signal, labelled Dis, disables one of the MC14512 selectors,
assuring transfer of data from only one register.
In addition to a choice of input registers, 1 thru 16, the rate
of transfer of the sequential information can also be varied.
That is, if the MC14512 were addressed at a rate that is eight
DATA ROUTING SYSTEM
REGISTER 1
D0
D1
D2
D3
D4
D5
D6
DIS
3STATE
DATA BUS
DATA
DISTRIBUTION
OUTPUT
REGISTERS
D1 D2 D3 D4
S0
STROBE
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
INHIBIT
S14
S15
D7
A0 A1 A2
REGISTER A
MC14514B
REGISTER 8
DATA
TRANSFER
MC14512
INPUT
REGISTERS
DATA
SELECT
A0 A1 A2
D0
Q
D1
D2
D3
D4
D5
D6
D7
DIS
MC14512
REGISTER 9
REGISTER 16
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274
REGISTER P
MC14516B
Binary Up/Down Counter

The MC14516B synchronous up/down binary counter is
constructed with MOS Pchannel and Nchannel enhancement mode
devices in a monolithic structure.
This counter can be preset by applying the desired value, in binary,
to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset
Enable (PE) high. The direction of counting is controlled by applying
a high (for up counting) or a low (for down counting) to the
UP/DOWN input. The state of the counter changes on the positive
transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high
to the reset (R) pin.
This CMOS counter finds primary use in up/down and difference
counting. Other applications include: (1) Frequency synthesizer
applications where low power dissipation and/or high noise immunity
is desired, (2) Analogtodigital and digitaltoanalog conversions,
and (3) Magnitude and sign generation.

Internally Synchronous for High Speed
Logic EdgeClocked Design Count Occurs on Positive Going
Edge of Clock
Single Pin Reset
Asynchronous Preset Enable Operation
Schottky Load Over the Rated Temperature Range
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MC14516BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14516B
AWLYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966
MC14516B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Symbol
VDD
Vin, Vout
Iin, Iout
PD
Parameter
(DC or Transient)
Device
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
may occur.
March, 2000 Rev. 3
275
Package
Shipping
MC14516BCP
PDIP16
2000/Box
MC14516BD
SOIC16
48/Rail
MC14516BDR2
SOIC16
2500/Tape & Reel
MC14516BF
SOEIAJ16
See Note 1.
MC14516BFEL
SOEIAJ16
See Note 1.

range VSS
(Vin or Vout)
VDD.

MC14516B/D
MC14516B
PIN ASSIGNMENT
PE
16
VDD
Q3
15
P3
14
Q2
P0
13
P2
CARRY IN
12
P1
Q0
11
Q1
CARRY OUT
10
U/D
VSS
BLOCK DIAGRAM
1
PE
CARRY IN
RESET
10
UP/DOWN
15
CLOCK
P0
12
P1
13
P2
P3
Q0
Q1
11
Q2
14
Q3
CARRY
OUT
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Carry In
Up/Down
Preset
Enable
Reset
Clock
Action
No Count
Count Up
Count Down
Preset
Reset
X = Dont Care
NOTE: When counting up, the Carry Out signal is normally high and is low only
when Q0 through Q3 are high and Carry In is low. When counting down,
Carry Out is low only when Q0 through Q3 and Carry In are low.
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276
MC14516B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

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277
Adc
MC14516B
All Types
Characteristic
Symbol

tTLH,
tTHL

Clock to Q
tPLH,
tPHL
Clock to Carry Out

tPLH,
tPHL
Carry In to Carry Out

tPLH,
tPHL
Preset or Reset to Q
tPLH,
tPHL
Preset or Reset to Carry Out

tPLH,
tPHL
VDD
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
315
130
100
630
260
200
5.0
10
15
315
130
100
630
260
200
5.0
10
15
180
80
60
360
160
120
5.0
10
15
315
130
100
630
360
200
5.0
10
15
550
225
150
1100
450
300
ns
ns
ns
ns
Reset Pulse Width
tw
5.0
10
15
380
200
160
190
100
80
ns
Clock Pulse Width
tWH
5.0
10
15
350
170
140
200
100
75
ns
fcl
5.0
10
15
3.0
6.0
8.0
1.5
3.0
4.0
MHz
8. Data labelled Typ is not to be used for design purposes but is intended as an Indication of the ICs potential performance.
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278
MC14516B
SWITCHING CHARACTERISTICS (9.) (CL = 50 pF, TA = 25_C) (continued)
All Types
Symbol
VDD
Min
Typ (10.)
Max
Unit
Preset or Reset Removal Time

The Preset or Reset signal must be low prior to a
positivegoing transition of the clock.
trem
5.0
10
15
650
230
180
325
115
90
ns
tTLH,
tTHL
5.0
10
15
15
5
4
Setup Time
Carry In to Clock
tsu
5.0
10
15
260
120
100
130
60
50
ns
Hold Time
Clock to Carry In
th
5.0
10
15
0
20
20
60
20
0
ns
Setup Time
Up/Down to Clock
tsu
5.0
10
15
500
200
150
250
100
75
ns
Hold Time
Clock to Up/Down
th
5.0
10
15
70
10
0
160
60
40
ns
Setup Time
Pn to PE
tsu
5.0
10
15
40
30
25
120
70
50
ns
Hold Time
PE to Pn
th
5.0
10
15
480
420
420
240
210
210
ns
tWH
5.0
10
15
200
100
80
100
50
40
ns
Characteristic
10. Data labelled Typ is not to be used for design purposes but is intended as an Indication of the ICs potential performance.
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279
MC14516B
VDD
500 pF
0.01 F
CERAMIC
ID
PE
Q0
CARRY IN
R
Q1
UP/DOWN
PULSE
GENERATOR
CLOCK
20 ns
20 ns
CL
Q2
Q3
P3
CARRY
OUT
10%
VARIABLE
WIDTH
CL
P0
P1
P2
VDD
90%
50%
CLOCK
CL
CL
CL

LOGIC DIAGRAM
P0
4
RESET
PRESET
ENABLE
Q0
6
P1 Q1
12 11
P2
13
Q2
14
P3
3
CLOCK 15
PE
PE
PE
7
T
CARRY IN
C
CARRY OUT
PE
UP/DOWN 10
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280
Q3
2
VSS
MC14516B
TOGGLE FLIPFLOP
FLIPFLOP FUNCTIONAL TRUTH TABLE
PARALLEL IN
PE
Preset
Enable
Clock
Qn+1
Parallel In
Qn
Qn
Qn
C
Q
X = Dont Care
tsu
trem
1
fcl
th
CARRY IN OR
UP/DOWN
VDD
50%
VSS
VDD
50%
CLOCK
VSS
tw(H)
tw(H)
VDD
PRESET ENABLE
VSS
tTLH
CARRY OUT ONLY
Q0 OR CARRY OUT
VOH
90%
10%
90%
10%
VOL
tPHL
tTHL
tPLH
tPLH
trem
VDD
50%
RESET
VSS
tw
Figure 2. Switching Time Waveforms
PIN DESCRIPTIONS
INPUTS
CONTROLS
P0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) Data
on these inputs is loaded into the counter when PE is taken
high.
Carry In, (Pin 5) This activelow input is used when
Cascading stages. Carry In is usually connected to Carry Out
of the previous stage. While high, Clock is inhibited.
Clock, (Pin 15) Binary data is incremented or
decremented, depending on the direction of count, on the
positive transition of this input.
PE, Preset Enable, (Pin 1) Asynchronously loads data

on the Preset Inputs. This pin is active high and inhibits the
clock when high.
R, Reset, (Pin 9) Asynchronously resets the Q out
puts to a low state. This pin is active high and inhibits the
clock when high.
Up/Down, (Pin 10) Controls the direction of count,
high for up count, low for down count.
OUTPUTS
VSS, Negative Supply Voltage, (Pin 8) This pin is

usually connected to ground.
VDD, Positive Supply Voltage, (Pin 16) This pin is
connected to a positive supply voltage ranging from 3.0
volts to 18.0 volts.
SUPPLY PINS
Q0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2)

Binary data is present on these outputs with Q0
corresponding to the least significant bit.
Carry Out, (Pin 7) Used when cascading stages, Carry
Out is usually connected to Carry In of the next stage. This
synchronous output is active low and may also be used to
indicate terminal count.
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281
MC14516B
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
PE
Q1
Q2
Q3
Q0
PE
Q1
Q2
Q3
Cout
Cin
PRESET
ENABLE
0 = COUNT
1 = PRESET
Cin
CLOCK
1 = UP
0 = DOWN
L.S.D.
MC14516B
U/D
R
P0
P1
P2
P0
P1
P2
CLOCK
Cout
M.S.D.
MC14516B
P3
U/D
R
P0
P1
P2
P3
P3
P4
P5
P6
P7
+VDD
CLOCK
+VDD
TERMINAL COUNT
INDICATOR
+VDD
THUMBWHEEL SWITCHES
(OPEN FOR 0)
RESISTORS = 10 k
RESET
OPEN = COUNT
NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit (M.S.D.) is disabled while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 15 (count
up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.
(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.
Figure 3. Presettable Cascaded 8Bit Up/Down Counter
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282
283
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COUNT
RESET
CARRY OUT
(LSD)
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CARRY OUT
(MSD)
P0
P1
P2
P3
P4
P5
P6
P7
PE
CARRY IN
(MSD)
UP/DOWN
CLOCK
13
15
16
UP COUNT
PRESET ENABLE
14
17
18
19
18
17
15
DOWN COUNT
16
14
13
PRESET
ENABLE
251
252
UP COUNT
253 254 255
DOWN
COUNT
RESET
UP COUNT
MC14516B
TIMING DIAGRAM FOR THE PRESETTABLE CASCADED 8BIT UP/DOWN COUNTER
MC14516B
fout
BUFFER
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
PE
Q1
Q2
Q3
Q0
PE
Q1
Q2
Q3
Cout
Cin
Cin
CLOCK
L.S.D.
MC14516B
U/D
R
P0
P1
P2
P0
P1
P2
Cout
M.S.D.
MC14516B
CLOCK
P3
U/D
R
P0
P1
P2
P3
P3
P4
P5
P6
P7
+VDD
+VDD
CLOCK (fin)
+VDD
THUMBWHEEL SWITCHES
(OPEN FOR 0)
RESISTORS = 10 k
RESET
fout =
fin
n
OPEN = COUNT
NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example,
the maximum divide ratio of 255 may be obtained by applying a 1111 1111 to the preset inputs P0 to P7. For this divide operation,
both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided.
Figure 4. Programmable Cascaded Frequency Divider
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284
MC14517B
Dual 64-Bit Static Shift
Register
The MC14517B dual 64bit static shift register consists of two
identical, independent, 64bit registers. Each register has separate clock
and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data
at the data input is entered by clocking, regardless of the state of the write
enable input. An output is disabled (open circuited) when the write enable
input is high. During this time, data appearing at the data input as well as
the 16bit, 32bit, and 48bit taps may be entered into the device by
application of a clock pulse. This feature permits the register to be loaded
with 64 bits in 16 clock periods, and also permits bus logic to be used.
This device is useful in time delay circuits, temporary memory storage
circuits, and other serial shift register applications.

Output Transitions Occur on the Rising Edge of the Clock Pulse
Exceedingly Slow Input Transition Rates May Be Applied to the
Clock Input
3State Output at 64thBit Allows Use in Bus Logic Applications
Shift Registers of any Length may be Fully Loaded with 16 Clock
Pulses
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MC14517BCP
AWLYYWW
1
16
14517B
SOIC16
DW SUFFIX
CASE 751G
AWLYYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Symbol
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
VDD
Vin, Vout
Iin, Iout
Parameter
(DC or Transient)
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Device
Package
Shipping
MC14517BCP
PDIP16
2000/Box
MC14517BDW
SOIC16
47/Rail
MC14517BDWR2
SOIC16
1000/Tape & Reel
may occur.
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
285

MC14517B/D
MC14517B
PIN ASSIGNMENT
Q16A
16
VDD
Q48A
15
Q16B
WEA
14
Q48B
CA
13
WEB
Q64A
12
CB
Q32A
11
Q64B
DA
10
Q32B
VSS
DB
FUNCTIONAL TRUTH TABLE (X = Dont Care)

Clock
Write
Enable
Data
16Bit Tap
32Bit Tap
48Bit Tap
64Bit Tap
Content of 16Bit
Displayed
Content of 32Bit
Displayed
Content of 48Bit
Displayed
Content of 64Bit
Displayed
High Impedance
High Impedance
High Impedance
High Impedance
Content of 16Bit
Displayed
Content of 32Bit
Displayed
Content of 48Bit
Displayed
Content of 64Bit
Displayed
High Impedance
High Impedance
High Impedance
High Impedance
Data entered
into 1st Bit
Content of 16Bit
Displayed
Content of 32Bit
Displayed
Content of 48Bit
Displayed
Content of 64Bit
Displayed
Data entered
into 1st Bit
Data at tap
entered into 17Bit
Data at tap
entered into 33Bit
Data at tap
entered into 49Bit
High Impedance
Content of 16Bit
Displayed
Content of 32Bit
Displayed
Content of 48Bit
Displayed
Content of 64Bit
Displayed
High Impedance
High Impedance
High Impedance
High Impedance
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286
MC14517B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
ITL
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
0.1
Adc
3.0
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287
Adc
MC14517B
VDD
Min
Typ (7.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
475
210
140
770
300
215
tWH
5.0
10
15
330
125
100
170
75
60
ns
fcl
5.0
10
15
3.0
6.7
8.3
1.5
4.0
5.3
MHz
tTLH, tTHL
5.0
10
15
Data to Clock Setup Time
tsu
5.0
10
15
0
10
15
40
15
0
ns
Data to Clock Hold Time
th
5.0
10
15
150
75
35
75
25
10
ns
Write Enable to Clock Setup Time
tsu
5.0
10
15
400
200
110
170
65
50
ns
Write Enable to Clock Release Time
trel
5.0
10
15
380
180
100
160
55
40
ns
Characteristic
Symbol

tTLH, tTHL

tPLH, tPHL
Clock Pulse Width
Unit
ns
ns
See Note (8.)
8. When shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than the rise and fall
time of the data outputs, driving data inputs, plus the propagation delay of the output driving stage.
VDD
REPETITIVE WAVEFORM
CL
WE
CL
VSS
D
C
VDD
D
(f = 1/2 fo)
CL
Q16 Q32 Q48 Q64
D
C
VDD
fo
CL
VSS
WE
Q16 Q32 Q48 Q64
VSS
50 F
ID
CL
CL
CL
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288
CL
MC14517B
Vout = VOH
Vout = VOL
VDD = VGS
VDD = VGS
Q16 Q32 Q48 Q64
D
C
Q16 Q32 Q48 Q64
D
C
WE
WE
D
C
D
C
IOH
WE
IOL
WE
Q16 Q32 Q48 Q64
Q16 Q32 Q48 Q64

EXTERNAL
POWER
SUPPLY
VSS
EXTERNAL
POWER
SUPPLY
VSS
(Output being tested should be in the highlogic state)
(Output being tested should be in the lowlogic state)
Figure 2. Typical Output Source Current

Figure 3. Typical Output Sink Current

tWH
tWL
PIN NOS
16
17
18
90%
19
10%
CLOCK 4 (12)
trel
WRITE 3 (13)
th1
th1
32BIT OUTPUT 6 (10)

33BIT INPUT
tsu1
th1
48BIT OUTPUT 2 (14)

49BIT INPUT
10%
tPHL
tsu0
th0
th1
VDD
90%
50%
tsu1
16BIT OUTPUT 1 (15)
17BIT INPUT
tsu1
VSS
20 ns
tsu0
tPLH
90%
VDD
tsu0
th0
20 ns
tsu0
th0
20 ns
VDD
50%
VSS
VDD
th0
tsu1
DATA IN 7 (9)
tsu
33
tPHL
VDD
tPHL
VDD
tTLH
tPLH
90%
tTLH
tPLH
VSS
VOH
VDD
10%
V
tTHL OL
VOH
50%
10%
VOL
tTHL
VOH
VSS
tTLH
tPHL
20 ns
50%
tPLH
tTHL
VDD
VSS
VDD
VSS
VOL
VDD
64BIT OUTPUT 5 (11)

tTLH
VSS
tTHL
Figure 4. AC Test Waveforms

EXPANDED BLOCK DIAGRAM (1/2 OF DEVICE SHOWN)
CLOCK
DATA
WRITE
ENABLE
D
C
D
C
D
Q
C 16
3STATE
WRITE ENABLE = 0, 16BIT OUTPUT

WRITE ENABLE = 1, 17BIT INPUT
D
Q
C 17
WE
D
Q
C 32
3STATE
32BIT OUTPUT
33BIT INPUT
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289
D
Q
C 33
WE
D
Q
C 48
3STATE
48BIT OUTPUT
49BIT INPUT
D
Q
C 49
WE
D
C 64 Q
3STATE
64BIT OUTPUT
HIGH IMPEDANCE
MC14518B
Dual Up Counters
The MC14518B dual BCD counter and the MC14520B dual binary
counter are constructed with MOS Pchannel and Nchannel
enhancement mode devices in a single monolithic structure. Each
consists of two identical, independent, internally synchronous 4stage
counters. The counter stages are type D flipflops, with
interchangeable Clock and Enable lines for incrementing on either the
positivegoing or negativegoing transition as required when
cascading multiple stages. Each counter can be cleared by applying a
high level on the Reset line. In addition, the MC14518B will count out
of all undefined states within two clock periods. These complementary
MOS up counters find primary use in multistage synchronous or
ripple counting applications requiring low power dissipation and/or
high noise immunity.
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MC14518BCP
AWLYYWW
1

Internally Synchronous for High Internal and External Speeds
Logic EdgeClocked Design Incremented on Positive Transition
of Clock or Negative Transition on Enable
16
14518B
SOIC16
DW SUFFIX
CASE 751G
AWLYYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966

Symbol
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
VDD
Vin, Vout
Iin, Iout
Parameter
(DC or Transient)
may occur.
to the range VSS
(Vin or Vout)
VDD.
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14518BCP
PDIP16
2000/Box
MC14518BDW
SOIC16
47/Rail
MC14518BDWR2
SOIC16
1000/Tape & Reel
MC14518BF
SOEIAJ16
See Note 1.
MC14518BFEL
SOEIAJ16
See Note 1.

March, 2000 Rev. 3
MC14518B
AWLYWW
290

MC14518B/D
MC14518B
PIN ASSIGNMENT
CA
16
VDD
EA
15
RB
Q0A
14
Q3B
Q1A
13
Q2B
Q2A
12
Q1B
Q3A
11
Q0B
RA
10
EB
VSS
CB
BLOCK DIAGRAM
CLOCK
1
Q0
Q1
Q2
2
ENABLE
3
4
Q3
5
6
Q0
11
Q1
Q2
Q3
12
7
CLOCK
9
C
10
ENABLE
13
14
15
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Clock
Enable
Reset
Action
Increment Counter
Increment Counter
No Change
No Change
No Change
No Change
Q0 thru Q3 = 0
0
X
X
0
1
X
X = Dont Care
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291
MC14518B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

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292
Adc
MC14518B
All Types
Characteristic
Symbol

tTLH,
tTHL

Clock to Q/Enable to Q
tPLH,
tPHL
Reset to Q
tPHL = (0.66 ns/pF) CL + 117 ns
tPHL
VDD
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
280
115
80
560
230
160
5.0
10
15
330
130
90
650
230
170
tw(H)
tw(L)
5.0
10
15
200
100
70
100
50
35
ns
fcl
5.0
10
15
2.5
6.0
8.0
1.5
3.0
4.0
MHz
tTHL, tTLH
5.0
10
15
15
5
4
Enable Pulse Width
tWH(E)
5.0
10
15
440
200
140
220
100
70
ns
Reset Pulse Width
tWH(R)
5.0
10
15
280
120
90
125
55
40
ns
trem
5.0
10
15
5
15
20
45
15
5
ns
Clock Pulse Width
Clock or Enable Rise and Fall Time
Reset Removal Time
ns
VDD
500 F
PULSE
GENERATOR
ID
0.01 F
CERAMIC
C Q0
Q1
Q2
E Q3
R
CL
CL
CL
CL
VSS
20 ns
20 ns
50%
90%
10%
VARIABLE
WIDTH
VSS
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293
MC14518B
20 ns
VDD
PULSE
GENERATOR
20 ns
90%
50%
10%
CLOCK
INPUT
Q0
tWH
Q1
E
R
Q2
Q3
CL
CL
VSS
CL
50%
10%
Q
tf
2 3
4 5
7 8
9 10 11 12 13 14 15 16 17 18
2 3
4 5
7 8
9 0 1
7 8
9 0
2 3
4 5
7 8
9 10 11 12 13 14 15 0
1 2
CLOCK
ENABLE
RESET
2 3
4 5
Q0
Q1
Q2
Q3
Q0
MC14520B
tPHL
90%
tr
MC14518B
VSS
tWL
tPLH
CL
VDD
Q1
Q2
Q3
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294
MC14518B
Q0
D
C
Q1
Q2
Q3
RESET
ENABLE
CLOCK
Figure 4. Decade Counter (MC14518B) Logic Diagram

Q0
D
C
Q1
Q2
RESET
ENABLE
CLOCK
Figure 5. Binary Counter (MC14520B) Logic Diagram

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295
Q3
MC14521B
24-Stage Frequency Divider
The MC14521B consists of a chain of 24 flipflops with an input
circuit that allows three modes of operation. The input will function as
a crystal oscillator, an RC oscillator, or as an input buffer for an
external oscillator. Each flipflop divides the frequency of the
previous flipflop by two, consequently this part will count up to 224 =
16,777,216. The count advances on the negative going edge of the
clock. The outputs of the last sevenstages are available for added
flexibility.
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MARKING
DIAGRAMS
All Stages are Resettable

Reset Disables the RC Oscillator for Low Standby Power Drain
RC and Crystal Oscillator Outputs Are Capable of Driving External
16
PDIP16
P SUFFIX
CASE 648
Loads
Test Mode to Reduce Test Time
VDD and VSS Pins Brought Out on Crystal Oscillator Inverter to
Allow the Connection of External Resistors for LowPower
Operation
Schottky TTL Load over the Rated Temperature Range.
1
16
SOIC16
D SUFFIX
CASE 751B
VDD
Vin, Vout
Iin, Iout
PD
Parameter
16
SOEIAJ16
F SUFFIX
CASE 966
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
Power Dissipation,
500
mW

(DC or Transient)
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
may occur.
(Vin or Vout)
VDD.
to the range VSS
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14521BCP
PDIP16
2000/Box
MC14521BD
SOIC16
48/Rail
MC14521BDR2
SOIC16
2500/Tape & Reel
MC14521BF
SOEIAJ16
See Note 1.
MC14521BFEL
SOEIAJ16
See Note 1.
MC14521BFR2
SOEIAJ16
See Note 1.

March, 2000 Rev. 3
MC14521B
AWLYWW
1
Value
14521B
AWLYWW
1

Symbol
MC14521BCP
AWLYYWW
296

MC14521B/D
MC14521B
PIN ASSIGNMENT
VDD
Q24
16
RESET
15
Q23
VSS
14
Q22
OUT 2
13
Q21
VDD
12
Q20
IN 2
11
Q19
10
Q18
IN 1
VSS
BLOCK DIAGRAM
RESET
2
9
IN 1
STAGES
1 THRU 17
6
IN 2
7
OUT 1
5
VDD
VSS
4
OUT2
STAGES
18 THRU 24
Q18 Q19 Q20 Q21 Q22 Q23 Q24
VDD = PIN 16
VSS = PIN 8
10
11
12
13
14
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297
15
Output
Count Capacity
Q18
Q19
Q20
Q21
Q22
Q23
Q24
218 = 262,144
219 = 524,288
220 = 1,048,576
221 = 2,097,152
222 = 4,194,304
223 = 8,388,608
224 = 16,777,216
MC14521B

Characteristic
Symbol
Output Voltage
Vin = VDD or 0
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Source
Pins 4 & 7
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
(VOH = 2.5 Vdc)

Source
(VOH = 4.6 Vdc)
Pins 1, 10,
(VOH = 9.5 Vdc) 11, 12, 13, 14
(VOH = 13.5 Vdc)
and 15
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
mAdc
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Sink

Per Package)
buffers switching)
mAdc

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298
Adc
MC14521B

Characteristic
Symbol
Output Rise and Fall Time (Counter Outputs)

tTLH, tTHL

Clock to Q18
tPHL, tPLH
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
Clock to Q24
Reset to Qn
tPHL = (1.7 ns/pF) CL + 1215 ns
tPHL = (0.66 ns/pF) CL + 467 ns
VDD
Vdc
5.0
10
15
4.5
1.7
1.3
9.0
3.5
2.7
5.0
10
15
6.0
2.2
1.7
12
4.5
3.5
tPHL
5.0
10
15
1300
500
375
2600
1000
750
tWH(cl)
5.0
10
15
385
150
120
140
55
40
ns
fcl
5.0
10
15
3.5
9.0
12
2.0
5.0
6.5
MHz
tTLH, tTHL
5.0
10
15
15
5.0
4.0
tWH(R)
5.0
10
15
1400
600
450
700
300
225
ns
trem
5.0
10
15
30
0
40
200
160
110
ns
Clock Pulse Width
ns
Reset Pulse Width
Reset Removal Time
VDD
500 F
VDD
PULSE
GENERATOR
0.01 F
CERAMIC
ID
IN 2
R
VSS
VDD
Q18
Q19
Q20
Q21
Q22
Q23
Q24
CL
CL
Vin
CL
20 ns
90%
50%
10%
50% DUTY CYCLE
CL
CL
CL
CL
VSS
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299
20 ns
VDD
0V
MC14521B
VDD
VDD
VDD
PULSE
GENERATOR
IN 2
20 ns
CL
CL
tWL
CL
CL
Qn
CL
50%
20 ns
90%
50%
10%
CL
VSS
VSS
20 ns
IN 2
Q18
Q19
Q20
Q21
Q22
Q23
Q24
tWH
90%
10%
tPLH
tTLH
CL
tPHL
tTHL
500 kHz
Circuit
50 kHz
Circuit
Unit
Crystal Characteristics
Resonant Frequency
Equivalent Resistance, RS
500
1.0
50
6.2
kHz
k
External Resistor/Capacitor Values

Ro
CT
CS
47
82
20
750
82
20
k
pF
pF
+ 6.0
+ 2.0
+ 2.0
+ 2.0
ppm
ppm
4.0
+ 100
2.0
+ 120
ppm
ppm
2.0
160
2.0
560
ppm
ppm
Characteristic
VDD
Ro
18 M
CS
CT
VDD
R*
VDD
IN 1 OUT 1
OUT 2
Q18
Q19
IN 2
Q20
Q21
Q22
Q23
R
Q24
VSS
VSS
R*
*Optional for low power operation,

10 k R 70 k.
Figure 3. Crystal Oscillator Circuit
Frequency Stability
of VDD (TA = 25_C)
VDD Change from 5.0 V to 10 V
VDD Change from 10 V to 15 V
of Temperature (VDD = 10 V)
TA Change from 55_C to + 25_C
MC14521 only
Complete Oscillator*
TA Change from + 25_C to + 125_C
MC14521 only
Complete Oscillator*
*Complete oscillator includes crystal, capacitors, and resistors.
Figure 4. Typical Data for Crystal Oscillator Circuit
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300
MC14521B
100
8.0
VDD = 15 V
4.0
TEST CIRCUIT
FIGURE 7
0
10 V
4.0
8.0
5.0 V
20
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS 2RTC)
10
5.0
2.0
1.0
TEST CIRCUIT
FIGURE 7
VDD = 10 V
50
f AS A FUNCTION
OF C
(RTC = 56 k)
(RS = 120 k)
0.5
0.2
12
RTC = 56 k,
C = 1000 pF
16
55
0.1
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25C

RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C
25
0
25
50
75
100
TA, AMBIENT TEMPERATURE (C), DEVICE ONLY
1.0 k
125
0.0001
RS
RTC
10 k
100 k
0.001
0.01
C, CAPACITANCE (F)
1.0 m
0.1

VDD
VDD
C
VDD
VDD
VDD
IN 1
IN 1
IN 2
OUT 1
OUT 2
Q18
Q19
Q20
Q21
Q22
Q23
Q24
VSS
PULSE
GENERATOR
Q18
Q19
Q20
Q21
IN 2
Q22
Q23
Q24
OUT 1
R
OUT 2
VSS
VSS
Figure 7. RC Oscillator Circuit
VSS
Figure 8. Functional Test Circuit
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301
MC14521B
FUNCTIONAL TEST SEQUENCE

Inputs
A test function (see Figure 8) has been

included for the reduction of test time required to
exercise all 24 counter stages. This test function
divides the counter into three 8stage sections,
and 255 counts are loaded in each of the
8stage sections in parallel. All flipflops are
now at a logic
g 1. The counter is now returned
to the normal 24stages in series configuration.
One more pulse is entered into Input 2 (In 2)
which will cause the counter to ripple from an all
1 state to an all 0 state.
Outputs
Comments
Reset
In 2
Out 2
VSS
VDD
Q18 thru
Q24
VDD
Gnd
First 0 to 1 transition
on In 2, Out 2 node.
0
1
0
1
255 0 to 1 transitions
are clocked into this In 2,
Out 2 node.
0
0
0
0
1
1
1
0
G d
Gnd
The 255th 0 to 1
transition.
Counter converted back to

24stages in series mode.
Out 2 converts back to an

output.
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302
Counter is in three 8stage

sections in parallel mode
Counter is reset. In 2 and
Out 2 are connected
together
VDD
Counter ripples from an all

1 state to an all 0 stage.
MC14521B
LOGIC DIAGRAM
VDD
5
RESET
2
IN 1
3
VSS
9
17
18
19
10
Q18
4
OUT 2
6
IN 2
7
OUT 1
STAGES
3 THRU 7
20
11
Q19
21
12
Q20
22
13
Q21
10
23
14
Q22
16
24
15
Q23
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303
STAGES
11 THRU 15
1
Q24
VDD = PIN 16
VSS = PIN 8
MC14526B
Presettable 4-Bit Down
Counters
The MC14526B binary counter is constructed with MOS Pchannel
and Nchannel enhancement mode devices in a monolithic structure.
This device is presettable, cascadable, synchronous down counter
with a decoded 0 state output for dividebyN applications. In
single stage applications the 0 output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade dividebyN
operation with no additional gates required. The Inhibit input allows
disabling of the pulse counting function. Inhibit may also be used as a
negative edge clock.
This complementary MOS counter can be used in frequency
synthesizers, phaselocked loops, and other frequency division
applications requiring low power dissipation and/or high noise
immunity.
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MC14526BCP
AWLYYWW
1
16

Logic EdgeClocked Design Incremented on Positive Transition
14526B
SOIC16
DW SUFFIX
CASE 751G
of Clock or Negative Transition of Inhibit
Asynchronous Preset Enable

AWLYYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966

Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Symbol
VDD
Vin, Vout
Iin, Iout

(DC or Transient)
to the range VSS
(Vin or Vout)
VDD.
Package
Shipping
MC14526BCP
PDIP16
2000/Box
MC14526BDW
SOIC16
47/Rail
MC14526BDWR2
SOIC16
1000/Tape & Reel
SOEIAJ16
See Note 1.
MC14526BF

March, 2000 Rev. 3
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
may occur.
MC14526B
AWLYWW
304

MC14526B/D
MC14526B
PIN ASSIGNMENT
Q3
16
VDD
P3
15
Q2
PE
14
P2
INHIBIT
13
CF
P0
12
CLOCK
11
P1
10
RESET
VSS
Q1
FUNCTION TABLE
Inputs
Output
Resulting
Function
Clock
Reset
Inhibit
Preset
Enable
Cascade
Feedback
X
X
X
H
H
H
X
X
X
L
H
X
L
L
H
L
H
H
Asynchronous
y
reset*
Asynchronous reset
A
Asynchronous
h
reset
Asynchronous preset
L
L
L
L
X
X
L
L
Decrement inhibited
Decrement inhibited
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
No change**
g
(inactive
(
edge)
g )
No change** (inactive edge)
D
Decrement**
**
Decrement**
H
H
X = Dont Care
NOTES:
** Output 0 is low when reset goes high only it PE and CF are low.
** Output 0 is high when reset is low, only if CF is high and count is 0000.
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305
MC14526B
55_C
VDD
25_C
125_C
Symbol
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Characteristic
Output Voltage
Vin = VDD or 0
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

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306
Adc
MC14526B

Characteristic

Propagation Delay Time (Inhibit Used as Negative

Edge Clock)
Clock or Inhibit to Q
Symbol
tTLH,
tTHL
(Figures 4, 5)
VDD
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
ns
tPLH,
tPHL
(Figures 4, 5, 6)
Clock or Inhibit to 0
Unit
ns
5.0
10
15
550
225
160
1100
450
320
5.0
10
15
240
130
100
480
260
200

Pn to Q
tPLH,
tPHL
(Figures 4, 7)
5.0
10
15
260
120
100
520
240
200
ns

Reset to Q
tPHL
250
110
80
500
220
160
ns
(Figure 8)
5.0
10
15
tPHL,
tPLH
(Figures 4, 9)
5.0
10
15
220
100
80
440
200
160
ns
tw
5.0
10
15
250
100
80
125
50
40
ns
2.0
5.0
6.6
1.5
3.0
4.0
MHz
(Figures 4, 5, 6)
5.0
10
15
tr,
tf
(Figures 5, 6)
5.0
10
15
15
5
4
tsu
5.0
10
15
90
50
40
40
15
10
ns
5.0
10
15
30
30
30
15
5
0
ns
5.0
10
15
250
100
80
125
50
40
ns
5.0
10
15
350
250
200
175
125
100
ns
5.0
10
15
10
20
30
110
30
20
ns

Preset Enable to 0
Clock or Inhibit Pulse Width
(Figures 5, 6)
Clock Pulse Frequency (with PE = low)
Clock or Inhibit Rise and Fall Time
Setup Time
Pn to Preset Enable
fmax
(Figure 10)
Hold Time
Preset Enable to Pn
th
(Figure 10)
tw
(Figure 10)
Reset Pulse Width
tw
(Figure 8)
Reset Removal Time
trem
(Figure 8)
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307
MC14526B
VOL
VOH
VDD = VGS
VDD = VGS
CF
PE
P0
P1
P2
P3
RESET
INHIBIT
CLOCK
CF
PE
P0
P1
P2
P3
RESET
INHIBIT
CLOCK
Q0
Q1
Q2
IOH
Q3
0
EXTERNAL
POWER
SUPPLY
VSS
Q0
Q1
Q2
IOL
Q3
0
EXTERNAL
POWER
SUPPLY
VSS


VDD
CF
PE
P0
P1
P2
P3
RESET
INHIBIT
CLOCK
Q0
Q1
Q2
20 ns
CLOCK
TEST POINT
CL
CL
0
VSS
PULSE
GENERATOR
CL
Q3
Q or 0
CL
DEVICE
UNDER
TEST
CL
20 ns
VDD
90%
50%
10%
VSS
VARIABLE
50%
DUTY
CYCLE
WIDTH
CL*
*Includes all probe and jig capacitance.
Figure 3. Power Dissipation
Figure 4. Test Circuit
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308
MC14526B
SWITCHING WAVEFORMS
tr
CLOCK
tf
tf
VDD
90%
50%
10%
tr
VDD
90%
50%
10%
INHIBIT
VSS
VSS
tw
tw
1/fmax
tPHL
tPLH
ANY Q
OR 0
1/fmax
tPLH
90%
50%
10%
ANY Q
OR 0
tTLH
tPHL
90%
50%
10%
tTHL
tTLH
Figure 5.
tTHL
Figure 6.
tw
VDD
RESET
50%
VSS
tr
ANY P
tf
tPHL
VDD
90%
50%
10%
ANY Q
VSS
tPLH
50%
tPHL
trem
ANY Q
VDD
50%
CLOCK
50%
VSS
Figure 7.
Figure 8.
VALID
tr
PRESET
ENABLE
tf
VDD
VDD
90%
50%
10%
ANY P
50%
VSS
GND
tPHL
th
tsu
tPLH
VDD
PRESET
ENABLE
0
50%
50%
VSS
tw
Figure 9.
Figure 10.
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309
MC14526B
PIN DESCRIPTIONS
other than all zeroes, the 0 output is valid after the rising
edge of Preset Enable (when Cascade Feedback is high). See
the Function Table.
Cascade Feedback (Pin 13) If the Cascade Feedback
input is high, a high level is generated at the 0 output when
the count is all zeroes. If Cascade Feedback is low, the 0
output depends on the Preset Enable input level. See the
Function Table.
P0, P1, P2, P3 (Pins 5, 11, 14, 2) These are the preset
data inputs. P0 is the LSB.
Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) These are the
synchronous counter outputs. Q0 is the LSB.
VSS (Pin 8) The most negative power supply potential.
This pin is usually ground.
VDD (Pin 16) The most positive power supply
potential. VDD may range from 3 to 18 V with respect to VSS.
Preset Enable (Pin 3) If Reset is low, a high level on

the Preset Enable input asynchronously loads the counter
with the programmed values on P0, P1, P2, and P3.
Inhibit (Pin 4) A high level on the Inhibit input pre
vents the Clock from decrementing the counter. With Clock
(pin 6) held high, Inhibit may be used as a negative edge
clock input.
Clock (Pin 6) The counter decrements by one for each
rising edge of Clock. See the Function Table for level
requirements on the other inputs.
Reset (Pin 10) A high level on Reset asynchronously
forces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback is
high, causes the 0 output to go high.
0 (Pin 12) The 0 (Zero) output issues a pulse one
clock period wide when the counter reaches terminal count
(Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high and
Preset Enable is low. When presetting the counter to a value
STATE DIAGRAM
MC14526B
0
15
14
13
12
11
10
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310
MC14526B
MC14526B LOGIC DIAGRAM (Binary Down Counter)
P0
Q0
P1
7
Q1
11
P2
9
P3
15
Q3
2
D R
D RQ
D RQ
D RQ
T PE Q
T PE Q
T PE Q
T PE Q
VDD
VDD
CF
Q2
14
13
PE
INHIBIT
4
12
CLOCK
RESET
10
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311
MC14526B
DivideByN, Single Stage
Cascaded, Presettable DivideByN
Figure 11 shows a single stage dividebyN application.

To initialize counting a number, N is set on the parallel
inputs (P0, P1, P2, and P3) and reset is taken high
asynchronously. A zero is forced into the master and slave
of each bit and, at the same time, the 0 output goes high.
Because Preset Enable is tied to the 0 output, preset is
enabled. Reset must be released while the Clock is high so
the slaves of each bit may receive N before the Clock goes
low. When the Clock goes low and Reset is low, the 0
output goes low (if P0 through P3 are unequal to zero).
The counter downcounts with each rising edge of the
Clock. When the counter reaches the zero state, an output
pulse occurs on 0 which presets N. The propagation delays
from the Clocks rising and falling edges to the 0 outputs
rising and falling edges are about equal, making the 0
output pulse approximately equal to that of the Clock pulse.
The Inhibit pin may be used to stop pulse counting. When
this pin is taken high, decrementing is inhibited.
Figure 12 shows a three stage cascade application. Taking

Reset high loads N. Only the first stages Reset pin (least
significant counter) must be taken high to cause the preset
for all stages, but all pins could be tied together, as shown.
When the first stages Reset pin goes high, the 0 output
is latched in a high state. Reset must be released while Clock
is high and time allowed for Preset Enable to load N into all
stages before Clock goes low.
When Preset Enable is high and Clock is low, time must
be allowed for the zero digits to propagate a Cascade
Feedback to the first nonzero stage. Worst case is from the
most significant bit (M.S.B.) to the L.S.B., when the L.S.B.
is equal to one (i.e. N = 1).
After N is loaded, each stage counts down to zero with
each rising edge of Clock. When any stage reaches zero and
the leading stages (more significant bits) are zero, the 0
output goes high and feeds back to the preceding stage.
When all stages are zero, the Preset Enable automatically
loads N while the Clock is high and the cycle is renewed.
N
VDD
fin
VSS
Q0
Q1
Q2
Q3
P0
P1
P2
P3
CF
RESET
INHIBIT
BUFFER
fin
CLOCK
PE
Figure 11. N Counter
LSB
N0 N1 N2 N3
P0 P1 P2 P3
fin
P0 P1 P2 P3
Q0 Q1 Q2 Q3
CLOCK
VSS
MSB
N8 N9 N10 N11
N4 N5 N6 N7
Q0 Q1 Q2 Q3
P0 P1 P2 P3
CLOCK
CLOCK
INHIBIT
RESET
CF
0
PE
VSS
INHIBIT
RESET
CF
0
PE
VSS
INHIBIT
RESET
Q0 Q1 Q2 Q3
VDD
CF
0
PE
VDD
LOAD
N
BUFFER
10 K
fin
VSS
Figure 12. 3 Stages Cascaded
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312
MC14528B
Dual Monostable
Multivibrator
The MC14528B is a dual, retriggerable, resettable monostable
multivibrator. It may be triggered from either edge of an input pulse,
and produces an output pulse over a wide range of widths, the duration
of which is determined by the external timing components, CX and
RX.
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MARKING
DIAGRAMS
Separate Reset Available

Triggerable from Leading or Trailing Edge Pulse
PinforPin Replacement with the MC14538B
16
PDIP16
P SUFFIX
CASE 648
MC14528BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
1

Parameter
Symbol
VDD
Value
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Iin, Iout

(DC or Transient)
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
SOEIAJ16
F SUFFIX
CASE 966
MC14528B
AWLYWW
1
may occur.
16
Unit
0.5 to +18.0
Vin, Vout
14528B
AWLYWW
313
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14528BCP
PDIP16
2000/Box
MC14528BD
SOIC16
48/Rail
MC14528BDR2
SOIC16
2500/Tape & Reel
MC14528BF
SOEIAJ16
See Note 1.
MC14528BFEL
SOEIAJ16
See Note 1.


MC14528B/D
MC14528B
PIN ASSIGNMENT
VSS
16
VDD
CX1/RX1
15
VSS
RESET 1
14
CX2/RX2
A1
13
RESET 2
B1
12
A2
Q1
11
B2
Q1
10
Q2
VSS
Q2
BLOCK DIAGRAM
CX1
1
RX1
2
6
4
A1
5
B1
RESET 1
VDD
Q1
Q1
CX2
RX2
VDD
15
14
10
12
A2
11
B2
RESET 2
Q2
Q2
13
VDD = PIN 16
VSS = PIN 1, PIN 8, PIN 15
RX AND CX ARE EXTERNAL COMPONENTS
ONESHOT SELECTION GUIDE

100 ns
1 ms
10 ms
100 ms
1 ms
10 ms
100 ms
MC14528B
MC14536B
MC14538B
MC14541B
1s
10 s
23 HR
5 MIN.
MC4538A*
*LIMITED OPERATING VOLTAGE (26 V)

TOTAL OUTPUT PULSE WIDTH RANGE
RECOMMENDED PULSE WIDTH RANGE
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314
MC14528B
55_C
VDD
25_C
125_C
Symbol
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
1.2
0.64
1.6
4.2
1.0
0.51
1.3
3.4
1.7
0.88
2.25
8.8
0.7
0.36
0.9
2.4
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
IOL
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
Characteristic
Output Voltage
Vin = VDD or 0
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
mAdc
Source
IOH
Sink
Total Supply Current at an

external load Capacitance (CL)
and at external timing
capacitance (CX), use the
formula (5.)
IT(CL, CX) = [(CL + 0.36CX)VDDf + 2x108

RXCX(VDD2)2f] x 103
where: IT in A (per circuit), CL and CX in pF, RX in megohms,
VDD in Vdc, f in kHz is input frequency.
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315
Adc
MC14528B
Characteristic
Symbol
CX
pF
RX
k
VDD
Vdc
Min
Typ (9.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
325
120
90
650
240
180
5.0
10
15
705
290
210
Unit

tTLH,
tTHL
TurnOff, TurnOn Delay Time A or B to Q or Q

tPLH,
tPHL
15
TurnOff, TurnOn Delay Time A or B to Q or Q

tPLH,
tPHL
1000
Input Pulse Width A or B
tWH
15
5.0
5.0
10
15
150
75
55
70
30
30
ns
tWL
1000
10
5.0
10
15
70
30
30
ns
Output Pulse Width Q or Q

(For CX < 0.01 F use graph for
appropriate VDD level.)
tW
15
5.0
5.0
10
15
550
350
300
ns

(For CX > 0.01 F use formula:
tW = 0.2 RX CX Ln [VDD VSS]) (6.)
tW
10,000
10
5.0
10
15
15
10
15
30
50
55
45
90
95
t1 t2
10,000
10
5.0
10
15
6.0
8.0
8.0
25
35
35
tPLH,
tPHL
15
5.0
5.0
10
15
325
90
60
600
225
170
ns
1000
10
5.0
10
15
1000
300
250
ns
15
5.0
5.0
10
15
0
0
0
ns
1000
10
5.0
10
15
0
0
0
ns
5.0
1000
Pulse Width Match between Circuits in the same

package
Reset Propagation Delay Reset to Q or Q
Retrigger Time
External Timing Resistance

External Timing Capacitance
6.
7.
8.
9.
trr
RX
CX
ns
5.0
ns
10
ns
No Limits
(7.)
RX is in Ohms, CX is in farads, VDD and VSS in volts, PWout in seconds.

If CX > 15 F, Use Discharge Protection Diode DX, per Fig. 9.
The formulas given are for the typical characteristics only at 25_C.
Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
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316
MC14528B
FUNCTION TABLE
Inputs
Reset
Outputs
H
H
H
H
H
H
L
H
L
Not Triggered
Not Triggered
L, H,
L
H
L, H,
Not Triggered
Not Triggered
X
X
X
X
L
H
Not Triggered
VDD
16
VDD
16
IOL
A
B
OPEN
RESET
IOH
VSS
VOL
VOH
RESET
Figure 1. Output Source Current Test Circuit
OPEN
VSS
Figure 2. Output Sink Current Test Circuit
VDD
500 pF
0.1 mF
CERAMIC
ID
RX
RX
CX
CX
20 ns
20 ns
Vin
90%
VDD
A
Vin
10%
CL
RESET
DUTY CYCLE = 50%
Q
CL
CL
CL
RESET
VSS
Figure 3. Power Dissipation Test Circuit and Waveforms
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317
0V
MC14528B
VDD
RX
RX
Characteristics
CX
CX
INPUT CONNECTIONS
*CX = 15 pF
*CL = 15 pF
RX = 5.0 k
PULSE
GENERATOR
Reset
tPLH, tPHL, tTLH, tTHL

tW
VDD
PG1
VDD
tPLH, tPHL, tTLH, tTHL

tW
VDD
VSS
PG2
tPLH(R), tPHL(R), tW
PG3
PG1
PG2
CL
PULSE
GENERATOR
RESET
CL
CL
B
PULSE
GENERATOR
Q
CL
RESET
VSS
*Includes capacitance of probes,

wiring, and fixture parasitic.
PG1 =
NOTE: AC test waveforms for

PG1, PG2, and PG3 on
next page.
PG2 =
PG3 =
Figure 4. AC Test Circuit
tTLH
tWH
VDD
90%
10%
tTHL
50%
50%
tTHL
VSS
tTLH
VDD
90%
10%
50%
VSS
tWL
tTHL
RESET
tTLH
90%
10%
tTHL
tW
50%
tTLH
90%
10%
50%
trr
tPHL
VOH
50%
tTLH
tPHL
VSS
tWL
tPLH
50%
VDD
50%
VOL
tTHL
tPHL
tPHL
Q
50%
50%
VOH
90%
10%
50%
50%
Figure 5. AC Test Waveforms
1000
VDD = 15 V
t W, PULSE WIDTH ( m s)
10 V
5.0 V
100
15 V
10 V
5.0 V
RX = 100 k
15 V
10 V
5.0 V
10
RX = 10 k
W
RX = 5.0 k
1.0
0.1
15 V
10 V
5.0 V
10
100
1000
10,000
CX, EXTERNAL CAPACITANCE (pF)
Figure 6. Pulse Width versus CX
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318
100,000
VOL
MC14528B
Cx
Cx
Rx
Rx
VDD
VDD
RISING EDGE
TRIGGER
Q
RESET
VDD
RISING EDGE
TRIGGER
Q
RESET
VDD
VDD
Cx
Cx
Rx
Rx
VDD
VDD
FALLING EDGE
TRIGGER
Q
RESET
FALLING EDGE
TRIGGER
Q
RESET
VDD
VDD
Figure 7. Retriggerable
Monostables Circuitry
Figure 8. NonRetriggerable
DX
Cx
VDD
NC
1, 15
Rx
2, 14
VDD
NC
Q
RESET
NC
A
Q
B
VDD
Q
RESET
VDD
VDD
Figure 9. Use of a Diode to Limit

Power Down Current Surge
VDD
Figure 10. Connection of Unused Sections
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319
MC14532B
8-Bit Priority Encoder
The MC14532B is constructed with complementary MOS (CMOS)
enhancement mode devices. The primary function of a priority
encoder is to provide a binary address for the active input with the
highest priority. Eight data inputs (D0 thru D7) and an enable input
(Ein) are provided. Five outputs are available, three are address outputs
(Q0 thru Q2), one group select (GS) and one enable output (Eout).
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MC14532BCP
AWLYYWW
1

Symbol
16
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
VDD
Vin, Vout
Iin, Iout
Parameter
(DC or Transient)
14532B
AWLYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966
MC14532B
AWLYWW
1
may occur.
to the range VSS
(Vin or Vout)
VDD.
SOIC16
D SUFFIX
CASE 751B
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14532BCP
PDIP16
2000/Box
MC14532BD
SOIC16
48/Rail
MC14532BDR2
SOIC16
2500/Tape & Reel
MC14532BF
SOEIAJ16
See Note 1.
MC14532BFEL
SOEIAJ16
See Note 1.
MC14532BFR1
SOEIAJ16
See Note 1.

March, 2000 Rev. 3
320

MC14532B/D
MC14532B
PIN ASSIGNMENT
D4
16
VDD
D5
15
Eout
D6
14
GS
D7
13
D3
Ein
12
D2
Q2
11
D1
Q1
10
D0
VSS
Q0
TRUTH TABLE
Input
Output
Ein
D7
D6
D5
D4
D3
D2
D1
D0
GS
Q2
Q1
Q0
Eout
0
1
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
X
1
0
0
X
X
1
0
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
X
1
0
0
X
X
1
0
X
X
X
1
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
0
0
0
0
X = Dont Care
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321
MC14532B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

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322
Adc
MC14532B

Characteristic
Symbol

tTLH,
tTHL
Propagation Delay Time Ein to Eout

tPLH,
tPHL
Propagation Delay Time Ein to GS

tPLH, tPHL = (0.66 ns/pF) CL 57 ns
tPLH,
tPHL
Propagation Delay Time Ein to Qn

tPHL,
tPLH
Propagation Delay Time Dn to Qn

tPLH,
tPHL
Propagation Delay Time Dn to GS

tPLH,
tPHL
VDD
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
205
110
80
410
220
160
5.0
10
15
175
90
65
350
180
130
5.0
10
15
280
140
100
560
280
200
5.0
10
15
300
170
110
600
340
220
5.0
10
15
280
140
100
560
280
200
Unit
ns
ns
ns
ns
ns
ns
Vout
Ein
SWITCH
MATRIX
D0
D1
Eout
D2
D3
Q0
Q1
D4
D5
GS
VDD
Q2
ID
500 F
D6
0.01 F
ID
D7
EXTERNAL
POWER
SUPPLY
Output
Under
Test
Eout
Q0
Q1
Q2
GS
VGS = VDD
VDS = Vout
Sink Current
D0 thru D7
X
X
X
X
X
Ein
0
0
0
0
0
VGS = VDD
VDS = Vout VDD
Source Current
D0 thru D6
0
0
0
0
0
D7
0
1
1
1
1
Ein
1
1
1
1
1
PULSE
GENERATOR
(fo)
Figure 1. Typical Sink and Source

Current Characteristics
Ein
Eout
D0
D1
Q0
D2
D3
Q1
D4
D5
Q2
CL
CL
CL
CL
D6
GS
D7
VSS
CL
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323
MC14532B
VDD
PROGRAMMABLE
PULSE
GENERATOR
Ein
Eout
D0
D1
Q0
D2
D3
Q1
D4
D5
Q2
CL
CL
CL
D6
CL
GS
D7
VSS
CL
NOTE: Input rise and fall times are 20 ns

PIN
NO.
D0
10
D1
11
D2
12
D3
13
D4
D5
D6
D7
Ein
50%
50%
50%
50%
50%
50%
Eout
15
50%
50%
50%
tPLH
tPHL
90%
50%
10%
tTHL
tPLH
tTLH
GS
Q0
14
tTLH
tPLH
tPHL
tPLH
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Q1
7
tPLH
Q2
tTLH
Figure 3. AC Test Circuit and Waveforms
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324
tTLH
tTLH
90%
50%
10%
tTHL
tPHL
90%
50%
10%
tTHL
tPHL
90%
50%
10%
tTHL
tPHL
90%
50%
10%
tTHL
MC14532B
LOGIC DIAGRAM
(Positive Logic)
LOGIC EQUATIONS
Eout = Ein D0 D1 D2 D3 D4 D5 D6 D7
Q0 = Ein (D1 D2 D4 D6 + D3 D4 D6 + D5 D6 + D7)
Q1 = Ein (D2 D4 D5 + D3 D4 D5 + D6 + D7)
10
Q2 = Ein (D4 + D5 + D6 + D7)
D0
GS = Ein (D0 + D1 + D2 + D3 + D4 + 05 + D6 + D7)

11
D1
Q0
12
D2
13
D3
1
D4
7
Q1
2
D5
3
D6
4
D7
6
Q2
5
Ein
14
GS
15
Eout
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325
MC14532B
D15 D14 D13 D12 D11 D10
D7
VDD
D6
D5
D4
D3
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Eout
Ein
D2
Ein
GS
Q2 Q1
Eout = 1
WITH Din = 0
Eout
Q0
Q2 Q1
Q0
3/4 MC14071B
Q3
Q2
Q1
Q0
Figure 4. Two MC14532Bs Cascaded for 4Bit Output
VDD
VSS
CLOCK
INPUT
C
1/2 MC14520B
DIGITAL TO ANALOG CONVERSION
Q1
The digital eightbit word to be converted is applied to the

inputs of the MC14512 with the most significant bit at
X7 and the least significant bit at X0. A clock input of up to
2.5 MHz (at VDD = 10 V) is applied to the MC14520B.
A compromise between Ibias for the MC1710 and R
between N and Pchannel outputs gives a value of R of
33 k ohms. In order to filter out the switching frequencies,
RC should be about 1.0 ms (if R = 33 k ohms, C 0.03 F).
The analog 3.0 dB bandwidth would then be dc to 1.0 kHz.
ANALOG TO DIGITAL CONVERSION
Q2
Q3
1/2 MC14520B
Q4
Q1
Q2
Q3
Q4
DIGITAL INPUT/OUTPUT
D0 D1 D2 D3 D4 D5 D6 D7
VDD
An analog signal is applied to the analog input of the

MC1710. A digital eightbit word known to represent a digitized level less than the analog input is applied to the
MC14512 as in the D to A conversion. The word is incremented at rates sufficient to allow steady state to be reached
between incrementations (i.e. 3.0 ms). The output of the
MC1710 will change when the digital input represents the
first digitized level above the analog input. This word is the
digital representation of the analog word.
8BIT WORD
TO BE CONVERTED
Ein
Q2 Q1 Q0
A
B
C
X7 X6 X5 X4 X3 X2 X1 X0
MC1710
ANALOG
INPUT
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326
R
ANALOG
OUTPUT
STOP
WORD
INCREMENTATION
Figure 5. Digital to Analog and Analog to Digital Converter
MC14512
Z
MC14536B
Programmable Timer
The MC14536B programmable timer is a 24stage binary ripple
counter with 16 stages selectable by a binary code. Provisions for an
onchip RC oscillator or an external clock are provided. An onchip
monostable circuit incorporating a pulsetype output has been
included. By selecting the appropriate counter stage in conjunction
with the appropriate input clock frequency, a variety of timing can be
achieved.
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MARKING
DIAGRAMS
24 FlipFlop Stages Will Count From 20 to 224

Last 16 Stages Selectable By FourBit Select Code
8Bypass Input Allows Bypassing of First Eight Stages
Set and Reset Inputs
Clock Inhibit and Oscillator Inhibit Inputs
OnChip RC Oscillator Provisions
OnChip Monostable Output Provisions
Clock Conditioning Circuit Permits Operation With Very Long Rise
and Fall Times
Test Mode Allows Fast Test Sequence
16
PDIP16
P SUFFIX
CASE 648
MC14536BCP
AWLYYWW
1
16
14536B
SOIC16
DW SUFFIX
CASE 751G
AWLYYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966
1

Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
Symbol
VDD
Vin, Vout
Iin, Iout

(DC or Transient)
MC14536B
AWLYWW
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
TA
55 to +125
MC14536BCP
PDIP16
2000/Box
Tstg
65 to +150
MC14536BDW
SOIC16
47/Rail
TL
Lead Temperature
(8Second Soldering)
260
MC14536BDWR2
SOIC16
1000/Tape & Reel
SOEIAJ16
See Note 1.
may occur.
MC14536BF

to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 5
327

MC14536B/D
MC14536B
PIN ASSIGNMENT
SET
16
VDD
RESET
15
MONO IN
IN 1
14
OSC INH
OUT 1
13
DECODE
OUT 2
12
8BYPASS
11
CLOCK INH
10
VSS
BLOCK DIAGRAM
CLOCK INH.
7
RESET SET 8 BYPASS

2
1 6
OSC. INHIBIT 14
IN1
STAGES 9 THRU 24
Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
STAGES
1 THRU 8
3
4
OUT1
5
OUT2
VDD = PIN 16
VSS = PIN 8
A 9
B 10
C 11
D 12
DECODER
MONOIN 15
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328
MONOSTABLE
MULTIVIBRATOR
13
DECODE
OUT
MC14536B

Characteristic
Symbol
Output Voltage
Vin = VDD or 0
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Source
Pins 4 & 5
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.25
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
Source
Pin 13
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
mAdc
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.010
0.020
0.030
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Sink

Per Package)
buffers switching)
mAdc

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329
Adc
MC14536B

Characteristic
Symbol
Output Rise and Fall Time (Pin 13)

tTLH,
tTHL

Clock to Q1, 8Bypass (Pin 6) High
tPLH,
tPHL
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
3600
1300
1000
5.0
10
15
3.8
1.5
1.1
7.6
3.0
2.3
5.0
10
15
7.0
3.0
2.2
14
6.0
4.5
5.0
10
15
1500
600
450
3000
1200
900
tWH
5.0
10
15
600
200
170
300
100
85
ns
fcl
5.0
10
15
1.2
3.0
5.0
0.4
1.5
2.0
MHz
tTLH,
tTHL
5.0
10
15
tWH
5.0
10
15
tPLH,
tPHL
Reset to Qn
tPHL = (1.7 ns/pF) CL + 1415 ns
tPHL = (0.66 ns/pF) CL + 567 ns
tPHL
Reset Pulse Width
Max
1800
650
450
Clock to Q16
Typ (8.)
tPLH,
tPHL

(50% Duty Cycle)
Min
5.0
10
15
Clock to Q1, 8Bypass (Pin 6) Low

Clock Pulse Width
VDD
ns
No Limit
1000
400
300
500
200
150
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330
ns
MC14536B
PIN DESCRIPTIONS
INPUTS
OSC INHIBIT (Pin 14) A high level on this pin stops

the RC oscillator which allows for very lowpower standby
operation. May also be used, in conjunction with an external
clock, with essentially the same results as the Clock Inhibit
input.
MONOIN (Pin 15) Used as the timing pin for the
onchip monostable multivibrator. If the MonoIn input is
connected to VSS, the monostable circuit is disabled, and
Decode Out is directly connected to the selected Q output.
The monostable circuit is enabled if a resistor is connected
between MonoIn and VDD. This resistor and the devices
internal capacitance will determine the minimum output
pulse widths. With the addition of an external capacitor to
VSS, the pulse width range may be extended. For reliable
operation the resistor value should be limited to the range of
5 k to 100 k and the capacitor value should be limited to
a maximum of 1000 pf. (See figures 3, 4, 5, and 10).
A, B, C, D (Pins 9, 10, 11, 12) These inputs select the
flipflop stage to be connected to Decode Out. (See the truth
tables.)
SET (Pin 1) A high on Set asynchronously forces

Decode Out to a high level. This is accomplished by setting
an output conditioning latch to a high level while at the same
time resetting the 24 flipflop stages. After Set goes low
(inactive), the occurrence of the first negative clock
transition on IN1 causes Decode Out to go low. The
counters flipflop stages begin counting on the second
negative clock transition of IN1. When Set is high, the
onchip RC oscillator is disabled. This allows for very
lowpower standby operation.
RESET (Pin 2) A high on Reset asynchronously
forces Decode Out to a low level; all 24 flipflop stages are
also reset to a low level. Like the Set input, Reset disables
the onchip RC oscillator for standby operation.
IN1 (Pin 3) The devices internal counters advance on
the negativegoing edge of this input. IN1 may be used as an
external clock input or used in conjunction with OUT1 and
OUT2 to form an RC oscillator. When an external clock is
used, both OUT1 and OUT 2 may be left unconnected or
used to drive 1 LSTTL or several CMOS loads.
8BYPASS (Pin 6) A high on this input causes the first
8 flipflop stages to be bypassed. This device essentially
becomes a 16stage counter with all 16 stages selectable.
Selection is accomplished by the A, B, C, and D inputs. (See
the truth tables.)
CLOCK INHIBIT (Pin 7) A high on this input
disconnects the first counter stage from the clocking source.
This holds the present count and inhibits further counting.
However, the clocking source may continue to run.
Therefore, when Clock Inhibit is brought low, no oscillator
startup time is required. When Clock Inhibit is low, the
counter will start counting on the occurrence of the first
negative edge of the clocking source at IN1.
OUTPUTS
OUT1, OUT2 (Pin 4, 5) Outputs used in conjunction

with IN1 to form an RC oscillator. These outputs are
buffered and may be used for 20 frequency division of an
external clock.
DECODE OUT (Pin 13) Output function depends on
configuration. When the monostable circuit is disabled, this
output is a 50% duty cycle square wave during free run.
TEST MODE
The test mode configuration divides the 24 flipflop

stages into three 8stage sections to facilitate a fast test
sequence. The test mode is enabled when 8Bypass, Set and
Reset are at a high level. (See Figure 8.)
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MC14536B
TRUTH TABLES
Input
Input
8Bypass
Stage Selected
for Decode Out
8Bypass
Stage Selected
for Decode Out
10
11
12
13
14
15
16
17
18
10
19
11
20
12
21
13
22
14
23
15
24
16
FUNCTION TABLE
Set
Reset
Clock
Inh
OSC
Inh
No
Change
Advance to
next state
No
Change
No
Change
No
Change
In1
Out 1
Out 2
Decode
Out
Advance to
next state
X = Dont Care
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332
IN1
SET
1
4
OUT 1
OSC INHIBIT
14
OUT 2
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333
7
CLOCK
INHIBIT
En R
S
Q
T 1
RESET
2
STAGES
2 THRU 7
8
15
MONOIN
A
B
C
D
9
10
11
12
T 9
8BYPASS
STAGES
10 THRU
15
16
DECODER
OUT
13
DECODER
STAGES
18 THRU
23
VSS = PIN 8
VDD = PIN 16
17
24
MC14536B
LOGIC DIAGRAM
MC14536B
(For Circuit Diagram See Figure 11 In Application)
8.0
100
4.0
0
10 V
4.0
8.0
5.0 V
12
RTC = 56 k,
C = 1000 pF
16
55
25
*Device Only.
VDD = 10 V
50
VDD = 15 V
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25C

RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C
0
25
50
75
TA, AMBIENT TEMPERATURE (C)*
100
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS 2RTC)
20
10
5.0
2.0
1.0
0.5
f AS A FUNCTION
OF C
(RTC = 56 k)
(RS = 120 k)
0.2
0.1
1.0 k
125
10 k
100 k
0.001
0.01
C, CAPACITANCE (F)
0.0001
1.0 M
0.1

MONOSTABLE CHARACTERISTICS
(For Circuit Diagram See Figure 10 In Application)
100
10
t W, PULSE WIDTH ( s)
FORMULA FOR CALCULATING tW IN

MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 RX CX 0.85
WHERE R IS IN k, CX IN pF.
RX = 100 k
50 k
1.0
10 k
5 k
10

tW = 0.00247 RX CX 0.85
RX = 100 k
50 k
1.0
10 k
5 k
TA = 25C
VDD = 5 V
0.1
TA = 25C
VDD = 10 V
0.1
1.0
10
100
1000
1.0
Figure 3. Typical CX versus Pulse Width

@ VDD = 5.0 V
10
100

@ VDD = 10 V
100
100
10

tW = 0.00247 RX CX 0.85
RX = 100 k
50 k
1.0
10 k
5 k
TA = 25C
VDD = 15 V
0.1
1.0
10
100

@ VDD = 15 V
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334
1000
1000
MC14536B
VDD
500 F
PULSE
GENERATOR
0.01 F
CERAMIC
ID
SET
RESET OUT 1
8BYPASS
IN1
C INH
MONO IN OUT
2
OSC INH
A
B
C
D
CL
VDD
SET
OUT 1
RESET
8BYPASS
IN1
C INH
MONO IN OUT
2
OSC INH
A
B
C
DECODE
OUT
D
CL
PULSE
GENERATOR
DECODE
OUT
CL
VSS
20 ns
20 ns
20 ns
20 ns
50%
IN1
tWL
OUT
tWH
90%
10%
tPLH
50%
tTLH
tTHL
CL
VSS
90%
50%
10%
50%
DUTY CYCLE
Figure 6. Power Dissipation Test

Circuit and Waveform
VDD
Test function (Figure 8) has been included for the

reduction of test time required to exercise all 24 counter
stages. This test function divides the counter into three
8stage sections and 255 counts are loaded in each of the
8stage sections in parallel. All flipflops are now at a 1.
The counter is now returned to the normal 24stages in
series configuration. One more pulse is entered into In1
which will cause the counter to ripple from an all 1 state
to an all 0 state.
PULSE
GENERATOR
SET
RESET OUT 1
8BYPASS
IN1
C INH
MONO IN OUT
2
OSC INH
A
B
C
D
DECODE
OUT
VSS
Figure 8. Functional Test Circuit
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tPHL
MC14536B
Inputs
Outputs
Comments
g are in Reset mode.
All 24 stages
In1
Set
Reset
8Bypass
Decade Out
Q1 thru Q24
Counter is in three 8 stage sections in parallel mode.
First 1 to 0 transition of clock.
1
0
The 255 1 to 0 transition.
Counter converted back to 24 stages in series mode.

Set and Reset must be connected together and simultaneously
go from 1 to 0.
In1 Switches to a 1.
Counter Ripples from an all 1 state to an all 0 state.
255 1 to 0 transitions are clocked in the counter.
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336
MC14536B
+V
16
6
8BYPASS
VDD
OUT 1
A
10 B
11 C
12
2
14
15
1
PULSE
GEN.
7
3
PULSE
GEN.
D
RESET
OUT 2
DECODE OUT
13
OSC INH
MONOIN
SET
CLOCK INH
IN1
CLOCK
VSS
8
IN1
SET
CLOCK INH
DECODE OUT
POWER UP
NOTE: When power is first applied to the device, Decode Out can be either at a high or low state.
On the rising edge of a Set pulse the output goes high if initially at a low state. The output
remains high if initially at a high state. Because Clock Inh is held high, the clock source on
the input pin has no effect on the output. Once Clock Inh is taken low, the output goes low
on the first negative clock transition. The output returns high depending on the 8Bypass,
A, B, C, and D inputs, and the clock input period. A 2n frequency division (where n = the
number of stages selected from the truth table) is obtainable at Decode Out. A 20divided
output of IN1 can be obtained at OUT1 and OUT2.
Figure 9. Time Interval Configuration Using an External Clock, Set,

and Clock Inhibit Functions
(Divideby2 Configured)
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337
MC14536B
+V
6
RX
A
10 B
11 C
12
PULSE
GEN.
2
1
7
15
14
3
CLOCK
8BYPASS
16
VDD
OUT 1
D
OUT 2
DECODE OUT
13
RESET
SET
CLOCK INH
MONOIN
CLOCK INH
IN1
VSS
CX
IN1
RESET
*tw .00247 RX CX0.85
tw in sec
RX in k
CX in pF
DECODE OUT
*tw
POWER UP
NOTE: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. Bringing the Reset
input low enables the chips internal counters. After Reset goes low, the 2n/2 negative transition of the clock input causes
Decode Out to go high. Since the MonoIn input is being used, the output becomes monostable. The pulse width of the
output is dependent on the external timing components. The second and all subsequent pulses occur at 2n x (the clock
period) intervals where n = the number of stages selected from the truth table.
Figure 10. Time Interval Configuration Using an External Clock, Reset,

and Output Monostable to Achieve a Pulse Output
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MC14536B
+V
RS
16
6
8BYPASS
VDD
9
A
10 B
11 C
12
PULSE
GEN.
2
14
15
1
7
3
OUT 1
4
C
RTC
D
OUT 2
RESET
SET
CLOCK INH
MONOIN
CLOCK INH
IN1
VSS
8
DECODE OUT 13
RESET
OUT 1
OUT 2
fosc
DECODE OUT
POWER UP
^ 2.3 R1tc C
Rs Rtc
F = Hz
R = Ohms
C = FARADS
tw
NOTE: This circuit is designed to use the onchip oscillation function. The oscillator frequency is determined by the external R and C components. When power is first applied to the device, Decode Out
initializes to a high state. Because this output is tied directly to the OscInh input, the oscillator is
disabled. This puts the device in a lowcurrent standby condition. The rising edge of the Reset pulse
will cause the output to go low. This in turn causes OscInh to go low. However, while Reset is high,
the oscillator is still disabled (i.e.: standy condition). After Reset goes low, the output remains low
for 2n/2 of the oscillators period. After the part times out, the output again goes high.
Figure 11. Time Interval Configuration Using OnChip RC Oscillator and

Reset Input to Initiate Time Interval
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339
MC14538B
Dual Precision
Retriggerable/Resettable
Monostable Multivibrator
The MC14538B is a dual, retriggerable, resettable monostable
multivibrator. It may be triggered from either edge of an input pulse,
and produces an accurate output pulse over a wide range of widths, the
duration and accuracy of which are determined by the external timing
components, CX and RX.
Output Pulse Width = (Cx) (Rx) where:
Rx is in k
Cx is in F
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MARKING
DIAGRAMS
W
m
Unlimited Rise and Fall Time Allowed on the A Trigger Input

Pulse Width Range = 10 s to 10 s
Latched Trigger Inputs
Separate Latched Reset Inputs
3.0 Vdc to 18 Vdc Operational Limits
Triggerable from Positive (A Input) or NegativeGoing Edge
(BInput)
Pinforpin Compatible with MC14528B and CD4528B (CD4098)
Use the MC54/74HC4538A for Pulse Widths Less Than 10 s with
Supplies Up to 6 V.
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Vin, Vout
Iin, Iout

(DC or Transient)
may occur.
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
1
16
14538B
AWLYWW
1
16
TSSOP16
DT SUFFIX
CASE 948F
14
538B
ALYW
1
16
14538B
SOIC16
DW SUFFIX
CASE 751G
AWLYYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966
Value
VDD
Parameter
MC14538BCP
AWLYYWW
SOIC16
D SUFFIX
CASE 751B

Symbol
16
PDIP16
P SUFFIX
CASE 648
340
MC14538B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14538BCP
PDIP16
2000/Box
MC14538BD
SOIC16
48/Rail
MC14538BDR2
SOIC16
2500/Tape & Reel
MC14538BDT
TSSOP16
96/Rail
MC14538BDTR2
MC14538BDW
SOIC16
47/Rail
MC14538BDWR2
SOIC16
1000/Tape & Reel
MC14538BF
SOEIAJ16
See Note 1.
MC14538BFEL
SOEIAJ16
See Note 1.

MC14538B/D
MC14538B
PIN ASSIGNMENT
VSS
16
VDD
CX/RXA
15
VSS
RESET A
14
CX/RXB
AA
13
RESET B
BA
12
AB
QA
11
BB
QA
10
QB
VSS
QB
BLOCK DIAGRAM
CX
1
4
5
RX
VDD
A
B
Q1
Q1
RESET
3
CX
15
RX
VDD
14
12
Q2
B
11
10
Q2
RESET
13
RX AND CX ARE EXTERNAL COMPONENTS.
VDD = PIN 16
VSS = PIN 8, PIN 1, PIN 15
ONESHOT SELECTION GUIDE

100 ns
MC14528B
MC14536B
MC14538B
1 s
10 s
100 s
1 ms
10 ms
100 ms
1s
10 s
23 HR
5 MIN.
MC14541B
MC4538A*
*LIMITED OPERATING VOLTAGE (2 6 V)
TOTAL OUTPUT PULSE WIDTH RANGE
RECOMMENDED PULSE WIDTH RANGE
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341
MC14538B
55_C
VDD
25_C
125_C
Symbol
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current, Pin 2 or 14
Iin
15
0.05
0.00001
0.05
0.5
Adc
Input Current, Other Inputs
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance, Pin 2 or 14
Cin
25
pF
Input Capacitance, Other Inputs

(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
Q = Low, Q = High
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
Quiescent Current, Active State

(Both) (Per Package)
Q = High, Q = Low
IDD
5.0
10
15
2.0
2.0
2.0
0.04
0.08
0.13
0.20
0.45
0.70
2.0
2.0
2.0
mAdc
IT
5.0
10
Characteristic
Output Voltage
Vin = VDD or 0
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Total Supply Current at an external

load capacitance (CL) and at
external timing network (RX, CX) (5.)
mAdc
IT = (3.5 x 102) RXCXf + 4CXf + 1 x 105 CLf

where: IT in A (one monostable switching only),
where: CX in F, CL in pF, RX in k ohms, and
where: f in Hz is the input frequency.
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Adc
MC14538B

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL

A or B to Q or Q
tPLH,
tPHL
All Types
VDD
Vdc
Min
Typ (7.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
ns
5.0
10
15
300
150
100
600
300
220
5.0
10
15
250
125
95
500
250
190
5
10
15
15
5
4
B Input
5
10
15
300
1.2
0.4
1.0
0.1
0.05
ms
A Input
5
10
15
Reset to Q or Q
Input Rise and Fall Times
Reset
Input Pulse Width

A, B, or Reset
ns
tr, tf
No Limit
tWH,
tWL
5.0
10
15
170
90
80
85
45
40
ns
Retrigger Time
trr
5.0
10
15
0
0
0
ns

Refer to Figures 8 and 9
CX = 0.002 F, RX = 100 k
s
5.0
10
15
198
200
202
210
212
214
230
232
234
CX = 0.1 F, RX = 100 k
5.0
10
15
9.3
9.4
9.5
9.86
10
10.14
10.5
10.6
10.7
ms
CX = 10 F, RX = 100 k
5.0
10
15
0.91
0.92
0.93
0.965
0.98
0.99
1.03
1.04
1.06
5.0
10
15
1.0
1.0
1.0
5.0
5.0
5.0
Pulse Width Match between circuits in

the same package.
CX = 0.1 F, RX = 100 k
100
[(T1 T2)/T1]
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343
MC14538B
OPERATING CONDITIONS
External Timing Resistance
RX
5.0
(8.)
External Timing Capacitance
CX
No
Limit (9.)
8. The maximum usable resistance RX is a function of the leakage of the capacitor CX, leakage of the MC14538B, and leakage due to board
layout and surface resistance. Susceptibility to externally induced noise signals may occur for RX > 1 M..
9. If CX > 15 F, use discharge protection diode per Fig. 11.
VDD
VDD
P1
RX
2 (14)
CX
+
C1
Vref1
1 (15)
ENABLE
+
C2
Vref2
ENABLE
R
Q
OUTPUT
LATCH
S
Q
N1
VSS
4 (12)
6 (10)
7 (9)
CONTROL
5 (11)
B
RESET
QR
S
3 (13)
RESET LATCH
NOTE: Pins 1, 8 and 15 must

be externally grounded
QR
R
Figure 1. Logic Diagram

(1/2 of DevIce Shown)
VDD
500 pF
0.1 F
CERAMIC
ID
RX
RX
VSS
Vin
CX
CX
VSS
CX/RX
RESET
20 ns
CL
20 ns
90%
CL
CL
Vin
10%
CL
RESET
VSS
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344
VDD
0V
MC14538B
VDD
INPUT CONNECTIONS
RX
RX
VSS
PULSE
GENERATOR
RESET
PULSE
GENERATOR
VSS
CX/RX
PULSE
GENERATOR
CL
CL
CL
Q
CL
RESET
Reset
tPLH, tPHL, tTLH, tTHL,

T, tWH, tWL
VDD
PG1
VDD
tPLH, tPHL, tTLH, tTHL,

T, tWH, tWL
VDD
VSS
PG2
tPLH(R), tPHL(R),
tWH, tWL
PG3
PG1
PG2
*CL = 50 pF
CX
CX
Characteristics
VSS
*Includes capacitance of probes,

wiring, and fixture parasitic.
PG1 =
NOTE: Switching test waveforms

for PG1, PG2, PG3 are shown
In Figure 4.
PG2 =
PG3 =
Figure 3. Switching Test Circuit
90%
10%
tTHL
50%
A
tTLH
tWH
50%
tTHL
VDD
tTLH
90%
10%
50%
VDD
tWL
tTHL
RESET
50%
tTHL
tPLH
tPLH
50%
tPHL
50%
tTLH
tPHL
tWL
tTLH
trr
tPHL
50%
tTHL
90%
10%
50%
VDD
50%
90%
10%
50%
tPHL
90%
10%
tPLH
50%
50%
TA = 25C
RX = 100 k
CX = 0.1 F
1.0
0% POINT PULSE WIDTH

VDD = 5.0 V, T = 9.8 ms
VDD = 10 V, T = 10 ms
VDD = 15 V, T = 10.2 ms
0.8
0.6
0.4
0.2
0
NORMALIZED PULSE WIDTH CHANGE

WITH RESPECT TO VALUE AT VDD = 10 V (%)
RELATIVE FREQUENCY OF OCCURRENCE
Figure 4. Switching Test Waveforms
RX = 100 k
CX = 0.1 F
2
1
0
1
2
4 2
0
2
4
T, OUTPUT PULSE WIDTH (%)
Figure 5. Typical Normalized Distribution

of Units for Output Pulse Width
8
9
10
11
12
VDD, SUPPLY VOLTAGE (VOLTS)
13
14
Figure 6. Typical Pulse Width Variation as

a Function of Supply Voltage VDD
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345
15
MC14538B
TOTAL SUPPLY CURRENT ( A)
1000
FUNCTION TABLE
Inputs
RX = 100 k, CL = 50 pF
ONE MONOSTABLE SWITCHING ONLY
100
Reset
VDD = 15 V
5.0 V
10
10 V
1.0
0.1
0.001
0.1
1.0
10
Outputs
H
H
H
H
H
H
L
H
L
Not Triggered
Not Triggered
L, H,
L
H
L, H,
Not Triggered
Not Triggered
X
X
X
X
L
H
Not Triggered
100
OUTPUT DUTY CYCLE (%)
RX = 100 k
CX = 0.1 F
2
1
VDD = 15 V
VDD = 10 V
0
VDD = 5 V
TYPICAL NORMALIZED ERROR

WITH RESPECT TO 25C VALUE AT VDD = 10 V (%)
TYPICAL NORMALIZED ERROR

WITH RESPECT TO 25C VALUE AT VDD = 10 V (%)
Figure 7. Typical Total Supply Current

versus Output Duty Cycle
RX = 100 k
CX = .002 F
3.0
2.0
1.0
0
1.0
VDD = 15 V
VDD = 10 V
2.0
VDD = 5.0 V
3.0
60 40
20
0
20
40
60
80 100
120
140
60 40
Figure 8. Typical Error of Pulse Width

Equation versus Temperature
20
0
20
40
60
80 100
120 140
Figure 9. Typical Error of Pulse Width

Equation versus Temperature
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346
MC14538B
THEORY OF OPERATION
A
2
B
5
RESET
Vref 2
Vref 2
CX/RX
Vref 1
Vref 1
Vref 2
Vref 2
Vref 1
Vref 1
Q
T
Positive edge trigger
Positive edge retrigger (pulse lengthening)
Negative edge trigger
Positive edge retrigger (pulse lengthening)
Positive edge trigger
Figure 10. Timing Operation
TRIGGER OPERATION
RETRIGGER OPERATION
The block diagram of the MC14538B is shown in

Figure 1, with circuit operation following.
As shown in Figure 1 and 10, before an input trigger
occurs, the monostable is in the quiescent state with the Q
output low, and the timing capacitor CX completely charged
to VDD. When the trigger input A goes from VSS to VDD
(while inputs B and Reset are held to VDD) a valid trigger is
recognized, which turns on comparator C1 and Nchannel
transistor N1 . At the same time the output latch is set. With
transistor N1 on, the capacitor CX rapidly discharges toward
VSS until Vref1 is reached. At this point the output of
comparator C1 changes state and transistor N1 turns off.
Comparator C1 then turns off while at the same time
comparator C2 turns on. With transistor N1 off, the capacitor
CX begins to charge through the timing resistor, RX, toward
VDD. When the voltage across CX equals Vref 2, comparator
C2 changes state, causing the output latch to reset (Q goes
low) while at the same time disabling comparator C2 . This
ends at the timing cycle with the monostable in the quiescent
state, waiting for the next trigger.
In the quiescent state, CX is fully charged to VDD causing
the current through resistor RX to be zero. Both comparators
are off with total device current due only to reverse
junction leakages. An added feature of the MC14538B is
that the output latch is set via the input trigger without regard
to the capacitor voltage. Thus, propagation delay from
trigger to Q is independent of the value of CX, RX, or the duty
cycle of the input waveform.
The MC14538B is retriggered if a valid trigger occurs

followed by another valid trigger before the Q output has
returned to the quiescent (zero) state. Any retrigger, after the
timing node voltage at pin 2 or 14 has begun to rise from
Vref 1, but has not yet reached Vref 2, will cause an increase
in output pulse width T. When a valid retrigger is initiated
, the voltage at CX/RX will again drop to Vref 1 before
progressing along the RC charging curve toward VDD. The
Q output will remain high until time T, after the last valid
retrigger.
RESET OPERATION
The MC14538B may be reset during the generation of the

output pulse. In the reset mode of operation, an input pulse
on Reset sets the reset latch and causes the capacitor to be
fast charged to VDD by turning on transistor P1 . When the
voltage on the capacitor reaches Vref 2, the reset latch will
clear, and will then be ready to accept another pulse. It the
Reset input is held low, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will not
change. Since the Q output is reset when an input low level
is detected on the Reset input, the output pulse T can be made
significantly shorter than the minimum pulse width
specification.
POWERDOWN CONSIDERATIONS
Large capacitance values can cause problems due to the

large amount of energy stored. When a system containing
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347
MC14538B
Dx
the MC14538B is powered down, the capacitor voltage may

discharge from VDD through the standard protection diodes
at pin 2 or 14. Current through the protection diodes should
be limited to 10 mA and therefore the discharge time of the
VDD supply must not be faster than (VDD). (C) / (10 mA).
For example, if VDD = 10 V and CX = 10 F, the VDD supply
should discharge no faster than (10 V) x (10 F) / (10 mA)
= 10 ms. This is normally not a problem since power
supplies are heavily filtered and cannot discharge at this rate.
When a more rapid decrease of VDD to zero volts occurs,
the MC14538B can sustain damage. To avoid this possibility
use an external clamping diode, DX, connected as shown in
Fig. 11.
Cx
Rx VDD
VSS
VDD
Q
Q
RESET
Figure 11. Use of a Diode to Limit

Power Down Current Surge
CX
RX
CX
RX
VDD
RISINGEDGE
TRIGGER
A
VDD
RISINGEDGE
A
TRIGGER
B
Q
Q
B = VDD
RESET = VDD
CX
RESET = VDD
CX
RX
VDD
VDD
A = VSS
Q
B
FALLINGEDGE
TRIGGER
RX
A
B
FALLINGEDGE
TRIGGER
RESET = VDD
RESET = VDD
Figure 12. Retriggerable

Figure 13. NonRetriggerable

NC
A
B
NC
NC
CD
VDD
VDD
Figure 14. Connection of Unused Sections
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348
MC14541B
Programmable Timer
The MC14541B programmable timer consists of a 16stage binary
counter, an integrated oscillator for use with an external capacitor and
two resistors, an automatic poweron reset circuit, and output control
logic.
Timing is initialized by turning on power, whereupon the poweron
reset is enabled and initializes the counter, within the specified VDD
range. With the power already on, an external reset pulse can be
applied. Upon release of the initial reset command, the oscillator will
oscillate with a frequency determined by the external RC network. The
16stage counter divides the oscillator frequency (fosc) with the nth
stage frequency being fosc/2n.
Available Outputs 28, 210, 213 or 216
Increments on Positive Edge Clock Transitions
Builtin Low Power RC Oscillator ( 2% accuracy over temperature
range and 20% supply and 3% over processing at < 10 kHz)
Oscillator May Be Bypassed if External Clock Is Available (Apply
external clock to Pin 3)
External Master Reset Totally Independent of Automatic Reset
Operation
Operates as 2n Frequency Divider or Single Transition Timer
Q/Q Select Provides Output Logic Level Flexibility
Reset (auto or master) Disables Oscillator During Resetting to
Provide No Active Power Dissipation
Clock Conditioning Circuit Permits Operation with Very Slow Clock
Rise and Fall Times
Automatic Reset Initializes All Counters On Power Up
Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset
Supply Voltage Range = Disabled (Pin 5 = VDD)
Supply Voltage Range = 8.5 Vdc to 18 Vdc with Auto Reset
Supply Voltage Range = Enabled (Pin 5 = VSS)
Symbol
VDD
Vin, Vout
Parameter
Value
Unit
0.5 to +18.0

(DC or Transient)
0.5 to VDD + 0.5
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PDIP14
P SUFFIX
CASE 646
14
MARKING
DIAGRAMS
MC14541BCP
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A
14541B
AWLYWW
1
14
TSSOP14
DT SUFFIX
CASE 948G
14
541B
ALYW
14
SOEIAJ14
F SUFFIX
CASE 965
1
MC14541B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14541BCP
PDIP14
2000/Box
MC14541BD
SOIC14
55/Rail
MC14541BDR2
SOIC14
2500/Tape & Reel
MC14541BDT
TSSOP14
96/Rail
MC14541BDTR2
MC14541BF
SOEIAJ14
See Note 1.
SOEIAJ14
See Note 1.
Iin
10 (per Pin)
mA
MC14541BFEL
Iout
Output Current (DC or Transient)
45 (per Pin)
mA
PD
Power Dissipation,
500
mW

TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
may occur.
March, 2000 Rev. 6
349

range VSS
(Vin or Vout)
VDD.

MC14541B/D
MC14541B
PIN ASSIGNMENT
Rtc
14
VDD
Ctc
13
RS
12
NC
11
NC
AR
10
MODE
MR
Q/Q SEL
VSS
NC = NO CONNECTION
55_C
VDD
25_C
125_C
Symbol
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
10
15
7.96
4.19
16.3
6.42
3.38
13.2
12.83
6.75
26.33
4.49
2.37
9.24
IOL
5.0
10
15
1.93
4.96
19.3
1.56
4.0
15.6
3.12
8.0
31.2
1.09
2.8
10.9
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Pin 5 is High)
Auto Reset Disabled
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
Auto Reset Quiescent Current

(Pin 5 is low)
IDDR
10
15
250
500
30
82
250
500
1500
2000
Adc
Supply Current (5.) (6.)

(Dynamic plus Quiescent)
ID
5.0
10
15
Characteristic
Output Voltage
Vin = VDD or 0
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc
ID = (0.4 A/kHz) f + IDD

Adc
6. When using the on chip oscillator the total supply current (in Adc) becomes: IT = ID + 2 Ctc VDD f x 103 where ID is in A, Ctc is in pF,
VDD in Volts DC, and f in kHz. (see Fig. 3) Dissipation during poweron with automatic reset enabled is typically 50 A @ VDD = 10 Vdc.
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350
MC14541B

Characteristic
VDD
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
3.5
1.25
0.9
10.5
3.8
2.9
5.0
10
15
6.0
3.5
2.5
18
10
7.5
tWH(cl)
5.0
10
15
900
300
225
300
100
85
ns
fcl
5.0
10
15
1.5
4.0
6.0
0.75
2.0
3.0
MHz
tWH(R)
5.0
10
15
900
300
225
300
100
85
ns
trem
5.0
10
15
420
200
200
210
100
100
ns
Symbol

tTLH,
tTHL
Propagation Delay, Clock to Q (28 Output)

tPLH
tPHL
Propagation Delay, Clock to Q (216 Output)

tPHL
tPLH
Clock Pulse Width
Clock Pulse Frequency (50% Duty Cycle)
MR Pulse Width
Master Reset Removal Time
Unit
ns
VDD
PULSE
GENERATOR
VDD
PULSE
GENERATOR
RS
AR
Q/Q SELECT
MODE
RS
AR
Q/Q SELECT
MODE
A
B
MR
A
B
MR
CL
VSS
CL
VSS
20 ns
(Rtc AND Ctc OUTPUTS ARE LEFT OPEN)

20 ns
RS
20 ns
90% 50%
10%
50%
DUTY CYCLE
20 ns
90% 50%
10%
tPLH
tPHL
50%
Q
tTLH

and Waveform
50%
90%
10%
50%
tTHL

and Waveforms
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351
MC14541B
EXPANDED BLOCK DIAGRAM
A 12
B 13
1 OF 4
MUX
8 Q
Rtc 1
Ctc 2
OSC
RS 3
RESET
AUTO RESET
5
210 213 216

C 8STAGE
COUNTER
RESET
8STAGE 8
2
C
COUNTER
RESET
POWERON
RESET
6
MASTER RESET
10
MODE
9
Q/Q
SELECT
VDD = PIN 14
VSS = PIN 7
FREQUENCY SELECTION TABLE
Number of
Counter Stages
n
13
8192
10
1024
256
16
65536
TRUTH TABLE
State
Count
2n
Pin
Auto Reset,
0
5
Auto Reset
Operating
Auto Reset Disabled
Master Reset, 6
Timer Operational
Master Reset On
Q / Q,
Output Initially Low

After Reset
Output Initially High

After Reset
Mode,
10
Single Cycle Mode
Recycle Mode
TO CLOCK
CIRCUIT
INTERNAL
RESET
2
1
Ctc
RS
RTC
Figure 3. Oscillator Circuit Using RC Configuration
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352
MC14541B
8.0
100
VDD = 15 V
0
10 V
4.0
8.0
5.0 V
12
RTC = 56 k,
C = 1000 pF
16
55
25
VDD = 10 V
50
4.0
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25C

RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C
0
25
50
75
100
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS 2RTC)
20
10
5.0
2.0
1.0
f AS A FUNCTION
OF C
(RTC = 56 k)
(RS = 120 k)
0.5
0.2
0.1
1.0 k
125
0.0001
10 k
100 k
1.0 m
0.001
0.01
C, CAPACITANCE (F)
0.1

Function of Rtc and Ctc
With Auto Reset pin set to a 0 the counter circuit is
initialized by turning on power. Or with power already on,
the counter circuit is reset when the Master Reset pin is set
to a 1. Both types of reset will result in synchronously
resetting all counter stages independent of counter state.
Auto Reset pin when set to a 1 provides a low power
operation.
The RC oscillator as shown in Figure 3 will oscillate with
a frequency determined by the external RC network i.e.,
f=
1
2.3 RtcCtc
and RS 2 Rtc
if (1 kHz
when B is 0, normal counting is interrupted and the 9th

counter stage receives its clock directly from the oscillator
(i.e., effectively outputting 28).
The Q/Q select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q select pin is set to a 0 the Q output is a 0,
correspondingly when Q/Q select pin is set to a 1 the Q
output is a 1.
When the mode control pin is set to a 1, the selected
count is continually transmitted to the output. But, with
mode pin 0 and after a reset condition the RS flipflop (see
Expanded Block Diagram) resets, counting commences,
and after 2n1 counts the RS flipflop sets which causes the
output to change state. Hence, after another 2n1 counts the
output will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to reset
the single cycle operation.
v f v 100 kHz)
where RS 10 k
The time select inputs (A and B) provide a twobit address

to output any one of four counter stages (28, 210, 213 and
216). The 2n counts as shown in the Frequency Selection
Table represents the Q output of the Nth stage of the counter.
When A is 1, 216 is selected for both states of B. However,
DIGITAL TIMER APPLICATION

When Master Reset (MR) receives a positive pulse, the
internal counters and latch are reset. The Q output goes high
and remains high until the selected (via A and B) number of
clock pulses are counted, the Q output then goes low and
remains low until another input pulse is received.
This one shot is fully retriggerable and as accurate as the
input frequency. An external clock can be used (pin 3 is the
clock input, pins 1 and 2 are outputs) if additional accuracy
is needed.
Notice that a setup time equal to the desired pulse width
output is required immediately following initial power up,
during which time Q output will be high.
Rtc
Ctc
NC
RS
AR
MR
INPUT
14
VDD
13
12
11
10
N.C.
MODE
Q/Q
VDD
OUTPUT
tMR
t + tMR
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353
MC14543B
BCD-to-Seven Segment
Latch/Decoder/Driver for
Liquid Crystals
designed for use with liquid crystal readouts, and is constructed with
complementary MOS (CMOS) enhancement mode devices. The
circuit provides the functions of a 4bit storage latch and an 8421
BCDtoseven segment decoder and driver. The device has the
capability to invert the logic levels of the output combination. The
phase (Ph), blanking (BI), and latch disable (LD) inputs are used to
reverse the truth table phase, blank the display, and store a BCD code,
respectively. For liquid crystal (LC) readouts, a square wave is applied
to the Ph input of the circuit and the electrically common backplane of
the display. The outputs of the circuit are connected directly to the
segments of the LC readout. For other types of readouts, such as
lightemitting diode (LED), incandescent, gas discharge, and
fluorescent readouts, connection diagrams are given on this data sheet.
Applications include instrument (e.g., counter, DVM etc.) display
Latch Storage of Code

Blanking Input
Readout Blanking on All Illegal Input Combinations
Direct LED (Common Anode or Cathode) Driving Capability
Capable of Driving 2 Lowpower TTL Loads, 1 Lowpower Schottky
TTL Load or 2 HTL Loads Over the Rated Temperature Range
PinforPin Replacement for CD4056A (with Pin 7 Tied to VSS).

Symbol
Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MC14543BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14543B
AWLYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966
MC14543B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14543BCP
PDIP16
2000/Box
MC14543BD
SOIC16
48/Rail
MC14543BDR2
SOIC16
2500/Tape & Reel
VDD
Vin
Iin
DC Input Current per Pin
10
mA
MC14543BF
SOEIAJ16
See Note 1.
PD
Power Dissipation,
500
mW
MC14543BFEL
SOEIAJ16
See Note 1.
TA
55 to +125
Tstg
65 to +150
IOHmax
IOLmax

Drive Current (Source or Sink)
10
(per Output)
mA
POHmax
POLmax

Power (Source or Sink) (4.)
70
(per Output)
mW
may occur.
4. POHmax = IOH (VOH VDD) and POLmax = IOL (VOL VSS)
March, 2000 Rev. 3
354

range VSS
(Vin or Vout)
VDD.

MC14543B/D
MC14543B
PIN ASSIGNMENT
LD
16
VDD
15
14
13
12
PH
11
BI
10
VSS
TRUTH TABLE
Inputs
LD
Outputs
BI Ph*
B A a b c d e
Display
X X 0
Blank
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
1
0
1
0
0
0
0
0
1
1
0
1
2
3
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
1
1
1
0
1
1
0
0
0
1
0
1
1
1
0
1
1
1
0
4
5
6
7
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
8
9
Blank
Blank
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Blank
Blank
Blank
Blank
X X
**
Inverse of Output
Combinations
Above
**
Display
as above
X = Dont care
= Above Combinations
* = For liquid crystal readouts, apply a square wave to Ph
For common cathode LED readouts, select Ph = 0
For common anode LED readouts, select Ph = 1
** = Depends upon the BCD code previously applied when LD = 1
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355
MC14543B
55_C
VDD
25_C
125_C
Symbol
Vdc
Min
Max
Min
Typ (5.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
10.1
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
10.1
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
Iout = 0 A
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
Characteristic
Output Voltage
Vin = VDD or 0
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 0.5 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 9.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
mAdc


Noise Margin for both 1 and 0 level = 1.0 V min @ VDD = 5.0 V
= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
where: IT is in A (per package), CL in pF, VDD in V, and f in kHz is input frequency.
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356
Adc
MC14543B

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 12.5 ns
tTHL
TurnOff Delay Time

tPLH = (0.66 ns/pF) CL + 217 ns
tPLH
TurnOn Delay Time

tPHL = (0.66 ns/pF) CL + 172 ns
tPHL
VDD
Min
Typ
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
100
50
40
200
100
80
5.0
10
15
605
250
185
1210
500
370
5.0
10
15
505
205
155
1650
660
495
Unit
ns
ns
ns
ns
Setup Time
tsu
5.0
10
15
350
450
500
ns
Hold Time
th
5.0
10
15
40
30
20
ns
tWH
5.0
10
15
250
100
80
ns
Latch Disable Pulse Width (Strobing Data)
125
50
40
LOGIC DIAGRAM
BI 7
VDD = PIN 16
VSS = PIN 8
9 a
A 5
10 b
11 c
B 3
12 d
13 e
C 2
15 f
14 g
D 4
LD 1
PHASE 6
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357
MC14543B
24
VDD = 15 Vdc
VDD = 5.0 Vdc
POHmax = 70 mWdc
IOL , SINK CURRENT (mAdc)
IOH, SOURCE CURRENT (mAdc)
6.0
VDD = 10 Vdc
12
18
18
VDD = 10 Vdc
12
6.0
VDD = 15 Vdc
24
16
POLmax = 70 mWdc
VDD = 5.0 Vdc

VSS = 0 Vdc
VSS = 0 Vdc
12
8.0
4.0
(VOH VDD), SOURCE DEVICE VOLTAGE (Vdc)
4.0
8.0
12
(VOL VSS), SINK DEVICE VOLTAGE (Vdc)

Characteristics
16

Characteristics
(a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high.

20 ns
20 ns
90%
10%
VDD
50%
tPLH
tPHL
90%
50%
VOH
10%
tTLH
tTHL
VSS
VOL
(b) Inputs D, Ph, and BI low, and Inputs A and B high.

20 ns
90%
10%
LD
VDD
50%
VSS
tsu
Inputs BI and Ph low, and Inputs D and LD high.

th
50%
50%
VSS

20 ns
A, B, AND C
10%
ANY OUTPUT
20 ns
90%
50%
1
2f
50% DUTY CYCLE
VDD
VOH
g
VDD
VOL
VSS
(c) Data DCBA strobed into latches
VDD
VOH
LD
VOL
50%
tWH
Figure 3. Dynamic Power Dissipation

Signal Waveforms
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358
VSS
MC14543B
LIQUID CRYSTAL (LC) READOUT
MC14543B
OUTPUT
Ph
APPROPRIATE
VOLTAGE
ONE OF SEVEN SEGMENTS

COMMON
BACKPLANE
MC14543B
OUTPUT
Ph
SQUARE WAVE
(VSS TO VDD)
VSS
COMMON
CATHODE LED
COMMON
ANODE LED
MC14543B
OUTPUT
Ph
APPROPRIATE
VOLTAGE
VDD
MC14543B
OUTPUT
Ph
MC14543B
OUTPUT
Ph
VSS
VDD
NOTE: Bipolar transistors may be added for gain (for VDD
v 10 V or Iout 10 mA).
VSS
CONNECTIONS TO SEGMENTS
a
f
c
d
VDD = PIN 16
VSS = PIN 8
DISPLAY
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359
MC14549B, MC14559B
Successive Approximation
Registers
The MC14549B and MC14559B successive approximation
registers are 8bit registers providing all the digital control and storage
necessary for successive approximation analogtodigital conversion
systems. These parts differ in only one control input. The Master Reset
(MR) on the MC14549B is required in the cascaded mode when more
than 8 bits are desired. The Feed Forward (FF) of the MC14559B is
used for register shortening where EndofConversion (EOC) is
required after less than eight cycles.
Applications for the MC14549B and MC14559B include
analogtodigital conversion, with serial and parallel outputs.
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
Totally Synchronous Operation

Serial Output
Retriggerable
Compatible with a Variety of Digital and Analog Systems such as the
MC1408 8Bit D/A Converter
All Control Inputs PositiveEdge Triggered
Capable of Driving 2 LowPower TTL Loads, 1 LowPower Schottky
TTL Load or 2 HTL Loads Over the Rated Temperature Range
Parameter
16
145XXB
SOIC16
DW SUFFIX
CASE 751G
AWLYYWW
1
XX
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Symbol
MC145XXBCP
AWLYYWW
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5
VDD
Vin
Iin
DC Input Current, per Pin
10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
Package
Shipping
MC14549BCP
PDIP16
25/Rail
MC14549BDWR2
SOIC16
1000/Tape & Reel
MC14559BCP
PDIP16
25/Rail
MC14559BDWR2
SOIC16
1000/Tape & Reel
may occur.
Device
to the range VSS
(Vin or Vout)
VDD.
either VSS or VDD).
March, 2000 Rev. 3
360

MC14549B/D
MC14549B, MC14559B
PIN ASSIGNMENT
Q4
16
VDD
Q5
15
Q3
Q6
14
Q2
Q7
13
Q1
Sout
12
Q0
11
EOC
10
VSS
SC
*For MC14549B Pin 10 is MR input.

For MC14559B Pin 10 is FF input.
MC14549B
SC SC(t1) MR MR(t1) Clock
X
X
1
X
X
0
X
1
0
X
X
0
TRUTH TABLES
MC14559B
Action
SC
None
Reset
Start
Conversion
Start
Conversion
Continue
Conversion
Continue
Previous
Operation
X
1
X
0
X
0
X = Dont Care t1 = State at Previous Clock
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361
SC(t1) EOC Clock
Action
None
Start
Conversion
Continue
Conversion
Continue
Conversion
Retain
Conversion
Result
Start
Conversion
MC14549B, MC14559B
55_C
VDD
25_C
125_C
Symbol
Vdc
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage (3.)

0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
5.0
10
15
1.28
3.2
8.4
1.02
2.6
6.8
1.76
4.5
17.6
0.72
1.8
4.8
mAdc
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Characteristic
Output Voltage
Vin = VDD or 0
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Q Outputs
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Pin 5, 11 only
IOL
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
(Clock = 0 V,
Other Inputs = VDD
or 0 V, Iout = 0 A)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15

Per Package)
buffers switching)


Noise Margin for both 1 and 0 level = 1.0 V min @ VDD = 5.0 V
= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
IT(CL) = IT(50 pF) + 3.5 x 103 (CL = 50) VDDf
where: IT is in A (per package), CL in pF, VDD in V, and f in kHz is input frequency.
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362
Adc
MC14549B, MC14559B

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL

Clock to Q
Clock to Sout
Clock to EOC
tPLH,
tPHL
VDD
Min
Typ
Max
5.0
10
15
180
90
65
360
180
130
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
ns
5.0
10
15
500
210
155
1000
420
310
5.0
10
15
750
310
220
1500
620
440
5.0
10
15
300
130
100
600
260
200
tsu
5.0
10
15
250
100
80
125
50
40
ns
tWH(cl)
5.0
10
15
700
270
200
350
135
100
ns
Pulse Width D, SC, FF or MR
tWH
5.0
10
15
500
200
160
250
100
80
ns
tTLH,
tTHL
5.0
10
15
15
1.0
0.5
5.0
10
15
1.5
3.0
4.0
0.8
1.5
2.0
MHz
SC, D, FF or MR Setup Time
Clock Pulse Width
fcl
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363
MC14549B, MC14559B
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VDD
Q7
Q6
Q5
PROGRAMMABLE
PULSE
GENERATOR
CL
CL
Q4
Q3
SC
FF(MR)
CL
CL
Q2
Q1
CL
CL
Q0
EOC
CL
CL
Sout
CL
CL
1
fcl
VSS
C
tWH(cl)
50%
SC
D
tsu
50%
tsu
tWH(D)
tsu
50%
tPLH
Q7
tPHL
50%
90%
tTLH
Sout
10%
tTHL
50%
tPLH
90%
10%
tTLH
NOTE: Pin 10 = VSS
TIMING DIAGRAM
CLOCK
SC
D
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
EOC
Sout
INH Q7 Q6 INH Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q8* INH

Dont care condition
INH Indicates Serial Out is inhibited low.

* Q8 is ninthbit of serial information available from 8bit register.
NOTE: Pin 10 = VSS
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364
MC14549B, MC14559B
conversion, tie Q1 to FF; the part will respond as shown in
the timing diagram less two bit times. Not that Q1 and Q0
will still operate and must be disregarded.
For 8bit operation, FF is tied to VSS.
For applications with more than 8 but less than 16 bits, use
the basic connections shown in Figure 1. The FF input of the
MC14559B is used to shorten the setup. Tying FF directly
to the least significant bit used in the MC14559B allows
EOC to provide the cascading signal, and results in smooth
transition of serial information from the MC14559B to the
MC14549B. The Serial Out (Sout) inhibit structure of the
MC14559B remains inactive one cycle after EOC goes high,
while Sout of the MC14549B remains inhibited until the
second clock cycle of its operation.
Qn = Data Outputs After a conversion is initiated the
Qs on succeeding cycles go high and are then conditionally
reset dependent upon the state of the D input. Once
conditionally reset they remain in the proper state until the
circuit is either reset or reinitiated.
EOC = End of Convert This output goes high on the
negativegoing transition of the clock following FF = 1 (for
the MC14559B) or the conditional reset of Q0. This allows
settling of the digital circuitry prior to the End of Conversion
indication. Therefore either level or edge triggering can
indicate complete conversion.
Sout = Serial Out Transmits conversion in serial
fashion. Serial data occurs during the clock period when the
corresponding parallel data bit is conditionally reset. Serial
Out is inhibited on the initial period of a cycle, when the
circuit is reset, and on the second cycle after EOC goes high.
This provides efficient operation when cascaded.
Both the MC14549B and MC14559B can be operated in

either the free run or strobed operation mode for
conversion schemes with any number of bits. Reliable
cascading and/or recirculating operation can be achieved if
the End of Convert (EOC) output is used as the controlling
function, since with EOC = 0 (and with SC = 1 for
MC14549B but either 1 or 0 for MC14559B) no stable state
exists under continual clocked operation. The MC14559B
will automatically recirculate after EOC = 1 during
externally strobed operation, provided SC = 1.
All data and control inputs for these devices are triggered
into the circuit on the positive edge of the clock pulse.
Operation of the various terminals is as follows:
C = Clock A positivegoing transition of the Clock is
required for data on any input to be strobed into the circuit.
SC = Start Convert A conversion sequence is initiated
on the positivegoing transition of the SC input on
succeeding clock cycles.
D = Data in Data on this input (usually from a
comparator in A/D applications) is also entered into the
circuit on a positivegoing transition of the clock. This input
is Schmitt triggered and synchronized to allow fast response
and guaranteed quality of serial and parallel data.
MR = Master Reset (MC14549B Only) Resets all
output to 0 on positivegoing transitions of the clock. If
removed while SC = 0, the circuit will remain reset until SC
= 1. This allows easy cascading of circuits.
FF = Feed Forward (MC14559B Only) Provides
register shortening by removing unwanted bits from a
system.
For operation with less than 8 bits, tie the output following
the least significant bit of the circuit to EOC. E.g., for a 6bit
FROM A/D
COMPARATOR
D
C
SC
EXTERNAL
CLOCK
Sout
MC14559B
* FF
Q7 Q6 Q5 Q4 Q0 EOC
1/4 MC14001
D
C
SC
Sout
MC14549B
MR
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC
**
MSB
NC
TO D/A AND PARALLEL DATA
LSB
TO D/A AND
PARALLEL DATA
FREE RUN MODE
EXTERNAL STROBE
* FF allows EOC to activate as if in 4stage register.
** Cascading using EOC guaranteed; no stable unfunctional state.
Completion of conversion automatically reinitiates cycle in free run mode.
Figure 1. 12Bit Conversion Scheme
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365
SERIAL OUT
(CONTINUAL
UPDATE EVERY
13 CLOCK CYCLES)
MC14549B, MC14559B
Externally Controlled 6Bit ADC (Figure 2)
Continuously Cycling 12Bit ADC (Figure 4)
Several features are shown in this application:

Shortening of the register to six bits by feeding the
seventh output bit into the FF input.
Continuous conversion, if a continuous signal is applied
to SC.
Externally controlled updating (the start pulse must be
shorter than the conversion cycle).
The EOC output indicating that the parallel data are valid
and that the serial output is complete.
Because each successive approximation register (SAR)

has a capability of handling only an eightbit word, two
must be cascaded to make an ADC with more than eight bits.
When it is necessary to cascade two SARs, the second
SAR must have a stable resettable state to remain in while
awaiting a subsequent start signal. However, the first stage
must not have a stable resettable state while recycling,
because during switchon or due to outside influences, the
first stage has entered a reset state, the entire ADC will
remain in a stable nonfunctional condition.
This 12bit ADC is continuously recycling. The serial as
well as the parallel outputs are updated every thirteenth
clock pulse. The EOC pulse indicates the completion of the
12bit conversion cycle, the end of the serial output word,
and the validity of the parallel data output.
Continuously Cycling 8Bit ADC (Figure 3)
This ADC is running continuously because the EOC

signal is fed back to the SC input, immediately initiating a
new cycle on the next clock pulse.
C
SC
Sout
MC14559B
Q7 Q6
Q5
Q4
Q3
Q2
Q1
Q0
FF EOC
TO DAC
Figure 2. Externally Controlled 6Bit ADC
C
SC
Sout
MC14559B
Q7 Q6
Q5
Q4
Q3
Q2
Q1
Q0
FF EOC
TO DAC
Figure 3. Continuously Cycling 8Bit ADC
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366
MC14549B, MC14559B
Sout
C
SC
Sout
Sout
MC14549B
MR
SC
MC14559B
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC
TO DAC
TO DAC
EOC
Figure 4. Continuously Cycling 12Bit ADC
Externally Controlled 12Bit ADC (Figure 5)
Additional Motorola Parts for Successive

Approximation ADC
In this circuit the external pulse starts the first SAR and
simultaneously resets the cascaded second SAR. When Q4
of the first SAR goes high, the second SAR starts
conversion, and the first one stops conversion. EOC
indicates that the parallel data are valid and that the serial
output is complete. Updating the output data is started with
every external control pulse.
SC
Monolithic digitaltoanalog converters The

MC1408/1508 converter has eightbit resolution and is
available with 6, 7, and 8bit accuracy. The
amplifiercomparator block The MC1407/1507
contains a high speed operational amplifier and a high speed
comparator with adjustable window.
With these two linear parts it is possible to construct
SAADCs with an accuracy of up to eight bits, using as the
register one MC14549B or one MC14559B. An additional
CMOS block will be necessary to generate the clock
frequency.
Additional information on successive approximation
ADC is found in Motorola Application Note AN716.
Sout
SC
MC14559B
MC14549B
Sout
MR
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC
TO DAC
TO DAC
EOC
Figure 5. Externally Controlled 12Bit ADC
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367
Sout
MC14551B
Quad 2-Channel Analog
The MC14551B is a digitallycontrolled analog switch. This device
implements a 4PDT solid state switch with low ON impedance and
very low OFF Leakage current. Control of analog signals up to the
complete supply voltage range can be achieved.
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Triple Diode Protection on All Control Inputs

Analog Voltage Range (VDD VEE) = 3.0 to 18 V
MARKING
DIAGRAMS
16
Note: VEE must be VSS

Low Noise 12 nVCycle, f 1.0 kHz typical
For Low RON, Use The HC4051, HC4052, or HC4053 HighSpeed
CMOS Devices
Switch Function is Break Before Make
PDIP16
P SUFFIX
CASE 648
1
16
SOIC16
D SUFFIX
CASE 751B
MAXIMUM RATINGS (2.)
VDD
Vin, Vout
Parameter

(Referenced to VEE, VSS VEE)
Input Current (DC or Transient),

per Control Pin
Isw
Unit
V
0.5 to VDD + 0.5
16
SOEIAJ16
F SUFFIX
CASE 966
MC14551B
AWLYWW
1
Input or Output Voltage (DC or

Transient) (Referenced to VSS for
Control Input & VEE for Switch I/O)
Iin
Value
0.5 to + 18.0
14551B
AWLYWW
1
Symbol
MC14551BCP
AWLYYWW
(3.)
10
mA
25
mA
500
mW
PD
Power Dissipation, per Package
TA
55 to + 125
_C
Tstg
65 to + 150
_C
TL
Lead Temperature
(8Second Soldering)
260
_C
may occur.
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14551BCP
PDIP16
2000/Box
MC14551BD
SOIC16
48/Rail
MC14551BDR2
SOIC16
2500/Tape & Reel
SOEIAJ16
See Note 1.
MC14551BF

to the range VSS (Vin or Vout) VDD for control inputs and VEE (Vin or Vout)
VDD for Switch I/O.
either VSS, VEE or VDD). Unused outputs must be left open.
March, 2000 Rev. 3
368

MC14551B/D
MC14551B
PIN ASSIGNMENT
W1
16
VDD
X0
15
W0
X1
14
13
12
Z1
Y0
11
Z0
VEE
10
Y1
VSS
SWITCHES
IN/OUT
VDD = Pin 16
VSS = Pin 8
VEE = Pin 7
15
1
2
3
6
10
11
12
CONTROL
W
W0
W1
X0
X1
Y0
Y1
Z0
Z1
CONTROL
14
4
COMMONS
OUT/IN
13
Control
ON
W0 X0 Y0 Z0
W1 X1 Y1 Z1
NOTE: Control Input referenced to VSS, Analog Inputs and

Outputs reference to VEE. VEE must be
VSS.
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369
MC14551B
55_C
Characteristic
Symbol
VDD
Test Conditions
25_C
125_C
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit

Range
VDD
VDD 3.0 VSS

VEE
3.0
18
3.0
18
3.0
18

Package
IDD
5.0
10
15
Control Inputs: Vin =

VSS or VDD,
VI/O
Switch I/O: VEE
VDD, and Vswitch
500 mV (5.)
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
5.0
10
15
TA = 25_C only (The

channel component,
(Vin Vout)/Ron, is
not included.)

(Dynamic Plus
Quiescent, Per Package)
ID(AV)
v
v
Typical

CONTROL INPUT (Voltages Referenced to VSS)

VIL
5.0
10
15
Ron = per spec,

Ioff = per spec
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
VIH
5.0
10
15
Ron = per spec,

Ioff = per spec
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Iin
15
Vin = 0 or VDD
0.1
0.00001
0.1
1.0
Input Capacitance
Cin
5.0
7.5
pF
SWITCHES IN/OUT AND COMMONS OUT/IN W, X, Y, Z (Voltages Referenced to VEE)

Recommended Peakto
Peak Voltage Into or Out
of the Switch
VI/O
Channel On or Off
VDD
VDD
VDD
Vpp
Vswitch
Channel On
600
600
300
mV
VOO
Vin = 0 V, No Load
10
ON Resistance
Ron
5.0
10
15
Vswitch
500 mV (5.),
Vin = VIL or VIH
0 to VDD (Switch)
800
400
220
250
120
80
1050
500
280
1200
520
300
Ron
5.0
10
15
70
50
45
25
10
10
70
50
45
135
95
65
Ioff
15
Vin = VIL or VIH

Channel or Any One
Channel
100
0.05
100
1000
nA
CI/O
Switch Off
10
pF
CO/I
17
pF
(Channel Off)
CI/O
0.15
0.47
pF
Any Two Channels
in the Same Package
OffChannel Leakage
Current (Figure 8)
Pins Not Adjacent

Pins Adjacent
5. For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
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370
MC14551B
ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C, VEE

Characteristic
Symbol

Switch Input to Switch Output (RL = 10 k)
tPLH, tPHL
Control Input to Output (RL = 10 k)

VEE = VSS (Figure 4)
tPLH, tPHL
VSS)
VDD VEE
Vdc
Min
Typ (6.)
Max
Unit
ns
5.0
10
15
35
15
12
90
40
30
5.0
10
15
350
140
100
875
350
250
10
0.07
BW
10
17
MHz
Off Channel Feedthrough Attenuation, Figure 5

RL = 1 k, Vin = 1/2 (VDD VEE) pp,
fin = 55 MHz
10
50
dB

fin = 3 MHz
10
50
dB
Crosstalk, Control Input to Common O/I, Figure 7

R1 = 1 k, RL = 10 k,
Control tr = tf = 20 ns
10
75
mV

RL = 10 k, f = 1 kHz, Vin = 5 Vpp
Bandwidth (Figure 5)
20 Log (Vout / Vin) = 3 dB, CL = 50 pF
ns
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371
MC14551B
VDD
VDD
VDD
IN/OUT
OUT/IN
VEE
VDD
LEVEL
CONVERTED
CONTROL
IN/OUT
OUT/IN
CONTROL
VEE
Figure 1. Switch Circuit Schematic

16
CONTROL 9
VDD
LEVEL
CONVERTER
VSS
CONTROL
VEE
W0 15
14 W
W1 1
X0 2
4 X
X1 3
Y0 6
5 Y
Y1 10
Z0 11
13 Z
Z1 12
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372
MC14551B
TEST CIRCUITS
ON SWITCH
CONTROL
SECTION
OF IC
PULSE
GENERATOR
CONTROL
Vout
LOAD
V
RL
CL
SOURCE
VDD VEE
VEE VDD
Figure 4. Propagation Delay Times,

Control to Output
Control input used to turn ON or OFF

RL
ON
CONTROL
Vout
RL
CONTROL
OFF
CL = 50 pF
Vout
RL
CL = 50 pF
Vin
VDD VEE
2
Vin
VDD VEE
2


(Adjacent Channels Used for Setup)

VDD
CONTROL
CONTROL
SECTION
OF IC
Vout
RL
VEE
OTHER
CHANNEL(S)
CL = 50 pF
VEE
VDD
R1
VEE
VDD
Figure 7. Crosstalk, Control Input

to Common O/I
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 k
RANGE
VDD
VEE = VSS
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373
X/Y
PLOTTER
MC14551B
350
300
300
250
200
150
TA = 125C
100
25C
55C
50
0
10 8.0 6.0 4.0 2.0
RON, ON RESISTANCE (OHMS)
350
2.0
4.0
6.0
8.0
250
200
150
TA = 125C
100
25C
55C
50
0
10 8.0 6.0 4.0 2.0
10
2.0
4.0
6.0
8.0
Figure 10. VDD @ 7.5 V, VEE @ 7.5 V
700
350
600
300
500
400
300
TA = 125C
200
25C
100
55C
0
10 8.0 6.0 4.0 2.0
2.0
4.0
6.0
8.0
TA = 25C
VDD = 2.5 V
250
200
150
5.0 V
100
7.5 V
50
0
10 8.0 6.0 4.0 2.0
10
2.0
4.0
6.0
8.0
Figure 13. Comparison at 25_C, VDD @ VEE
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374
10
10
MC14551B
Figure A illustrates use of the onchip level converter
detailed in Figure 2. The 0to5 volt Digital Control signal
is used to directly control a 9 Vpp analog signal.
and VEE. The VDD voltage determines the maximum
recommended peak above VSS. The VEE voltage
determines the maximum swing below VSS. For the
example, VDD VSS = 5 volt maximum swing above VSS;
VSS VEE = 5 volt maximum swing below VSS. The
example shows a 4.5 volt signal which allows a 1/2 volt
margin at each peak. If voltage transients above VDD and/or

below VEE are anticipated on the analog channels, external
diodes (Dx) are recommended as shown in Figure B. These
diodes should be small signal types able to absorb the
maximum anticipated current surges during clipping.
VDD and VEE is 18.0 volts. Most parameters are specified
up to 15 volts which is the recommended maximum
difference between VDD and V EE.
Balanced supplies are not required. However, V SS must
be greater than or equal to VEE. For example, VDD =
+ 10 volts, VSS = + 5 volts, and VEE = 3 volts is acceptable.
See the table below.
+5 V
5 V
VDD
9 Vpp
+5 V
ANALOG SIGNAL
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
VSS
SWITCH
I/O
VEE
+ 4.5 V
COMMON
O/I
9 Vpp
GND
ANALOG SIGNAL
MC14551B
0TO5 V DIGITAL
4.5 V
CONTROL
CONTROL SIGNAL

VDD
VDD
Dx
Dx
SWITCH
I/O
COMMON
O/I
Dx
Dx
VEE
VEE
Figure B. External Schottky or Germanium Clipping Diodes
POSSIBLE SUPPLY CONNECTIONS

VDD
In Volts
VSS
In Volts
VEE
In Volts
Control Inputs
Logic High/Logic Low
In Volts
Maximum Analog Signal Range

In Volts
+8
+ 8/0
+ 8 to 8 = 16 Vpp
+5
12
+ 5/0
+ 5 to 12 = 17 Vpp
+5
+ 5/0
+ 5 to 0 = 5 Vpp
+5
+ 5/0
+ 5 to 5 = 10 Vpp
+ 10/ + 5
+ 10 to 5 = 15 Vpp
+ 10
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375
MC14553B
3-Digit BCD Counter
The MC14553B 3digit BCD counter consists of 3 negative edge
triggered BCD counters that are cascaded synchronously. A quad latch
at the output of each counter permits storage of any given count. The
information is then time division multiplexed, providing one BCD
number or digit at a time. Digit select outputs provide display control.
All outputs are TTL compatible.
An onchip oscillator provides the lowfrequency scanning clock
which drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays,
digital panel meters, and as a building block for general logic
applications.
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
TTL Compatible Outputs

OnChip Oscillator
Cascadable
Clock Disable Input
Pulse Shaping Permits Very Slow Rise Times on Input Clock
Output Latches
Master Reset
MC14553BCP
AWLYYWW
1
16
14553B
SOIC16
DW SUFFIX
CASE 751G
AWLYYWW
1

Symbol
VDD
Vin, Vout
Parameter
(DC or Transient)
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5
Iin
Input Current
10
mA
Iout
Output Current
+20
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14553BCP
PDIP16
25/Rail
MC14553BDW
SOIC16
47/Rail
may occur.
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
376

MC14553B/D
MC14553B
BLOCK DIAGRAM
4
CIA
3
CIB Q0
Q1
Q2
Q3
O.F.
DS1
DS2
DS3
15
CLOCK
12
10
LE
11
DIS
MR
13
14
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Inputs
Master
Reset
0
0
0
0
0
0
0
0
1
Clock
X
1
1
0
X
X
X
Disable
LE
Outputs
0
0
1
0
0
X
0
0
X
No Change
Advance
No Change
Advance
No Change
No Change
Latched
Latched
Q0 = Q1 = Q2 = Q3 = 0
X
X
X
X
1
0
X = Dont Care
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377
MC14553B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Vdc
Vdc
IOH

(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Source
Pin 3
5.0
10
15
0.25
0.62
1.8
0.2
0.5
1.5
0.36
0.9
3.5
0.14
0.35
1.1
(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Source
Other
Outputs
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
5.0
10
15
0.5
1.1
1.8
0.4
0.9
1.5
0.88
2.25
8.8
0.28
0.65
1.20
mAdc
5.0
10
15
3.0
6.0
18
2.5
5.0
15
4.0
8.0
20
1.6
3.5
10
mAdc
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Pin 3
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink Other
Outputs
IOL
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
MR = VDD
IDD
5.0
10
15
5.0
10
20
0.010
0.020
0.030
5.0
10
20
150
300
600
Adc
IT
5.0
10
15

Per Package)
buffers switching)

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378
Adc
MC14553B
VDD
Min
Typ (7.)
Max
5.0
10
15
100
50
40
200
100
80
tPLH,
tPHL
5.0
10
15
900
500
200
1800
1000
400
ns
2a
tPHL
5.0
10
15
600
400
200
1200
800
400
ns
Reset to BCD Out
2b
tPHL
5.0
10
15
900
500
300
1800
1000
600
ns
Clock to Latch Enable Setup Time

Master Reset to Latch Enable Setup Time
2b
tsu
5.0
10
15
600
400
200
300
200
100
ns
Removal Time
Latch Enable to Clock
2b
trem
5.0
10
15
80
10
0
200
70
50
ns
Clock Pulse Width
2a
tWH(cl)
5.0
10
15
550
200
150
275
100
75
ns
Reset Pulse Width
2b
tWH(R)
5.0
10
15
1200
600
450
600
300
225
ns
Reset Removal Time
trem
5.0
10
15
80
0
20
180
50
30
ns
Input Clock Frequency
2a
fcl
5.0
10
15
1.5
5.0
7.0
0.9
2.5
3.5
MHz
Input Clock Rise Time
2b
tTLH
5.0
10
15
Disable, MR, Latch Enable

Rise and Fall Times
tTLH,
tTHL
5.0
10
15
15
5.0
4.0
Scan Oscillator Frequency

(C1 measured in F)
fosc
5.0
10
15
1.5/C1
4.2/C1
7.0/C1
Hz
Characteristic
Figure
Symbol

2a
tTLH,
tTHL
Clock to BCD Out
2a
Clock to Overflow
ns
No
Limit
ns
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379
Unit
899
900
901
990
991
992
993
994
995
996
997
998
999
1000
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
MC14553B
UNITS CLOCK
UNITS Q0
UNITS Q1
UNITS Q2
UNITS Q3
TENS CLOCK
TENS Q0
TENS Q3
HUNDREDS
CLOCK
UP AT 980
UP AT 80
HUNDREDS Q0
HUNDREDS Q3
DISABLE
UP AT 800
(DISABLES CLOCK WHEN HIGH)
OVERFLOW
MASTER
RESET
SCAN
OSCILLATOR
DIGIT SELECT 1
UNITS
TENS
DIGIT SELECT 2
DIGIT SELECT 3
HUNDREDS
Figure 1. 3Digit Counter Timing Diagram (Reference Figure 3)

VDD
Q3
Q2
Q1
Q0
O.F.
DS1
DS2
DS3
C
LE
DIS
MR
8
20 ns
CL
CL
CL
CL
BCD OUT
CL
20 ns
90%
CLOCK
10%
tPLH
1000
16
999
(a)
PULSE
GENERATOR
tWL(cl)
50%
10%
tTLH
90%
1/fcl
tPHL
50%
tTHL
tPHL
50%
OVERFLOW
VSS
tTLH
(b)
GENERATOR
1
CLOCK
VDD
C
GENERATOR
2
LE
GENERATOR
3
MR
DIS
Q3
Q2
Q1
Q0
O.F.
DS1
DS2
DS3
50%
90%
10%
tsu
trem
CL
LATCH
ENABLE
CL
CL
50%
tPHL, tPLH
CL
CL
BCD OUT
tsu
50%
tPHL
VSS
50%
MASTER RESET
Figure 2. Switching Time Test Circuits and Waveforms
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380
tWH(R)
MC14553B
The Master Reset input, when taken high, initializes the
three BCD counters and the multiplexer scanning circuit.
While Master Reset is high the digit scanner is set to digit
one; but all three digit select outputs are disabled to prolong
display life, and the scan oscillator is inhibited. The Disable
input, when high, prevents the input clock from reaching the
counters, while still retaining the last count. A pulse shaping
circuit at the clock input permits the counters to continue
operating on input pulses with very slow rise times.
Information present in the counters when the latch input
goes high, will be stored in the latches and will be retained
while the latch input is high, independent of other inputs.
Information can be recovered from the latches after the
counters have been reset if Latch Enable remains high
during the entire reset cycle.
The MC14553B threedigit counter, shown in Figure 3,

consists of three negative edgetriggered BCD counters
which are cascaded in a synchronous fashion. A quad latch
at the output of each of the three BCD counters permits
storage of any given count. The three sets of BCD outputs
(active high), after going through the latches, are time
division multiplexed, providing one BCD number or digit at
a time. Digit select outputs (active low) are provided for
display control. All outputs are TTL compatible.
An onchip oscillator provides the low frequency
scanning clock which drives the multiplexer output selector.
The frequency of the oscillator can be controlled externally
by a capacitor between pins 3 and 4, or it can be overridden
and driven with an external clock at pin 4. Multiple devices
can be cascaded using the overflow output, which provides
one pulse for every 1000 counts.
C1A
4
SCAN
R
OSCILLATOR 3
C1B
LATCH ENABLE
10
CLOCK
12
PULSE
SHAPER
C1
PULSE
GENERATOR
R SCANNER
Q0
Q1
Q2
R 10
Q3
UNITS
C
QUAD
LATCH
9
11
DISABLE
(ACTIVE
HIGH)
MULTIPLEXER
7
Q0
C
Q1
Q2
R 10
Q3
TENS
Q1
QUAD
LATCH
BCD
OUTPUTS
(ACTIVE
HIGH)
6
Q0
Q1
Q2
R
10 Q3
HUNDREDS
C
13
MR
(ACTIVE HIGH)
Q0
QUAD
LATCH
14
OVERFLOW
2
1
15
DS1 DS2 DS3
(LSD) DIGIT SELECT (MSD)
(ACTIVE LOW)
Figure 3. Expanded Block Diagram
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381
Q2
Q3
CLOCK
INPUT
VDD
STROBE
RESET
11
12
MC14553B
13
MR
C1B
C1A
Figure 4. SixDigit Display
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382
LSD
5
9
a
A
3
B
b 10
2
11
C
c
12
4
D MC14543B d
6
13
Ph
e
1
15
f
LD
7
14
BI
g
O.F.
Q3 Q2 Q1 Q0 DS3 DS2 DS1
5
6
7
9 15
1 2
DIS
CLK
10
LE
14
4
0.001
F
MC14553B
MR
13
C1 B
C1 A
DISPLAYS ARE LOW CURRENT LEDs

(I peak < 10 mA PER SEGMENT)
VDD
14
4
3
9
10
2
MSD
b
11
c
12
4
D MC14543B d
6
13
Ph
e
1
15
LD
f
7
g 14
BI
O.F.
Q3 Q2 Q1 Q0 DS3 DS2 DS1
5
6
7
9 15
1
2
DIS
CLK
VDD
11
12
LE
10
MC14553B
MC14555B, MC14556B
Dual Binary to 1-of-4
Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with
complementary MOS (CMOS) enhancement mode devices. Each
Decoder/Demultiplexer has two select inputs (A and B), an active low
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,
Q3). The MC14555B has the selected output go to the high state,
and the MC14556B has the selected output go to the low state.
Expanded decoding such as binarytohexadecimal (1of16), etc.,
can be achieved by using other MC14555B or MC14556B devices.
Applications include code conversion, address decoding, memory
selection control, and demultiplexing (using the Enable input as a data
input) in digital data transmission systems.
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MC1455XBCP
AWLYYWW
1

Active High or Active Low Outputs
Expandable
16
SOIC16
D SUFFIX
CASE 751B
1455XB
AWLYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966
MC1455XB
AWLYWW
1

Symbol
VDD
Parameter
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
TL
Lead Temperature
(8Second Soldering)
Vin, Vout
Iin, Iout
Value

(DC or Transient)
X
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Package
Shipping
MC14555BCP
PDIP16
2000/Box
MC14555BD
SOIC16
48/Rail
65 to +150
MC14555BDR2
SOIC16
2500/Tape & Reel
260
MC14555BF
SOEIAJ16
See Note 1.
may occur.
MC14555BFEL
SOEIAJ16
See Note 1.
MC14556BCP
PDIP16
2000/Box
MC14556BD
SOIC16
48/Rail
to the range VSS
(Vin or Vout)
VDD.
MC14556BDR2
SOIC16
2500/Tape & Reel
MC14556BF
SOEIAJ16
See Note 1.
MC14556BFEL
SOEIAJ16
See Note 1.
March, 2000 Rev. 3
Device
383


MC14555B/D
MC14555B, MC14556B
PIN ASSIGNMENTS
MC14555B
MC14556B
EA
16
VDD
EA
16
VDD
AA
15
EB
AA
15
EB
BA
14
AB
BA
14
AB
Q0A
13
BB
Q0A
13
BB
Q1A
12
Q0B
Q1A
12
Q0B
Q2A
11
Q1B
Q2A
11
Q1B
Q3A
10
Q2B
Q3A
10
Q2B
VSS
Q3B
VSS
Q3B
TRUTH TABLE
Inputs
Enable
Outputs
Select
MC14555B
MC14556B
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
X = Dont Care
BLOCK DIAGRAM
MC14555B
2
14
13
15
MC14556B
Q0
Q1
Q2
Q3
4
5
6
7
Q0
Q1
Q2
Q3
12
11
10
9
14
13
15
VDD = PIN 16
VSS = PIN 8
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384
Q0
Q1
Q2
Q3
4
5
6
7
Q0
Q1
Q2
Q3
12
11
10
9
MC14555B, MC14556B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

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385
Adc
MC14555B, MC14556B

Characteristic
Symbol

tTLH,
tTHL
Propagation Delay Time A, B to Output

tPLH,
tPHL
Propagation Delay Time E to Output

tPLH,
tPHL
VDD
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
220
95
70
440
190
140
5.0
10
15
200
85
65
400
170
130
Unit
ns
ns
ns
INPUT E LOW
20 ns
INPUT A HIGH, INPUT E LOW

20 ns
20 ns
A INPUTS
(50% DUTY CYCLE)
1
2f
90%
50%
10%
VDD
20 ns
VSS
INPUT B
VDD
tPHL
B INPUTS
(50% DUTY CYCLE)
VSS
OUTPUT Q1
VOL
VOH
90%
50%
10%
OUTPUT Q3
MC14556B
tTHL
tPLH
OUTPUT Q3
MC14555B
VOH
VOL
Q0
A
*
Q1
B
*
Q2
Q3
386
V
tTLH OL
tTHL
LOGIC DIAGRAM
(1/2 of Dual)
http://onsemi.com
VOH
tPHL
90%
50%
10%
tTLH
*Eliminated for MC14555B
VSS
tPLH
All 8 outputs connect to respective CL loads.

VDD
90%
50%
10%
MC14557B
1-to-64 Bit Variable Length
Shift Register
The MC14557B is a static clocked serial shift register whose length
may be programmed to be any number of bits between 1 and 64. The
number of bits selected is equal to the sum of the subscripts of the
enabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plus
one. Serial data may be selected from the A or B data inputs with the
A/B select input. This feature is useful for recirculation purposes. A
Clock Enable (CE) input is provided to allow gating of the clock or
negative edge clocking capability.
The device can be effectively used for variable digital delay lines or
simply to implement odd length shift registers.
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
164 Bit Programmable Length

Q and Q Serial Buffered Outputs
Asynchronous Master Reset
All Inputs Buffered
No Limit On Clock Rise and Fall Times
Capable of Driving Two Lowpower TTL Loads or one Lowpower
MC14557BCP
AWLYYWW
1
16
14557B
SOIC16
DW SUFFIX
CASE 751G
AWLYYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966

Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Symbol
VDD
Vin, Vout
Iin, Iout

(DC or Transient)
may occur.
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
387
MC14557B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14557BCP
PDIP16
2000/Box
MC14557BDW
SOIC16
47/Rail
MC14557BDWR2
SOIC16
1000/Tape & Reel
MC14557BF
SOEIAJ16
See Note 1.
MC14557BFEL
SOEIAJ16
See Note 1.


MC14557B/D
MC14557B
PIN ASSIGNMENT
L2
16
VDD
L1
15
L4
RESET
14
L8
CLOCK
13
L16
CE
12
L32
11
10
VSS
A/B SEL
BLOCK DIAGRAM
3
4
5
6
7
9
2
1
15
14
13
12
RESET
CLOCK
CE
B
A
A/B SELECT
L1
L2
L4
L8
L16
L32
10
11
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Inputs
Rst
A/B
0
0
0
0
1
0
1
0
1
X
Output
Clock
1
1
X
CE
0
0
B
A
B
A
0
Q is the output of the first selected shift

register stage.
X = Dont Care
LENGTH SELECT TRUTH TABLE

L32
L16
L8
L4
L2
L1
Register Length
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1 Bit
2 Bits
Bit
3 Bits
4 Bits
5 Bits
6 Bits

1
1
0
0
0
0
0
0
0
0
0
1
33 Bits
Bit
34 Bits

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
0
1
61 Bits
62 Bits
63 Bits
64 Bit
Bits
NOTE: Length equals the sum of the binary length control

subscripts plus one.
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388
MC14557B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.010
0.020
0.030
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
mAdc
IOH
Source
Sink

Per Package)
buffers switching)

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389
Adc
MC14557B

Characteristic
Symbol
Rise and Fall Time, Q or Q Output

tTLH,
tTHL
Propagation Delay, Clock or CE to Q or Q

tPLH,
tPHL
Propagation Delay, Reset to Q or Q

tPLH,
tPHL
VDD
Min
Typ (8.)
Max
5
10
15
100
50
40
200
100
80
5
10
15
300
130
90
600
260
180
5
10
15
300
130
95
600
260
190
Unit
ns
ns
ns
Pulse Width, Clock
tWH(cl)
5
10
15
200
100
75
95
45
35
ns
Pulse Width, Reset
tWH(rst)
5
10
15
300
140
100
150
70
50
ns
Clock Frequency (50% Duty Cycle)
fcl
5
10
15
3.0
7.5
13.0
1.7
5.0
6.7
MHz
Setup Time, A or B to Clock or CE

Worst case condition: L1 = L2 = L4 = L8 =
L16 = L32 = VSS (Register Length = 1)
tsu
5
10
15
700
290
145
350
130
85
5
10
15
400
165
60
45
5
0
5
10
15
200
100
10
150
60
50
5
10
15
400
185
85
50
25
22
Best case condition: L32 = VDD, L1 through L16 =

Dont Care (Any register length from 33 to 64)
Hold Time, Clock or CE to A or B
Best case condition: L1 = L2 = L4 = L8 = L16 =
L32 = VSS (Register Length = 1)
th
Worst case condition: L32 = VDD, L1 through L16 =

Dont Care (Any register length from 33 to 64)
Rise and Fall Time, Clock
Rise and Fall Time, Reset or CE
Removal Time, Reset to Clock or CE
ns
ns
tr,
tf
5
10
15
tr,
tf
5
10
15
15
5
4
trem
5
10
15
160
80
70
80
40
35
ns
No Limit
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390
MC14557B
TIMING DIAGRAM
VDD
50%
CLOCK
tWH(cl)
VSS
1/fcl
VDD
50%
A INPUT
VSS
trem
tsu
VDD
th
50%
VSS
RESET
tTLH
1bit length:
CE = 0
Q
A/B = 1
L1 = L2 = L4 = L8 = L16 = L32 = 0
tTHL
PWR
VOH
90%
50%
10%
tPLH
tPHL
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391
tPHL
VOL
A/B 9
SELECT
RESET
CLOCK
CE
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392
2
L1
1
L2
C
2 BIT
L16
1 BIT
16 BIT
L32
13
R
32 BIT
12
L8
14
1 BIT
8 BIT
4 BIT
VDD = PIN 16
VSS = PIN 8
11
10
L4
15
MC14557B
LOGIC DIAGRAM
MC14562B
128-Bit Static Shift
Register
The MC14562B is a 128bit static shift register constructed with
single monolithic structure. Data is clocked in and out of the shift
register on the positive edge of the clock input. Data outputs are
available every 16 bits, from 16 through bit 128. This complementary
MOS shift register is primarily used where low power dissipation
and/or high noise immunity is desired.
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MARKING
DIAGRAMS

Cascadable to Provide Longer Shift Register Lengths
14
PDIP14
P SUFFIX
CASE 646
MC14562BCP
AWLYYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Symbol
VDD
Vin, Vout
Iin, Iout

(DC or Transient)
Device
MC14562BCP
Package
Shipping
PDIP14
25/Rail
may occur.
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
393

MC14562B/D
MC14562B
PIN ASSIGNMENT
Q64
14
VDD
Q96
13
Q32
Q128
12
DATA
NC
11
NC
CLOCK
10
Q16
Q112
Q48
VSS
Q80
NC = NO CONNECTION
BLOCK DIAGRAM
12
Q16
Q32
Q48
Q64
Q80
Q96
Q112
Q128
DATA
CLOCK
10
13
9
1
8
2
6
3
VDD = PIN 14
VSS = PIN 7
Pins 4 and 11
not used.
LOGIC DIAGRAM
CLOCK 5
DATA IN 12
D Q
C
1
D Q
C
2
D Q
C
3
D Q
C
16
D Q
C
17
D Q
C
32
D Q
C
33
D Q
C
48
D Q
C
49
D Q
C
64
10 Q16
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
D Q
C
65
80
81
96
97
112
113
128
13 Q32
9 Q48
1 Q64
8 Q80
2 Q96
6 Q112
3 Q128
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394
MC14562B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 05 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.010
0.020
0.030
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

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395
Adc
MC14562B

Characteristic
Symbol

tTLH,
tTHL

Clock to Q
tPLH,
tPHL
Clock Pulse Width

(50% Duty Cycle)
Data to Clock Setup Time
Data to Clock Hold Time
Clock Input Rise and Fall Times
VDD
Min
Typ (7.)
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
600
250
170
1200
500
340
tWH
5.0
10
15
600
220
150
300
110
75
ns
fcl
5.0
10
15
1.9
5.6
8.0
1.1
3.0
4.0
MHz
tsu(1)
5.0
10
15
20
10
0
170
64
60
ns
tsu(0)
5.0
10
15
20
10
0
91
58
48
ns
th(1)
5.0
10
15
350
165
155
263
109
100
ns
th(0)
5.0
10
15
350
200
140
267
140
93
ns
tr, tf
5.0
10
15
15
5
4
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396
MC14562B
VDD
Q16
Q32
Q48
Q64
Q80
Q96
Q112
Q128
DATA
CLOCK
CL
VSS
ID
CL
CL
CL
CL
CL
CL
CL
500 F
fo
CLOCK
VDD
DATA
(f = 1/2 fo)
VDD
VSS
VSS
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397
MC14562B
TIMING DIAGRAM
PIN
NO.S
PULSE 16
PULSE 1
PULSE 32
PULSE 128
CLOCK 5
DATA IN 12
Q16 10
Q32 13
Q28 3
AC TEST WAVEFORMS
PULSE 1
CLOCK
50%
50%
PULSE 2
50%
tWH
tr
tWL
DATA IN
PULSE 16
90%
10%
PULSE 17
VSS
tf
VDD
50%
50%
VSS
tsu(0)
th(0)
50% 10%
Q16
tPHL
PULSE 1
CLOCK
VDD
50%
50%
50%
PULSE 2
90%
VSS
tTHL
PULSE 17
PULSE 16
VDD
50%
50%
VSS
tWH
tWL
DATA IN
50%
tsu(1)
VDD
VDD
50%
VSS
th(1)
Q16
50%
tPLH
90%
10%
VDD
VSS
tTHL
NOTE: The remaining DataBit Outputs (Q32, Q48, Q64, Q80, Q96, Q112 and Q128) will occur at Clock Pulse 32, 48, 64, 80,
96, 112, 128 in the same relationship as Q16.
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398
MC14569B
Programmable Divide-By-N
Dual 4-Bit Binary/BCD
Down Counter
The MC14569B is a programmable dividebyN dual 4bit binary
or BCD down counter constructed with MOS Pchannel and
Nchannel enhancement mode devices (complementary MOS) in a
monolithic structure.
This device has been designed for use with the MC14568B phase
comparator/counter in frequency synthesizers, phaselocked loops,
and other frequency division applications requiring low power
dissipation and/or high noise immunity.
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
Speedup Circuitry for Zero Detection

Each 4Bit Counter Can Divide Independently in BCD or Binary
MC14569BCP
AWLYYWW
1
Mode
Can be Cascaded With MC14526B for
Frequency Synthesizer Applications
All Outputs are Buffered
Schmitt Triggered Clock Conditioning
16
TSSOP16
DT SUFFIX
CASE 948F
14
569B
ALYW
1
16

Parameter
Symbol
VDD
Vin, Vout

(DC or Transient)
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5
10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
may occur.
to the range VSS
(Vin or Vout)
VDD.
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14569BCP
PDIP16
2000/Box
MC14569BDT
TSSOP16
96/Rail
MC14569BDW
SOIC16
47/Rail
MC14569BDWR2
SOIC16
1000/Tape & Reel
March, 2000 Rev. 3
AWLYYWW
1

Iin, Iout
14569B
SOIC16
DW SUFFIX
CASE 751G
399

MC14569B/D
MC14569B
PIN ASSIGNMENT
ZERO
DETECT
CTL1
16
VDD
15
P0
14
P7
P1
13
P6
P2
12
P5
P3
CASCADE
FEEDBACK
VSS
11
P4
10
CTL2
CLOCK
BLOCK DIAGRAM
P0 P1 P2 P3
CTL = Low for Binary Count
CTL = High for BCD Count
CLOCK
CASCADE 7
FEEDBACK
CTL1 CTL2
10
P4 P5 P6 P7
11 12 13
CLOCK
LOAD
BINARY/BCD
COUNTER #1
ZERO DETECT ENCODER
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400
14
BINARY/BCD
COUNTER #2
VDD = PIN 16
VSS = PIN 8
15
1 ZERO
DETECT
MC14569B

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
Vdc
mAdc

http://onsemi.com
401
Adc
MC14569B
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

Characteristic
Symbol
All Types
VDD
Vdc
Min
Typ (6.)
Max
Unit
Output Rise Time
tTLH
5.0
10
15
100
50
40
200
100
80
ns
Output Fall Time
tTHL
5.0
10
15
100
50
40
200
100
80
ns
TurnOn Delay Time

Zero Detect Output
tPLH
5.0
10
15
420
175
125
700
300
250
5.0
10
15
675
285
200
1200
500
400
5.0
10
15
380
150
100
600
300
200
5.0
10
15
530
225
155
1000
400
300
ns
tWH
5.0
10
15
300
150
115
100
45
30
ns
fcl
5.0
10
15
3.5
9.5
13.0
2.1
5.1
7.8
MHz
tTLH, tTHL
5.0
10
15
Q Output
TurnOff Delay Time

Zero Detect Output
NO LIMIT
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402
ns
ns
tPHL
Q Output
Clock Pulse Width
ns
MC14569B
SWITCHING WAVEFORMS
20 ns
20 ns
CLOCK
10%
90%
50%
fin = fmax
tWH
tPLH
Q
10%
tPHL
90%
50%
tTLH
tTHL
Figure 1.
20 ns
20 ns
CLOCK
10%
90%
50%
tWH
tPHL
tPLH
90%
ZERO DETECT
10%
tTLH
tTHL
Figure 2.
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403
MC14569B
PIN DESCRIPTIONS
INPUTS
CONTROLS
P0, P1, P2, P3 (Pins 3, 4, 5, 6) Preset Inputs.

Programmable inputs for the least significant counter. May
be binary or BCD depending on the control input.
P4, P5, P6, P7 (Pins 11, 12, 13, 14) Preset Inputs.
Programmable inputs for the most significant counter. May
be binary or BCD depending on the control input.
Clock (Pin 9) Preset data is decremented by one on
each positive transition of this signal.
Cascade Feedback (Pin 7) This pin is normally set

high. When low, loading of the preset inputs (P0 through P7)
is inhibited, i.e., P0 through P7 are dont cares. Refer to
Table 1 for output characteristics.
CTL1 (Pin 2) This pin controls the counting mode of
the least significant counter. When set high, counting mode
is BCD. When set low, counting mode is binary.
CTL2 (Pin 10) This pin controls the counting mode of
the most significant counter. When set high, counting mode
is BCD. When set low, counting mode is binary.
OUTPUTS
Zero Detect (Pin 1) This output is normally low and

goes high for one clock cycle when the counter has
decremented to zero.
Q (Pin 15) Output of the last stage of the most
significant counter. This output will be inactive unless the
preset input P7 has been set high.
SUPPLY PINS
VSS (Pin 18) Negative Supply Voltage. This pin is

usually connected to ground.
VDD (Pin 16) Positive Supply Voltage. This pin is
connected to a positive supply voltage ranging from 3.0
volts to 18.0 volts.
one pulse appears on the Zero Detect output. (See Timing
Diagram.) The Q output is the output of the last stage of the
most significant counter (See Tables 1 through 5, Mode
Controls.)
When cascading the MC14569B to the MC14526B, the
Cascade Feedback input, Q, and Zero Detect outputs must
be respectively connected to 0, Clock, and Load of the
following counter. If the MC14569B is used alone, Cascade
Feedback must be connected to VDD.
The MC14569B is a programmable dividebyN dual

4bit down counter. This counter may be programmed (i.e.,
preset) in BCD or binary code through inputs P0 to P7. For
each counter, the counting sequence may be chosen
independently by applying a high (for BCD count) or a low
(for binary count) to the control inputs CTL1 and CTL2.
The divide ratio N (N being the value programmed on the
preset inputs P0 to P7) is automatically loaded into the
counter as soon as the count 1 is detected. Therefore, a
division ratio of one is not possible. After N clock cycles,
18
CL = 50 pF
f, FREQUENCY (MHz), TYPICAL
16
14
12
VDD = 15 V
10
8.0
10 V
6.0
4.0
5.0 V
2.0
0
40
20
0
+ 20
+ 40
+ 60
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404
+ 80
+ 100
MC14569B
Table 1. Mode Controls (Cascade Feedback = Low)
Counter Control Values
Divide Ratio
CTL1
CTL2
Zero Detect
0
0
1
1
0
1
0
1
256
160
160
100
256
160
160
100
NOTE: Data Preset Inputs (P0P7) are Dont Cares while Cascade Feedback is
Low.
Table 2. Mode Controls (CTL1 = Low, CTL2 = Low, Cascade Feedback = High)
Divide Ratio
Preset Inputs
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
256
X
2
3
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
15
16
32
64
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
27
128
26
64
Comments
Max Count
Illegal State
Min Count
127
128
256
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
128
136
136
255
255
25
32
24
16
23
8
22
4
21
2
20
1
Counter #2
Binary
Counter #1
Binary
Q Output Active
Bit Value
Counting
Sequence
X = No Output (Always Low)
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405
MC14569B
Table 3. Mode Controls (CTL1 = High, CTL2 = Low, Cascade Feedback = High)
Preset Inputs
Divide Ratio
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
160
X
2
3
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
9
10
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
19
20
30
40
50
60
70

Comments
Max Count
Illegal State
Min Count
80
160
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
80
90
90
150
150
159
159
80
40
20
10
Counter #2
Binary
Counter #1
BCD
Q Output Active
Bit Value
Counting
Sequence
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406
MC14569B
Table 4. Mode Controls (CTL1 = Low, CTL2 = High, Cascade Feedback = High)
Preset Values
Divide Ratio
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
160
X
2
3
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
15
16
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
31
32

Comments
Max Count
Illegal State
Min Count
48
160
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
64
80
112
128
128
144
144
159
159
27
128
26
64
25
32
24
16
23
8
22
4
21
2
20
1
Counter #2
BCD
Counter #1
Binary
Q Output Active
Bit Value
Counting
Sequence
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407
MC14569B
Table 5. Mode Controls (CTL1 = High, CTL2 = High, Cascade Feedback = High)
Preset Values
Divide Ratio
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
100
X
2
3
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
9
10
30
40
50
70
80
40
Comments
Max Count
illegal state
Min Count
80
100
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
80
90
90
99
99
20
10
Counter #2
BCD
Q Output Active
Bit Value
Counter #1
BCD
Counting
Sequence
TIMING DIAGRAM MC14569B

CLOCK
DIVIDE
BY 2
ZERO
DETECT
OUTPUT
DIVIDE
BY 3
DIVIDE
BY 4
DIVIDE
BY 12
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408
10
11
12
13
14
15
16
MC14569B
LOGIC DIAGRAM
CTL1
2
DP Q
D
DP Q
P0
P1
P2
D
DP Q
P3
PE
C
PE
C
DP Q
PE
DP Q
D
PE
C
DP Q
D
DP Q
D
DP Q
D
IU
PE
C
PE
C
PE
C
PE
C
VDD
CASCADE 7
FEEDBACK
CLOCK
VDD
9
1
ZERO
DETECT
P4
P5
P6
P7
CTL2
11
12
13
14
DP D
PE
DP D
PE
DP D
PE
DP D
Q
PE
C
15
10
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409
MC14569B
fin
CF
MC14569B
ZERO DETECT
PE
CF
MC14522B
OR
MC14526B
Q4
PE
DP0 DP3
CF
MC14522B
OR
MC14526B
Q4
Q1/C2
PE
MC14568B
DP0 DP3
DP0 DP3
LSD
fout
MSD
Figure 3. Cascading MC14568B and MC14522B or MC14526B with MC14569B
(40 kHz)
PCin
C1
CT1
VSS
fout
VCO
PCout
G
VSS
VSS
(144 146 MHz)
Q1/C2
PE
VDD
DP0 DP3
MC14011
CF
MC14569B
ZERO DETECT
MIXER
2k
2M
CRYSTAL
OSCILLATOR
Frequencies shown in parenthesis are given as an example
(143.5 MHz)
Figure 4. Frequency Synthesizer with MC14568B and MC14569B Using a Mixer

(Channel Spacing 10 kHz)
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410
MC14572UB
Hex Gate
The MC14572UB hex functional gate is constructed with MOS
monolithic structure. These complementary MOS logic gates find
primary use where low power dissipation and/or high noise immunity
is desired. The chip contains four inverters, one NOR gate and one
NAND gate.
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NOR Input Pin Adjacent to VSS Pin to Simplify Use As An Inverter
NAND Input Pin Adjacent to VDD Pin to Simplify Use As An
Inverter
NOR Output Pin Adjacent to Inverter Input Pin For OR Application
NAND Output Pin Adjacent to Inverter Input Pin For AND
Application
MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MC14572UBCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14572U
AWLYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966

Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Symbol
VDD
Vin, Vout
Iin, Iout

(DC or Transient)
Package
Shipping
MC14572UBCP
PDIP16
2000/Box
MC14572UBD
SOIC16
48/Rail
MC14572UBDR2
SOIC16
2500/Tape & Reel
MC14572UBF
SOEIAJ16
See Note 1.
MC14572UBFEL
SOEIAJ16
See Note 1.
to the range VSS
(Vin or Vout)
VDD.
Device

March, 2000 Rev. 3
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
may occur.
MC14572UB
AWLYWW
411

MC14572UB/D
MC14572UB
PIN ASSIGNMENT
OUTA
16
VDD
INA
15
IN 2F
OUTB
14
IN 1F
INB
13
OUTF
OUTC
12
INE
IN 1C
11
OUTE
IN 2C
10
IND
VSS
OUTD
LOGIC DIAGRAM
2
10
12
11
14
13
15
VDD = PIN 16
VSS = PIN 8
CIRCUIT SCHEMATIC
VDD
VDD
VDD
7
1
13
6
VSS
14
15
VSS
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412
VSS
MC14572UB
55_C
VDD
Characteristic
25_C
125_C
Symbol
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
1 Level
VIH
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

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413
Adc
MC14572UB

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL

tPLH,
tPHL
VDD
Min
Typ (8.)
Max
5.0
10
15
180
90
65
360
180
130
5.0
10
15
100
50
40
200
100
80
5.0
10
15
90
50
40
180
100
80
Unit
ns
ns
ns
VDD
PULSE
GENERATOR
VDD
INPUT
7
16
INPUT
2
PULSE
GENERATOR
OUTPUT
16
OUTPUT
1
8
VSS
CL
VSS
CL
VDD
20 ns
16
PULSE
GENERATOR
INPUT
15
INPUT
14
OUTPUT
VSS
90%
50%
10%
tPHL
13
8
90%
50%
10%
CL
OUTPUT
90%
50%
10%
90%
50%
10%
Figure 1. Switching Time Test Circuits and Waveforms
414
VSS
tPLH
tf
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20 ns
VDD
tr
VOH
VOL
MC14584B
Hex Schmitt Trigger
The MC14584B Hex Schmitt Trigger is constructed with MOS
may be used in place of the MC14069UB hex inverter for enhanced
noise immunity to square up slowly changing waveforms.
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MARKING
DIAGRAMS
14

Can Be Used to Replace MC14069UB
For Greater Hysteresis, Use MC14106B which is PinforPin
PDIP14
P SUFFIX
CASE 646
MC14584BCP
AWLYYWW
1
Replacement for CD40106B and MM74Cl4
14
SOIC14
D SUFFIX
CASE 751A

Parameter
Value
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Symbol
VDD
Vin, Vout
Iin, Iout

(DC or Transient)
14
TSSOP14
DT SUFFIX
CASE 948G
14
584B
ALYW
1
14
may occur.
to the range VSS
(Vin or Vout)
VDD.
14584B
AWLYWW
SOEIAJ14
F SUFFIX
CASE 965
MC14584B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14584BCP
PDIP14
2000/Box
MC14584BD
SOIC14
55/Rail
MC14584BDR2
SOIC14
2500/Tape & Reel
MC14584BDT
TSSOP14
96/Rail
MC14584BDTEL
MC14584BF
SOEIAJ14
See Note 1.
MC14584BFEL
SOEIAJ14
See Note 1.

March, 2000 Rev. 3
415

MC14584B/D
MC14584B
PIN ASSIGNMENT
IN 1
14
VDD
OUT 1
13
IN 6
IN 2
12
OUT 6
OUT 2
11
IN 5
OUT 5
IN 3
10
OUT 3
IN 4
VSS
OUT 4
LOGIC DIAGRAM
1
11
10
13
12
VDD = PIN 14
VSS = PIN 7
EQIVALENT CIRCUIT SCHEMATIC

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416
MC14584B

Characteristic
Output Voltage
Vin = VDD
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Hysteresis Voltage
VH (7.)
5.0
10
15
0.27
0.36
0.77
1.0
1.3
1.7
0.25
0.3
0.6
0.6
0.7
1.1
1.0
1.2
1.5
0.21
0.25
0.50
1.0
1.2
1.4
Threshold Voltage
PositiveGoing
VT+
5.0
10
15
1.9
3.4
5.2
3.5
7.0
10.6
1.8
3.3
5.2
2.7
5.3
8.0
3.4
6.9
10.5
1.7
3.2
5.2
3.4
6.9
10.5
5.0
10
15
1.6
3.0
4.5
3.3
6.7
9.7
1.6
3.0
4.6
2.1
4.6
6.9
3.2
6.7
9.8
1.5
3.0
4.7
3.2
6.7
9.9
Vin = 0

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOH
Source
Sink

Per Package)
buffers switching)
NegativeGoing
VT
mAdc

Adc
Vdc
Vdc
7. VH = VT+ VT (But maximum variation of VH is specified as less than VT + max VT min).
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417
Vdc
MC14584B

Characteristic
VDD
Vdc
Min
Typ (8.)
Max
Unit
Output Rise Time
tTLH
5.0
10
15
100
50
40
200
100
80
ns
Output Fall Time
tTHL
5.0
10
15
100
50
40
200
100
80
ns
tPLH, tPHL
5.0
10
15
125
50
40
250
100
80
ns
Symbol
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418
MC14584B
20 ns
VDD
14
PULSE
GENERATOR
INPUT
OUTPUT
INPUT
7 VSS
20 ns
tPHL
CL
VDD
90%
50%
10%
VSS
tPLH
90%
50%
10%
OUTPUT
tf
VOH
VOL
tr
Vin
VH
Vout
VDD
VH
VT+
VT
Vin
VDD
VT+
VT
Vin
VSS
VSS
VDD
VDD
Vout
Vout
VSS
VSS
(a) Schmitt Triggers will square up inputs with slow

rise and fall times.
(b) A Schmitt trigger offers maximum noise immunity

in gate applications.
Figure 2. Typical Schmitt Trigger Applications
VDD
VT
VT+
VH
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419
VDD
MC14585B
4-Bit Magnitude
Comparator
The MC14585B 4Bit Magnitude Comparator is constructed with
complementary MOS (CMOS) enhancement mode devices. The
circuit has eight comparing inputs (A3, B3, A2, B2, A1, B1, A0, B0),
three cascading inputs (A < B, A = B, and A > B), and three outputs (A
< B, A = B, and A > B). This device compares two 4bit words (A and
B) and determines whether they are less than, equal to, or greater
than by a high level on the appropriate output. For words greater than
4bits, units can be cascaded by connecting outputs (A > B), (A < B),
and (A = B) to the corresponding inputs of the next significant
comparator. Inputs (A < B), (A = B), and (A > B) on the least
significant (first) comparator are connected to a low, a high, and a low,
respectively.
Applications include logic in CPUs, correction and/or detection of
instrumentation conditions, comparator in testers, converters, and
controls.

Expandable
Applicable to Binary or 8421BCD Code
Can be Cascaded See Fig. 3

Parameter
Symbol
VDD
Unit
0.5 to +18.0
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Vin, Vout
Iin, Iout
Value

(DC or Transient)
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MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648
MC14585BCP
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
14585B
AWLYWW
1
16
SOEIAJ16
F SUFFIX
CASE 966
MC14585B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device
Package
Shipping
MC14585BCP
PDIP16
2000/Box
MC14585BD
SOIC16
48/Rail
MC14585BDR2
SOIC16
2500/Tape & Reel
SOEIAJ16
See Note 1.
MC14585BF

may occur.
to the range VSS
(Vin or Vout)
VDD.
March, 2000 Rev. 3
420

MC14585B/D
MC14585B
PIN ASSIGNMENT
B2
16
VDD
A2
15
A3
(A = B)out
14
B3
(A
13
(A
12
u B)out
(A t B)out
u B)in
(A t B)in
(A = B)in
11
B0
A1
10
A0
VSS
B1
BLOCK DIAGRAM
(A > B)in
(A = B)in
(A < B)in
A0
B0
A1
B1
A2
B2
A3
B3
4
6
5
10
11
7
9
2
1
15
14
(A > B)out
13
(A = B)out
(A < B)out
12
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE (x = Dont Care)

Inputs
Comparing
Outputs
Cascading
A3, B3
A2, B2
A1, B1
A0, B0
A<B
A=B
A>B
A<B
A=B
A>B
A3 > B3
A3 = B3
A3 = B3
A3 = B3
x
A2 > B2
A2 = B2
A2 = B2
x
x
A1 > B1
A1 = B1
x
x
x
A0 > B0
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
1
1
1
1
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A0 = B0
A0 = B0
A0 = B0
A0 = B0
0
0
1
1
0
1
0
1
x
x
x
x
0
0
1
1
0
1
0
1
1
0
0
0
A3 = B3
A3 = B3
A3 = B3
A2 = B2
A2 = B2
A2 < B2
A1 = B1
A1 < B1
x
A0 < B0
x
x
x
x
x
x
x
x
x
x
x
1
1
1
0
0
0
0
0
0
A3 < B3
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421
MC14585B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1 Level
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

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422
Adc
MC14585B

Characteristic
Symbol

tTLH,
tTHL
TurnOn, TurnOff Delay Time

tPLH,
tPHL
VDD
Min
Typ (8.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
430
180
130
860
360
260
Unit
ns
ns
20 ns
20 ns
VDD
A3
1
2f
VSS
VDD
B3
VSS
20 ns
20 ns
VOH
(A > B)out
VOL
50%
B0
10%
VOH
VSS
tPLH
(A = B)out
tPHL
VOL
VOH
90%
VOH
(A < B)out
VDD
90%
50%
(A < B)out
10%
VOL
tTLH
Inputs (A>B) and (A=B) high, and inputs B2, A2, B1,
A1, B0, A0 and (A<B) low.
VOL
tTHL
Inputs (A>B) and (A=B) high, and inputs B3, A3, B2,
A2, B1, A1, A0, and (A<B) low.
Figure 1. Dynamic Power Dissipation

Signal Waveforms
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423
MC14585B
(A>B)
(A=B)
(A<B)
(A>B)
(A=B)
B3 A3 B2 A2 B1 A1 B0 A0
OUTPUT
MC14585B
VSS VDD VSS

(A<B)
WORD
B = B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
WORD
A=
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
INPUTS
MC14585B
WORD B = B11, B10, ..., B0.

WORD A = A11, A10, ..., A0.
(A>B)
(A=B)
(A<B)
MC14585B
OUTPUTS
Figure 3. Cascading Comparators
LOGIC DIAGRAM
A3
B3
A2
B2
A1
B1
A0
B0
(A < B)in
15
14
2
1
12
9
10
11
5
3
(A = B)in
(A > B)in
(A < B)out
6
13
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424
(A = B)out
(A > B)out
MC14598B
8-Bit Bus-Compatible
Latches
The MC14598B is an 8bit latch addressed with an external binary
address. The 8 latchoutputs are high drive, threestate and bus line
compatible. The drive capability allows direct applications with MPU
systems such as the Motorola 6800 family.
The latches of the MC14598B are accessed via the Address pins,
A0, A1, and A2.
All 8 outputs from the latches are available in parallel when Enable
is in the low state. Data is entered into a selected latch from the Data
pin when the Strobe is high. Master reset is available on both parts.
Serial Data Input

ThreeState Bus Compatible Parallel Outputs
ThreeState Control Pin (Enable) TTL Compatible Input
Open Drain Full Flag (Multiple Latch WireO Ring)
Master Reset
Level Shifting Inputs on All Except Enable
Diode Protection All Inputs
Supply Voltage Range 3.0 Vdc to 18 Vdc
Capable of Driving TTL Over Rated Temperature Range
With Fanout as Follows:
1 TTL Load
4 LSTTL Loads
18
PDIP18
P SUFFIX
CASE 707
Parameter
Value
Unit
0.5 to +18.0
Vin
Input Voltage Range,

Enable (DC or Transient)
0.5 to VDD + 0.5
Vin
Input Voltage Range, All Other

Inputs (DC or Transient)
0.5 to VDD + 12
Vout
Output Voltage Range,

(DC or Transient)
0.5 to VDD + 0.5

10
mA
PD
Power Dissipation,
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
may occur.
March, 2000 Rev. 3
MC14598BCP
AWLYYWW
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
VDD
Iin, Iout
MARKING
DIAGRAMS

Symbol
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425
Device
MC14598BCP
Package
Shipping
PDIP18
20/Rail

range VSS
(Vin or Vout)
VDD.

MC14598B/D
MC14598B
PIN ASSIGNMENT
D0
18
VDD
RESET
17
D1
DATA
16
D2
ENABLE
15
D3
NC
14
D4
STROBE
13
D5
A0
12
D6
A1
11
D7
VSS
10
A2
BLOCK DIAGRAMS
MC14598B
ENABLE
OUTPUT
TRUTH TABLE
4
RESET
DATA
STROBE
A0
A1
A2
2
3
6
7
8 ADDRESS
10 DECODER
VDD = 18
VSS = 9
8
LATCHES
THREE
STATE
OUTPUT
BUFFERS
1
17
16
15
14
13
12
11
D0
D1
D2
D3
D4
D5
D6
D7
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426
Enable
Outputs
High Impedance
Dn
Dn = State of nth latch

NC = NO CONNECTION
MC14598B

Characteristic
55_C
25_C
(3.)
125_C
Min
Max
Min
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage (4.) Enable 0 Level

(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
0.8
1.6
2.4
1.1
2.2
3.4
0.8
1.6
2.4
0.8
1.6
2.4
1 Level
VIH
5.0
10
15
2.0
6.0
10
2.0
6.0
10
1.9
3.1
4.3
2.0
6.0
10
Output Voltage
Vin = VDD or 0
Symbol
VDD
Vdc
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Input Voltage
0 Level
Other Inputs
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH

(Full Sink Only)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Source
Typ
Vdc
Vdc
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
IOH
Vdc
mAdc
5.0
10
15
1.0
1.0
2.0
6.0
12
1.0
IOL
5.0
10
15
1.6
1.6
3.2
6.0
12
1.6
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
ITL
15
0.1
0.00001
0.1
3.0
Adc
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
Total Supply Current at an

**External Load Capacitance of
**130 pF (4.)

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427
Adc
MC14598B
SWITCHING CHARACTERISTICS (5.) (TA = 25_C, CL = 130 pF + 1 TTL Load)
All Types
VDD
Vdc
Min
Typ (6.)
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
160
125
100
320
250
200
Strobe to Output
5.0
10
15
200
100
80
400
200
160
Reset to Output
5.0
10
15
175
90
70
350
180
140
5.0
10
15
320
240
160
160
120
80
Strobe
5.0
10
15
200
100
80
100
50
40
Increment
5.0
10
15
200
100
80
100
50
40
Reset
5.0
10
15
300
160
100
150
80
50
5.0
10
15
100
50
35
50
25
20
5.0
10
15
200
100
70
100
50
35
5.0
10
15
100
50
35
50
25
20
5.0
10
15
100
50
35
50
25
20
5.0
10
15
20
20
20
25
15
10
Characteristic
Symbol

tTLH,
tTHL

Enable to Output
tPLH,
tPHL
Pulse Width
Enable
Setup Time
Data
tWH,
tWL
ns
ns
ns
th
ns
Address
Reset Removal Time
ns
tsu
Address
Hold Time
Data
Unit
trem
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428
ns
MC14598B
MC14598B FUNCTION DIAGRAM
RESET 2
VDD
DATA 3
1 D0
TO OTHER
LATCHES
STROBE 6
ENABLE 4
VSS
EACH LATCH
TO OTHER
LATCHES
ZERO
SELECT
17
16
15
14
13
12
11
A0 7
ADDRESS
DECODER
A1 8
ADDITIONAL 7 LATCHES
A2 10
(M.S.B)
MC14598B TIMING DIAGRAM

90%
10%
50%
tPLH
tTHL
D7
90%
10%
50%
tPLH
tPHL
tTLH
RESET
20 ns
tW
90%
10%
50%
A0, A1, A2
tsu
DATA
tsu
th
90%
10%
STROBE
50%
90%
10%
20 ns
20 ns
ENABLE
*
tW
*1.4 V with VDD = 5.0 V

NOTES:
1. Highimpedance output state (another device controls bus).
2. Output Load as for MC14597B.
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429
tW
th
D1
D2
D3
D4
D5
D6
D7
MC14598B
LATCH TRUTH TABLE
TRUTH TABLE FOR MC14597B
Address
Latch
Other
Latches
Strobe
Reset
Data
Increment
Address
Counter
Full
Count Up
No Change
Reset to Zero
Set to One
No Change
Set to One
If at
ADDRESS 7
To Zero on
Falling Edge
of STROBE
Enable
Reset
X
X
X
*= No change in state of latch

X = Dont care
X = Dont care
TEST LOAD
ALL OUTPUTS
+5.0 V
RL = 2.5 k
Dn
130 pF
11.7 k
The information contained herein is for guidance only,

with no warranty of any type, expressed or implied.
Motorola reserves the right to make any changes to the
information and the product(s) to which the information
applies and to discontinue manufacture of the product(s) at
any time.
Circuit diagrams external to or containing Motorola

products are included as a means of illustration only.
Complete information sufficient for construction purposes
may not be fully illustrated. Although the information herein
has been carefully checked and is believed to be reliable.
Motorola assumes no responsibility for inaccuracies.
Information herein does not convey to the purchaser any
license under the patent rights of Motorola or others.
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CHAPTER 7
CMOS Reliability
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RELIABILITY
Paramount in the mind of every semiconductor user is the
question of device performance versus time. After the
applicability of a particular device has been established, its
effectiveness depends on the length of troublefree service it
can offer. The reliability of a device is exactly that an
expression of how well it will serve the customer. The
following discussion will attempt to present an overview of
ON Semiconductors reliability efforts.
usually expressed in percent failures per thousand hours.

Other forms include FIT (Failures in Time = (%/103 hrs) x
104 = 109 failures per hour) and MTTF (Mean Time To
Failure) or MTBF (Mean Time Between Failures), both
being equal to 1/ and having units of hours.
Since reliability evaluations usually involve only samples
of an entire population of devices, the concepts of the
Central Limit Theorem apply and is calculated using x2
distribution through the equation:
BASIC CONCEPTS
It is essential to begin with an explanation of the various
parameters of Reliability. These are probably summarized
best in the Bathtub Curve (Figure 1). The reliability
performance of a device is characterized by three phases:
infant mortality, useful life, and wearout. When a device is
produced, there is often a small distribution of failure
mechanisms which will exhibit themselves under relatively
moderate stress levels and therefore appear early. This
period of early failures, termed infant mortality is reduced
significantly through proper manufacturing controls and
screening techniques. The most effective period is that in
which only occasional random failure mechanisms appear.
The useful life typically spans a long period of time with a
very low failure rate. The final period is that in which the
devices literally wear out due to continuous phenomena
which existed at the time of manufacture. Using strictly
controlled design techniques and selectivity in applications,
this period is shifted well beyond the lifetime required by the
user.
vx
(x, 2r + 2)
2nt
where x =
100 CL
100
CL = Confidence Limit in percent

r = Number of rejects
n = Number of devices
t = Duration of test
The confidence limit is the degree of conservatism desired
in the calculation. The Central Limit Theorem states that the
values of any sample of units out of a large population will
produce a normal distribution. A 50% confidence limit is
termed the best estimate and is the mean of this distribution.
A 90% confidence limit is a very conservative value and
results in a higher which represents the point at which 90%
of the area of the distribution is to the left of that value
(Figure 2). The term (2r + 2) is called the degrees of freedom
and is an expression of the number of rejects in a form
suitable to x2 tables.
FREQUENCY
50% CL
FAILURE RATE
INFANT MORTALITY
(SUCH AS EARLY
BURNIN FAILURES)
USEFUL LIFE
10
100
1000 10,000 100,000

TIME (HOURS)
90% CL
, FAILURE RATE
WEAROUT
FAILURES
Figure 2.
The number of rejects is a critical factor since the

definition of rejects often differs between manufacturers.
While ON Semiconductor uses data sheet limits to
determine failures, sometimes rejects are counted only if
they are catastrophic. Due to the increasing chance of a test
not being representative of the entire population, as sample
size and test time are decreased, the x2 calculation produces
surprisingly high values of for short test durations even
though the true long term failure rate may be quite low. For
this reason relatively large amounts of data must be gathered
to demonstrate the real long term failure rate.
Since this would require years of testing on thousands of
devices, methods of accelerated testing have been
developed.
1,000,000
Figure 1.
Both the infant mortality and random failure rate regions

can be described through the same types of calculations.
During this time the probability of having no failures to a
specific point in time can be expressed by the equation:
Po = e t
where is the failure rate and t is time. Since is changing

rapidly during infant mortality, the expression does not
become useful until the random period, where is relatively
constant. In this equation is failures per unit of time. It is
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432
devices will be used (Figure 3). For Discrete products, 0.7

eV is generally applied.
To accomplish this, the time in device hours (t1) and
temperature (T1) of the test are plotted as point P1. A vertical
line is drawn at the temperature of interest (T2) and a line
with a 1.0 eV slope is drawn through point P1.
Its intersection with the vertical line defines point P2, and
determines the number of equivalent device hours (t2). This
number may then be used with the x2 formula to determine
the failure rate at the temperature of interest. Assuming T1
of 125_C at t1 of 10,000 hours, a t2 of 7.8 million hours
results at a T2 of 50_C. If one reject results in the 10,000
device hours of testing at 125_C, the failure rate at that
temperature will be 0.1%/1,000 hours using a 60%
confidence level. One reject at the equivalent 7.8 million
device hours at 50_C will result in a 0.0008%/1,000 hour
failure rate, as illustrated in Figure 4.
Three parameters determine the failure rate quoted by the
manufacturer: the failure rate at the test temperature, the
activation energy employed, and the difference between the
test temperature and the temperature of the quoted . A term
often used in this manipulation is the acceleration factor
which is simply the equivalent device hours at the lower
temperature divided by the actual test device hours.
Every device will eventually fail, but with the present
techniques in Semiconductor design and applications, the
wearout phase is extended far beyond the lifetime required.
During wearout, as in infant mortality, the failure rate is
changing rapidly and therefore loses its value. The
parameter used to describe performance in this area is
Median Life and is the point at which 50% of the devices
have failed. There are currently only few significant wearout
mechanisms: electromigration of circuit metallization,
electrolytic corrosion in plastic devices and metal fatigue for
Power devices.
Years of semiconductor device testing has shown that

temperature will accelerate failures and that this behavior
fits the form of the Arrhenius equation:
R (t) = R0(t)e /kT
where R(t) = Reaction rate as a function of time and

temperature
R0 = A constant
t
= Time
= Activation energy in electron volts
k = Boltzmans constant
T = Temperature in degrees Kelvin
To provide timetemperature equivalents this equation is
applied to failure rate calculations in the form:
t = t0e /kT
where t = time
t0 = A constant
The Arrhenius equation essentially states that reaction

rate increases exponentially with temperature. This
produces a straight line when plotted in loglinear paper
with a slope expressed by . may be physically
interpreted as the energy threshold of a particular reaction or
failure mechanism. The activation energy exhibited by
semiconductors varies from about 0.3 eV. Although the
relationships do not prohibit devices from having poor
failure rates and high activation energies, good performance
usually does not imply a high . Studies by Bell Telephone
Laboratories have indicated that an overall for
semiconductors is 1.0 eV. This value has been accepted by
the
Rome
Air
Development
Command
for
timetemperature acceleration in powered burnin. Data
taken by ON Semiconductor on Integrated Circuits have
verified this number and it is therefore applied as our
standard timetemperature regression for extrapolation of
high temperature failure rates to temperatures at which the
1.6
2.0
2.4
2.8
3.2
3.6
100
100 k
10
, FAILURE RATE (%/1000 HOURS)
TIME (HOURS)
1.2
1000 k
10 k
t2
P2
1.0 k
100
10
t1
P1
1.0 eV
SLOPE
1.0
0.1
500
T1
200
100
TEMPERATURE (C)
1.2
1.6
2.0
2.4
2.8
3.2
3.6
100 k
1.0
2
0.01
0.0001
T2
50
0.00001
500
Figure 3. Normalized TimeTemperature

Regressions for Various Activation Energy Values
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200
100
TEMPERATURE (C)
Figure 4. Failure Rate
50
For increased flexibility in working with a broad range of

device hours, the timetemperature regression lines have
been normalized to 500_C and the time scale omitted,
permitting the user to define the scale based on his own
requirements.
where
TJ
TA
PD
THERMAL MANAGEMENT
Circuit performance and longterm circuit reliability are
affected by die temperature. Normally, both are improved by
keeping the IC junction temperatures low.
Electrical power dissipated in any integrated circuit is a
source of heat. This heat source increases the temperature of
the die relative to some reference point, normally the
ambient temperature of 25_C in still air. The temperature
increase, then, depends on the amount of power dissipated
in the circuit and on the net thermal resistance between the
heat source and the reference point.
The temperature at the junction is a function of the
packaging and mounting systems ability to remove heat
generated in the circuit from the junction region to the
ambient environment. The basic formula for converting
power dissipation to estimated junction temperature is:
JC
CA
JA
ambient
TJ = TA + PD(JC + CA)
(1)
TJ = TA + PD(JA)
(2)
= maximum junction temperature

= maximum ambient temperature
= calculated maximum power dissipation
including effects of external loads (see
Power Dissipation in section III).
= average thermal resistance, junction to case
= average thermal resistance, case to ambient
= average thermal resistance, junction to
This ON Semiconductor recommended formula has been

approved by RADC or DESC for calculating a practical
maximum
operating
junction
temperature
for
MILM38510 (JAN) devices.
Only two terms on the right side of equation (1) can be
varied by the user the ambient temperature, and the
device casetoambient thermal resistance, CA. (To some
extent the device power dissipation can also be controlled,
but under recommended use the VCC supply and loading
dictate a fixed power dissipation.) Both system air flow and
the package mounting technique affect the CA thermal
resistance term. JC is essentially independent of air flow
and external mounting method, but is sensitive to package
material, die bonding method, and die area.
or
Thermal Resistance in Still Air

Package Description
JC (_C/Watt)
No.
Leads
Body
Style
Body
Material
Body
WxL
Die
Bonds
Die Area
(Sq. Mils)
Flag Area
(Sq. Mils)
Avg.
Max.
14
16
DIL
DIL
Epoxy
Epoxy
1/4 x 3/4
1/4 x 3/4
Epoxy
Epoxy
4096
4096
6,400
12,100
38
34
61
54
NOTES:
1. All plastic packages use copper lead frames.
2. Body style DIL is DualInLine.
3. Standard Mounting Method: DualInLine Socket or P/C board with no contact between bottom of package and socket or P/C board.
Figure 5. Thermal Resistance Values for Standard I/C Packages
These figures show the proportionate increase in the

junction temperature of each dual inline package as the air
passes over each device. For higher rates of air flow the
change in junction temperature from package to package
down the airstream will be lower due to greater cooling.
For applications where the case is held at essentially a

fixed temperature by mounting on a large or
temperaturecontrolled heat sink, the estimated junction
temperature is calculated by:
TJ = TC + PD(JC)
(3)
where TC = maximum case temperature and the other

parameters are as previously defined.
The maximum and average JC resistance values for
standard IC packages are given in Figure 5.
AIR FLOW
The majority of users employ some form of airflow
cooling. As air passes over each device on a printed circuit
board, it absorbs heat from each package. This heat gradient
from the first package to the last package is a function of the
air flow rate and individual package dissipations. Figure 6
provides gradient data at power levels of 200 mW, 250 mW,
300 mW, and 400 mW with an air flow rate of 500 Ifpm.
Power Dissipation
(mW)
Junction Temperature Gradient

(_C/Package)
200
0.4
250
0.5
300
0.63
400
0.88
Devices mounted on 0.062 PC board with Z axis spacing of 0.5.

Air flow is 500 Ifpm along the Z axis.
Figure 6. Thermal Gradient of Junction Temperature

(16Pin DualinLine Package)
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OPTIMIZING THE LONG TERM RELIABILITY OF

PLASTIC PACKAGES
Todays plastic integrated circuit packages are as reliable
as ceramic packages under most environmental conditions.
However when the ultimate in system reliability is required,
thermal management must be considered as a prime system
design goal.
Modern plastic package assembly technology utilizes
gold wire bonded to aluminum bonding pads throughout the
electronics industry. When exposed to high temperatures for
protracted periods of time an intermetallic compound can
form in the bond area resulting in high impedance contacts
and degradation of device performance. Since the formation
of intermetallic compounds is directly related to device
junction temperature, it is incumbent on the designer to
determine that the device junction temperatures are
consistent with system reliability goals.
Table 1 is graphically illustrated in Figure 7 which shows

that the reliability for plastic and ceramic devices are the
same until elevated junction temperatures induces
intermetallic failures in plastic devices. Early and midlife
failure rates of plastic devices are not effected by this
intermetallic mechanism.
Predicting Bond Failure Time:
Based on the results of almost ten (10) years of +125_C

operating life testing, a special arrhenius equation has been
developed to show the relationship between junction
temperature and reliability.
Eq. (1) T = (6.376 x 109)e
TJ = 80 C
TJ = 90 C
TJ = 100C
TJ = 110C
TJ = 120C
TJ = 130C
NORMALIZED FAILURE RATE
FAILURE RATE OF PLASTIC = CERAMIC

UNTIL INTERMETALLIC FAILURES OCCUR
10
100
1000
TIME, YEARS
11554.267
273.15 + TJ
Figure 7. Failure Rate versus Time

Junction Temperature
Where: T = Time in hours to 0.1% bond failure

T = (1 failure per 1,000 bonds).
TJ = Device junction temperature, _C.
And:
Eq. (2) TJ = TA + PDJA = TA + TJ
Procedure
Device junction temperature, _C.

Ambient temperature, _C.
Device power dissipation in watts.
Device thermal resistance, junction to air,
_C/Watt.
TJ = Increase in junction temperature due to
onchip power dissipation.
Table 1 shows the relationship between junction
temperature, and continuous operating time to 0.1%. bond
failure, (1 failure per 1,000 bonds).
Where: TJ =
TA =
PD =
JA =
Table 1. Device Junction Temperature versus Time

to 0.1% Bond Failures
Junction
Temperature _C
Time, Hours
Time, Years
80
1,032,200
117.8
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
After the desired system failure rate has been established

for failure mechanisms other than intermetallics, each
device in the system should be evaluated for maximum
junction temperature. Knowing the maximum junction
temperature, refer to Table 1 or Equation 1 to determine the
continuous operating time required to 0.1% bond failures
due to intermetallic formation. At this time, system
reliability departs from the desired value as indicated in
Figure 7.
Air flow is one method of thermal management which
should be considered for system longevity. Other commonly
used methods include heat sinks for higher powered devices,
refrigerated air flow and lower density board stuffing. Since
CA is entirely dependent on the application, it is the
responsibility of the designer to determine its value. This can
be achieved by various techniques including simulation,
modeling, actual measurement, etc.
The material presented here emphasizes the need to
consider thermal management as an integral part of system
design and also the tools to determine if the management
methods being considered are adequate to produce the
desired system reliability.
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134C
TJ SOIC
400
121C
100C 99C
TJ PDIP
PD
PDIP & SOIC
300
7 mW/C
200
81C
75C
100
50C
25C
65C
TA, AMBIENT TEMPERATURE
125C
150C
Figure 8. Junction Temperature for Worst Case

CMOS Logic Device
135C
500
130C
400
PD
PDIP & SOIC
300
125C
129C
TJ SOIC
100C
98C
89C
75C
7 mW/C
200
TJ PDIP
100
58C
50C
25C
65C
TA, AMBIENT TEMPERATURE
125C
PD, MAXIMUM POWER DISSIPATION PER PACKAGE (mW)
139C
125C
500
TJ , JUNCTION TEMPERATURE ( C)
TJ , JUNCTION TEMPERATURE ( C)
137C
PD, MAXIMUM POWER DISSIPATION PER PACKAGE (mW)
150C
Figure 9. Junction Temperature for Typical

CMOS Logic Device
This graph illustrates junction temperature for the worst case CMOS
Logic device (MC14007UB) smallest die area operating at
maximum power dissipation limit in still air. The solid line indicates
the junction temperature, TJ, in a DualInLine (PDIP) package and
in a Small Outline IC (SOIC) package versus ambient temperature,
TA. The dotted line indicates maximum allowable power dissipation
derated over the ambient temperature range, 25_C to 125_C.
This graph illustrates junction temperature for a CMOS Logic device

(MC14053B) average die area operating at maximum power
dissipation limit in still air. The solid line indicates the junction
temperature, TJ, in a DualInLine (PDIP) package and in a Small
Outline IC (SOIC) package versus ambient temperature, TA. The
dotted line indicates maximum allowable power dissipation derated
over the ambient temperature range, 25_C to 125_C.
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CHAPTER 8
Equivalent Gate Count
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EQUIVALENT GATE COUNT

The following is a list of equivalent gate counts for some of ON Semiconductors CMOS devices. In general for CMOS,
the number of equivalent gates is equal to the total number of transistors on chip divided by four. This list includes only those
devices with equivalent gate counts known at the time of this printing.
DEVICE
EQUIVALENT
GATE COUNT
DEVICE
EQUIVALENT
GATE COUNT
MC14001B
MC14001UB
MC14007UB
MC14008B
MC14011B
MC14011UB
MC14012B
MC14013B
MC14014B
MC14015B
MC14016B
MC14017B
MC14018B
MC14020B
MC14021B
MC14023B
MC14024B
MC14025B
MC14028B
MC14029B
MC14040B
MC14042B
MC14046B
MC14049UB
MC14049B
MC14050B
MC14051B
MC14052B
MC14053B
MC14060B
MC14066B
MC14067B
MC14069UB
MC14071B
MC14073B
MC14076B
8
4
1.5
40
8
4
7
16
74
53
8
62.5
38.25
84
74
9
59
9
26
65.5
73
17.5
35
3
9
6
48.5
38.5
38
73.5
13
65
3
10
10.5
32.5
MC14081B
MC14082B
MC14093B
MC14094B
MC14099B
MC14174B
MC14175B
MC14490
MC14503B
MC14504B
MC14511B
MC14512B
MC14514B
MC14515B
MC14516B
MC14517B
MC14518B
MC14520B
MC14526B
MC14528B
MC14532B
MC14536B
MC14538B
MC14541B
MC14543B
MC14549B
MC14551B
MC14553B
MC14555B
MC14556B
MC14557B
MC14559B
MC14562B
MC14569B
MC14572UB
MC14584B
10
8
18
79
70
43.5
39.5
136.5
17
37.5
54
17.25
59
67
61
119
43.5
43.5
86
24
38.5
103
38
93
52
122
35
147.5
21
25
232.5
122
206
156
4
18
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CHAPTER 9
Packaging Information Including Surface Mounts
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PACKAGE DIMENSIONS
The standard package availability for each device is indicated on the front page of the individual data sheets. Dimensions
for the packages are given in this chapter. Surface mount packages may be special ordered by specifying the following suffixes:
D (narrow SOIC), DW (wide SOIC), or DT (TSSOP). For example, to order a quad NOR gate, use MC14001BD.
14-Pin Packages
PDIP14
P SUFFIX
PLASTIC PACKAGE
CASE 64606
ISSUE M
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
T
SEATING
PLANE
K
H
D 14 PL
0.13 (0.005)
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
10_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
10_
0.38
1.01
SOIC14
D SUFFIX
PLASTIC PACKAGE
CASE 751A03
ISSUE F
NOTES:
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
A
14
B
1
P 7 PL
0.25 (0.010)
R X 45 _
T
SEATING
PLANE
0.25 (0.010)
T B
D 14 PL
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DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019
14-Pin Packages
(continued)
TSSOP14
DT SUFFIX
PLASTIC PACKAGE
CASE 948G01
ISSUE O
14X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
NOTES:
Y14.5M, 1982.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE W.
N
2X
14
L/2
0.25 (0.010)
M
B
U
L
PIN 1
IDENT.
F
7
0.15 (0.006) T U
DETAIL E
K
A
V
K1
J J1
SECTION NN
W
C
0.10 (0.004)
T SEATING
PLANE
DETAIL E
SOEIAJ14
F SUFFIX
PLASTIC PACKAGE
CASE 96501
ISSUE O
14
Q1
E HE
M_
L
DETAIL P
Z
D
VIEW P
A1
b
0.13 (0.005)
0.10 (0.004)
http://onsemi.com
442
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.020
0.024
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
NOTES:
Y14.5M, 1982.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
1.42
INCHES
MIN
MAX
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
0.056
16-Pin Packages
PDIP16
P SUFFIX
PLASTIC PACKAGE
CASE 64808
ISSUE R
A
16
NOTES:
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
S
T
SEATING
PLANE
H
G
16 PL
0.25 (0.010)
T A
16
NOTES:
Y14.5M, 1982.
MOLD PROTRUSION.
PER SIDE.
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
B
1
8 PL
0.25 (0.010)
X 45 _
C
SEATING
PLANE
M
D
16 PL
0.25 (0.010)
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SOIC16
D SUFFIX
PLASTIC PACKAGE
CASE 751B05
ISSUE J
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
T B
http://onsemi.com
443
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16-Pin Packages
(continued)
SOEIAJ16
F SUFFIX
PLASTIC PACKAGE
CASE 96601
ISSUE O
16
NOTES:
Y14.5M, 1982.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
Q1
M_
E HE
1
DETAIL P
Z
D
e
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
VIEW P
A1
b
0.13 (0.005)
0.10 (0.004)
TSSOP16
DT SUFFIX
PLASTIC PACKAGE
CASE 948F01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
K1
2X
L/2
16
J1
B
U
SECTION NN
J
PIN 1
IDENT.
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
N
0.25 (0.010)
0.15 (0.006) T U
A
V
M
N
F
DETAIL E
C
0.10 (0.004)
T SEATING
PLANE
H
D
DETAIL E
http://onsemi.com
444
INCHES
MIN
MAX
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
0.031
NOTES:
Y14.5M, 1982.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE W.
MILLIMETERS
MIN
MAX
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
0.78
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
16-Pin Packages
(continued)
SOIC16
DW SUFFIX
PLASTIC PACKAGE
CASE 751G03
ISSUE B
D
9
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
h X 45 _
0.25
8X
16
16X
M
T A
DIM
A
A1
B
C
D
E
e
H
h
L
SEATING
PLANE
A1
14X
0.25
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
10.15
10.45
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
18-Pin Package
PDIP18
P SUFFIX
PLASTIC PACKAGE
CASE 70702
ISSUE C
18
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
10
B
1
A
L
N
F
H
D
G
SEATING
PLANE
K
M
http://onsemi.com
445
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
22.22
23.24
6.10
6.60
3.56
4.57
0.36
0.56
1.27
1.78
2.54 BSC
1.02
1.52
0.20
0.30
2.92
3.43
7.62 BSC
0_
15_
0.51
1.02
INCHES
MIN
MAX
0.875
0.915
0.240
0.260
0.140
0.180
0.014
0.022
0.050
0.070
0.100 BSC
0.040
0.060
0.008
0.012
0.115
0.135
0.300 BSC
0_
15 _
0.020
0.040
24-Pin Packages
PDIP24
P SUFFIX
PLASTIC PACKAGE
CASE 70902
ISSUE C
24
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
13
B
1
12
DIM
A
B
C
D
F
G
H
J
K
L
M
N
C
N
K
F
G
SEATING
PLANE
MILLIMETERS
MIN
MAX
31.37
32.13
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.03
0.20
0.38
2.92
3.43
15.24 BSC
0_
15_
0.51
1.02
INCHES
MIN
MAX
1.235
1.265
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.080
0.008
0.015
0.115
0.135
0.600 BSC
0_
15 _
0.020
0.040
SOIC24
DW SUFFIX
PLASTIC PACKAGE
CASE 751E04
ISSUE E
A
24
NOTES:
Y14.5M, 1982.
MOLD PROTRUSION.
PER SIDE.
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
13
12X
P
0.010 (0.25)
12
24X
0.010 (0.25)
T A
F
R
C
T
SEATING
PLANE
M
22X
http://onsemi.com
446
X 45 _
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0_
8_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0_
8_
0.395
0.415
0.010
0.029
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REFERENCE MANUAL
A Reference Manual is a publication that contains a comprehensive system or devicespecific description of the structure and function
(operation) of a particular part/system; used overwhelmingly to describe the functionality of a microprocessor, microcontroller, or some
other submicron sized device. Procedural information in a Reference Manual is limited to less than 40 percent (usually much less).
USERS GUIDE
A Users Guide contains procedural, taskoriented instructions for using or running a device or product. A Users Guide differs from
a Reference Manual in the following respects:
* Majority of information (> 60%) is procedural, not functional, in nature
* Volume of information is typically less than for Reference Manuals
* Usually written more in active voice, using secondperson singular (you) than is found in Reference Manuals
* May contain photographs and detailed line drawings rather than simple illustrations that are often found in Reference Manuals
POCKET GUIDE
A Pocket Guide is a pocketsized document that contains technical reference information. Types of information commonly found in
pocket guides include block diagrams, pinouts, alphabetized instruction set, alphabetized registers, alphabetized thirdparty vendors and
their products, etc.
ADDENDUM
A documentation Addendum is a supplemental publication that contains missing information or replaces preliminary information in the
primary publication it supports. Individual addendum items are published cumulatively. Addendums end with the next revision of the
primary document.
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An Application Note is a document that contains realworld application information about how a specific ON Semiconductor
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must already exist and be available.
A document called ApplicationSpecific Information is not the same as an Application Note.
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A Selector Guide is a trifold (or larger) document published on a regular basis (usually quarterly) by many, if not all, divisions, that
contains key lineitem, devicespecific information for particular product families. Some Selector Guides are published in book format
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A Product Preview is a summary document for a product/device under consideration or in the early stages of development. The Product
Preview exists only until an Advance Information document is published that replaces it. The Product Preview is often used as the first
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The Advance Information document is for a device that is NOT fully MCqualified. The Advance Information document is replaced
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herein are subject to change without notice.
TECHNICAL DATA
The Technical Data document is for a product/device that is in full production (i.e., fully released). It replaces the Advance Information
document and represents a part that is M, X, XC, or MC qualified. The Technical Data document is virtually the same document as the
Product Preview and the Advance Information document with the exception that it provides information that is unavailable for a product
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An Engineering Bulletin is a writeup that typically focuses on a single specific solution for a particular engineering or programming issue
involving one or several devices.
http://onsemi.com
448
DL131/D
Rev. 4, Mar-2000
ON Semiconductor
CMOS Logic Data
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further
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PUBLICATION ORDERING INFORMATION

For additional information, please contact your local

Chapter 1 Master Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 6 CMOS Logic Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Chapter 8 Equivalent Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Quad 2Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

CMOS Selection Guide by Function

Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Quad 2Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Quad 2Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Quad 2Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Dual 4Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

24Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

4Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Other Complex Functions

PhaseLocked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Reliability and Quality Handbook which contains data for

2.0 RAP TEST FLOW

3.0 TEST CONDITIONS AND COMMENTS

PTHB 15 psig/121C/100% RH at rated VCC or VEE

to be performed on plastic encapsulated devices

B AND UB SERIES FAMILY DATA

The CMOS Devices in this volume which have a B or UB

Output Drive Current

Exceptions to the B and UB Series Family

* Specifications coordinated by EIA/JEDEC SolidState Products Council.

MAXIMUM RATINGS* (Voltages Referenced to VSS)

0.5 to VDD + 0.5

Input or Output Voltage (DC or Transient)

Input or Output Current (DC or Transient), per Pin

Power Dissipation, per Package

Lead Temperature (8Second Soldering)

VIL = 1.5 V SECOND STAGE

Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications

Vin = VSS or VDD

VIN = VSS or VDD

VIN = VSS or VDD

All valid input

VIN = VSS or VDD

VIN = VSS or VDD

Table 2. ON Semiconductor Format for CMOS Industry B and UB Series Specifications

Input Capacitance (Vin = 0)

Gate Quiescent Current

FlipFlop and Buffer Quiescent Current

MSI Quiescent Current

LSI Quiescent Current

Input Voltage B Types

(VO = 0.5 or 4.5 Vdc)

Input Voltage UB Types