03 Inverter

CMOS I NVERTER
12/03/22 1 TUD/EE ET4293 - DigIC - 11/12 - NvdM - 03 Inverter

The CMOS I nver t er St at i c Model
Outline
First Glance
Digital Gate Characterization
Static Behavior (Robustness)
VTC
S it hi Th h ld Switching Threshold
Noise Margins
The CMOS I nver t er :
A Fi r st Gl anc e
V
DD
V
in
VV
out
C
L
CMOS I nver t er s (1)
V
DD
PMOS
In
Out
1.2 um
= 2
Polysilicon
Metal1
GND
NMOS
CMOS I nver t er Oper at i on Pr i nc i pl e
0 1
1
0
0
1
V
OH
= V
DD
V
OL
= 0
5.2
Di gi t al Gat e Fundament al
Par amet er s
Functionality
Reliability, Robustness y,
Area
Performance
Speed (delay) Speed (delay)
Power Consumption
Energy
The I deal I nver t er
V
out out
R
i
=
R
o
= 0
g = -
R
o
0
V
V
in
St at i c CMOS Pr oper t i es
Basic inverter belongs to class of static
circuits: output always connected to either
V or V Not ideal but: V
DD
or V
SS
. Not ideal but:
Rail to rail voltage swing
Ratio less design
Low output impedance
V
out
Extremely high input impedance
No static power dissipation
out
Good noise properties/margins
V
in
g = -
{TPS}: prioritize the list above
in
Voltage Transfer Characteristic (VTC)
5.2
Load Li ne (Ck t Theor y)
2.5
I
D
[10
-4
A]
2.5V
R
B
2.0
V
GS
= 2 0V
V
GS
= 2.5V
V
GS
R
A
1.0
1.5
V
GS
= 1.5V
V
GS
2.0V
0.5
V
GS
= 1.0V
V [V]
V
in
V
out
0V
Exercise:
0
0.5 1.0
1.5 2.0 2.5
V
DS
[V]
The blue load line A corresponds to R =
The orange load line B corresponds to R =
With load line A and V
GS
= 1V, V
out
=
12.5kO
25kO
approx 1.6 V
GS
,
out
Draw a graph V
out
(V
in
) for load line A and B
pp
PMOS Load Li nes
V
DD
-
V
GSp
-
Ki h ff
Goal: Combine I
Dn
and I
Dp
in one graph
V
-
+
V
GSp
+
-
V
DSp
I
Dp
Kirchoff:
V
in
= V
DD
+ V
GSp
I = - I
V
in
V
out
I
Dn
I
I
Dn
= - I
Dp
V
out
= V
DD
+ V
DSp
I I I
Dp
I
Dn
V =0
in
in
V =3
I
Dn
V
in
=0
V
in
=3
V
DSp
V
GSp
=-5
V
GSp
=-2
V
out
V = V + V
V
DSp
V
out
= V
DD
+ V
DSp
V
in
= V
DD
+ V
GSp
I
Dn
= - I
Dp
Example: V
DD
=5V
CMOS I nver t er Load Char ac t er i st i c s
I
n p n,p
V
in
= 5
V
in
= 0
NMOS
PMOS
V
in
= 4
V
in
= 1
V
in
= 3
in
V
in
= 2
V
in
= 2
V
in
= 3
V
in
= 1
in
in
V
in
= 4
V
in
= 4
V
in
= 5
V
in
= 2
V
in
= 3
V
in
= 0
V
in
= 1
V
out
CMOS I nver t er VTC
V
out
5
4
5
I
n,p
V
in
= 5
V
in
= 0
NMOS
PMOS
2
3
V
in
= 4
V
in
= 3
V
in
= 1
V
in
= 2
V
in
= 2
V
in
= 3
V
in
= 4
V
1
V
in
= 0
V
in
= 1
V
in
2
in
V
in
= 4
V
in
= 5
V
in
= 2 V
in
= 3
V
out
V
in
1 2 3 4 5
V
out
Oper at i ng
Condi t i ons
|
Need to know for proper dimensioning,
analysis of noise margin, etc.
V
out
= V
in
- V
Tp
| V
out
V
dd
NMOS
1 V
in
= V
GS
< V
Tn
off
V
out
= V
in
- V
Tn
2 V
out
> V
in
- V
Tn
V
DS
> V
GS
- V
Tn
V
dd
- |V
Tp
|
V
dd
V
in
V
Tn
- V
Tp
V
Tp
V
GD
< V
Tn
saturation
3 V
out
< V
in
- V
Tn
resistive
dd in Tn Tp
1 2 3
PMOS
4 V > V + V off
4
4 V
in
> V
DD
+ V
Tp
off
5
5 V
out
< V
in
- V
Tp
saturation
6
6 V V V i ti
Exercise: check
6 V
out
> V
in
- V
Tp
resistive
results for PMOS
Oper at i ng Condi t i ons
|
NMOS 1 off
V
out
= V
in
- V
Tp
| V
out
V
dd
NMOS 1 off
2 saturation
3 resistive
PMOS 4 off
V
out
= V
in
- V
Tn
PMOS 4 off
5 saturation
6 resistive
V
dd
- |V
Tp
|
V
dd
V
in
V
Tn
- V
Tp
V
Tp
V
out
5
NMOS off
PMOS lin
NMOS t
dd in Tn Tp
1 2 3
3
4
NMOS sat
PMOS t
NMOS sat
PMOS lin
4 5 6
1
2
NMOS lin
PMOS ff
PMOS sat
NMOS lin
PMOS sat
V
in
1 2 3 4 5
PMOS off
Inverter Static Behavior
R ti Regeneration
Noise margins
D l t i Delay metrics
5.3
The Real i st i c I nver t er
V
out
2.5
V
out
[V]
R
i
=
R
o
= 0
1.5
2.0
g = -
0.5
1.0
V
in
0
0.5
0.5 1.0
1.5 2.0 2.5
V
IN
[V]
V
in
Ideal Inverter
Realistic Inverter
The Regener at i ve Pr oper t y
A chain of inverters
Regenerative
Property: ability to
regenerate (repair) regenerate (repair)
a weak signal in a
chain of gates
Ex 1 4
The regenerative property
Ex. 1.4
The Regener at i ve Pr oper t y (2)
(a) A chain of inverters
v
0
v
1
v
2
v
3
v
4
v
5
v
6
...
(a) A chain of inverters.
v
1
, v
3
, ... v
1
, v
3
, ...
f(v)
finv(v)
finv(v)
f(v)
v
0
, v
2
, ... v
0
, v
2
, ...
(b) Regenerative gate (c) Non-regenerative gate
(b) Regenerative gate (c) Non regenerative gate
The r egener at i ve Pr oper t y (3)
Exercise: what is the output voltage of a chain of 4
i t ith i i li VTC i th h (0 inverters with a piece-wise linear VTC passing through (0,
10), (3,7), (7,1) and (10,0) [Volt], as the result of an input
voltage of 6 [Volt].
Exercise: discuss the behavior for an input of 5 [Volt]
I nver t er Sw i t c hi ng Tr eshol d
Not the device threshold
V
m
= f(R
onn
, R
onp
)
Point of V
in
= V
out
V
out
V
in
Try to set W
n
, L
n
, W
p
, L
p
so that VTC is symmetric so that VTC is symmetric
as this will improve noise
margins
optimize NMOS-PMOS ratio
Si mul at ed Gat e Sw i t c hi ng Thr eshol d
See Figure 5.7
Electrical Design Rule
W ~ 2.5 W W
p
~ 2.5 W
n
Assumes L
p
= L
n
Should be applied
V
M
(
V
)
Should be applied
consistently
V
S t i l VTC V V W /W
3 5
W
p
/ W
n
Symmetrical VTC V
m
~ V
DD
W
p
/W
n
~
In practice: somewhat smaller
3.5
Why? Save area with only slight asymmetry
I nver t er Sw i t c hi ng Thr eshol d
Anal yt i c al Der i vat i on
V
M
is V
in
such that V
in
= V
out
V
DS
= V
GS
V
GD
= 0 saturation
Assume V
DSAT
< V
M
- V
T
(velocity saturation)
Ignore channel length modulation
V
M
follows from
I
DSAT
(V
M
) = - I
DSAT
(V
M
) I
DSATn
(V
M
) I
DSATp
(V
M
)
5.3.1
I nver t er Sw i t c hi ng Thr eshol d
Anal yt i c al Der i vat i on (c t d) a yt c a e at o (c t d)
( ) 2 / V V V kV I
DSAT
T GS DSAT
D
=
I
DSATn
(V
M
) = - I
DSATp
(V
M
)
( ) = 2 / V V V V k
DSATn Tn M DSAT n
n
( ) 2 / V V V V V k
DSATp Tp DD M DSAT p
P

( )
( ) 2
2
/ V V V V V
/ V V V V
k
k
DSATp Tp DD M DSAT
DSATn Tn M DSAT
n
p
n

=
( )
DSATp Tp DD M DSAT p
P
k
L
W
k
'
=
( ) 2 / V V V V V k
DSATp Tp DD M DSAT n
P
( )
( ) 2
2
/ V V V V V
k
/ V V V V
k
) L / W (
) L / W (
DSAT T DD M DSAT
'
p
DSATn Tn M DSAT
'
n
p
n

=
( ) 2 / V V V V V
k
) L / W (
DSATp Tp DD M DSAT p n
P
See Example 5.1:
(W/L) = 3 5 (W/L) for typical conditions and V = V
(W/L)
p
= 3.5 (W/L)
n
for typical conditions and V
M
= V
DD
Usually: L
n
= L
p
Gat e Sw i t c hi ng Thr eshol d
w /o Vel oc i t y Sat ur at i on
Long channel approximation
Also applicable with low V
DD
4.0
Exercise (Problem 5.1):
derive V
M
for long-
3.0
V
M
derive V
M
for long-
channel approximation
as shown below
0 1 0 3 1 0 3 2 10 0
1.0
2.0
0.1 0.3 1.0 3.2 10.0
0
k
p
/k
n
n
p Tn Tp DD
k
k
r with
r
) V V V ( r
V
M
=
+
+
=
1
n
k r + 1
Noi se i n Di gi t al I nt egr at ed Ci r c ui t s
V
DD
v(t)
i(t) ( )
( ) P d d
(a) Inductive coupling (b) Capacitive coupling
(c) Power and ground
noise
Study behavior of static CMOS Gates with noisy
signals
Noi se i n Di gi t al Ci r c ui t s
0
+
-
VDD Drop
+
-
V
i
1
0
X
-
+
V
noise
-
Ground Bounce
1.3.2 5.3.2
Noi se Mar gi ns
V
V
OH
V
DD
V
OL
V
IL
V
IH
V
DD 0
1.3.2 5.3.2
V
OL
= Output Low Voltage
V
IL
= Input Low Voltage
IL
p g
V
OH
, V
IH
=
Noi se Mar gi ns
V
OL
= Output Low Voltage
V
IL
= Input Low Voltage
V
OH
, V
IH
=
Noi se Mar gi ns
NM
H
= V
OH
- V
IH
= High Noise Margin
NM V V L N i M i
NM
L
= V
IL
- V
OL
= Low Noise Margin
Noi se Mar gi n f or Real i st i c Gat es
V
OL
not well defined
Conveniently relate to slope s = -1
{TPS}: explain significance of slope = -1 for noise margin
Noi se Mar gi n Cal c ul at i on
Piece-wise linear
approximation of
VTC
g = gain factor
(slope of VTC)
VTC
(slope of VTC)
W k h We know how
to compute V
M
Next: how to
( )
g
V
g
V V
V V
DD OL OH
IL IH
=
Next: how to
compute g
g g
g
V
V V
M
M IH
=
g
V V
V V
M DD
M IL
+ =
IH DD H
V V NM =
IL L
V NM =
Noi se Mar gi n Cal c ul at i on (2)
Approximate g as the slope in V vs V at V = V
( )( ) + +
out n DSATn Tn in DSAT n
V / V V V V k
n
1 2
Approximate g as the slope in V
out
vs. V
in
at V
in
= V
M
( )( ) 0 1 2 = +
DD p out p DSATp Tp DD in DSAT p
V V / V V V V V k
P

( )( )
out
r dV
g
+
~ =
1
DSATp p
V k
r
( )( )
p n DSATp T M
V V
in
/ V V V dV
g
M in

=
2
Mostly determined by technology
DSATn n
p p
V k
r =
See example 5.2
Exercise: verify calculation
Exercise: explain why we add channel length
modulation to the I
D
expressions (we did not do
this to determine V
M
)
Gai n as a f unc t i on of VDD
( )( )
p n DSATp T M
V V
in
out
/ V V V
r
dV
dV
g
M in

+
~ =
=
2
1
consider
2
2.5
0.15
0.2
1
1.5
V
o
u
t
(
V
)
0.1
V
o
u
t
(
V
)
Gain=-1
0.5
1
0.05
0 0.5 1 1.5 2 2.5
0
V
in
(V)
0 0.05 0.1 0.15 0.2
0
V
in
(V)
Subthreshold!
12/03/22
Subthreshold!
34 TUD/EE ET4293 - DigIC - 11/12 - NvdM - 03 Inverter
Dynami c Noi se Mar gi n
Previous definition was Static Noise Margin
Dynamic Noise Margin: how does noise energy
d t i b h i determine behavior
A short pulse may have higher amplitude than a
long pulse before problems occur. long pulse before problems occur.
Short spikes may safely exceed Static Noise
Margin
A
m
p
l
i
t
u
d
e
Error free
i
s
e

P
u
l
s
e

A
Error free
N
o
i
Noise Pulse Duration
CMOS I NVERTER
dynami c behavi or (per f or manc e)
Capacitances
(Dis)charge times
y (p )
( ) g
Delay
5.4
Before: propagation delay analysis
L DD
DSAT
DD
p
C V
I
V
t
|
.
|
\
|
~
6
5
- 1
4
3
69 . 0
Th T i t S i t h
Next: propagation delay
from a design perspective
The Tr ansi st or as a Sw i t c h
V
GS

>
V
T
R
on
S
D
I
D
V
GS
= V
DD
from a design perspective
inverter sizing
V
DS
V
GS
V
DD
V
DD
/2 V
DD
R
0
R
mid
Ex. 3.8
5.4.1
12/03/05 39 TUD/EE ET4293 - Dig. IC - 1112 - NvdM - 01 Devices
V
DD
/2 V
DD
Reduc i ng t
p
L DD
DSAT
DD
pHL
C V
I
V
t
n
|
.
|
\
|
~
6
5
- 1
4
3
69 . 0
=0
( )

=
2
2
1
'
DSAT
DSAT T GS DSAT
V V V V
L
W
k I
) 2 / ( ) / (
52 . 0
'
DSATn Tn DD DSATn n n
DD L
pHL
V V V V k L W
V C
t

~
) ( ) (
{TPS}: How can you reduce propagation delay?
Propagation Delay t
p
can be reduced by
Increasing V
DD
(until V
DD
>> V
T
+ V
DSAT
/2)
Increasing W
g
Reducing C
L
Del ay as a f unc t i on of V
DD
5
5.5
4
4.5
5
z
e
d
)
) 2 / ( ) / (
52 . 0
'
DD L
pHL
V V V V k L W
V C
t ~
3
3.5
4
o
r
m
a
l
i
z
) 2 / ( ) / (
p
V V V V k L W
2
2.5
t
p
(
N
o
Spice
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
1
1.5
V (V)
Fg.5.17
V
DD
(V)
Si zi ng
Propagation Delay t
p
can be reduced by
Increasing V
DD
(until V
DD
>> V
T
+ V
DSAT
/2)
Increasing W
Reducing C
L
W
C
V V V V k L W
V C
t
L
DD L
pHL

=
) 2 / ( ) / (
52 . 0
'
C
L
can be reduced by good layout design
B t t f C d d W! But part of C
L
depends on W!
t
p
as a f unc t i on of W
p
/W
n
5
x 10
-11
t
I
pd
t
pHL
4
4.5
(
s
e
c
)
t
pHL
t
pLH W
n
C
D
t
pLH
3.5
4
t
p
(t
pHL
+ t
pLH
)/2
W
3
1 1.5 2 2.5 3 3.5 4 4.5 5
W
p
W
p
/W
n
Min t
p
in general not when t
pLH
= t
pHL
p p p
Save area, time at expense of robustness
TUD/EE ET4293 - DigIC - 11/12 - NvdM - 03 Inverter 07 inductance 42
I nt r i nsi c vs Ex t r i nsi c vs Par asi t i c Load Cap
C
GS4
V
DD
V
DD
M
2
M
4
C
DB2
V
out
V
in V
o t2
2
M
4
C
GS3
C
DB1
C
GD1
+ C
GD2
C
in V
out2
M
M
3
C
GD1
C
GD2
C
W
M
1
C
int
= C
DB1
+ C
DB2
+ 2(C
GD1
+ C
GD2
)
C
ext
= C
GS3
+ C
GS4
+ C
GD3
+ C
GD4
C = C
Intrinsic load
Extrinsic / fan-out load
Parasitic load
C
par
= C
w
Parasitic load
I sol at ed I nver t er Si zi ng
Assume C can be
|
|
.
|
\
|
+ = + =
int
ext
int eq ext int eq p
C
C
C R C C R t 1 69 . 0 ) ( 69 . 0
Assume C
par
can be
ignored or its effect can
be absorbed in other C
R
0
: resistance of minimum size inverter
0
(assume proper | = W
p
/ W
n
ratio)
C
0
: intrinsic load (output, drain) cap of min. size inverter
t
p0
= 0.69 R
0
C
0
: t
p0
0.69 R
0
C
0
:
intrinsic or unloaded delay
basic time constant for technology
minimum delay possible in technology given V minimum delay possible in technology given V
DD
S: sizing factor for W
n
, W
p
of driving inverter
W
n
= S W
min
, W
p
= S | W
min
R
eq
= R
0
/S C
int
= SC
0
|
|
| C
ext
|
|
.
|
\
|
+ =
0
0
1
SC
C
t t
ext
p p
I sol at ed I nver t er Si zi ng
|
|
.
|
\
|
+ =
0
0
1
SC
C
t t
ext
p p
Increasing S reduces delay until SC
0
>> C
ext
t
t
p
S
t
p0
C
ext
I nver t er Chai n
Assume size of inverter 1 is fixed.
Increasing S of inverter 2 reduces t
p
of inverter 2
But it increases t of inverter 1 (higher load cap)
In
Out
But it increases t
p
of inverter 1 (higher load cap)
Expect an optimum!
1 2
C
L
1 2
{TPS} If C
L
is given and knowing properties of input source:
L
- How many stages are needed to minimize the delay?
- How to size the inverters?
Del ay For mul a
|
.
|
\
|
+ =
|
|
.
|
\
|
+ =
f
t
SC
C
t t
p
ext
p p
1 1
0
0
0
C
gin
input gate capacitance
. \
. \

0
= C
int
/C
gin
= SC
0
/C
gin
self loading coefficient
property of technology typically ~ 1 property of technology, typically ~ 1
f = C
ext
/C
gin
effective fanout
C
C f gin
ext
0
SC
x
C
g
gin
ext
=

Appl y t o I nver t er Chai n
I O t
C
In Out
1
2 N
C
L
t
p
= t
p,1
+ t
p,2
+ + t
p,N
|
|
.
|
\
|
+ =
|
|
.
|
\
|
+ =
+
j gin
j gin
p
j
p j p
C
C
t
f
t t
,
1 ,
0 0 ,
1 1

L N gin
N
j
j gin
j gin
p
N
j
j p p
C C
C
C
t t t =
|
|
.
|
\
|
+ = =
+
=
+
=

1 ,
1
,
1 ,
0
1
,
, 1

j
j g
j
. \
1
,
1
[ t
p
= t
p0
(1+f/) f = C
ext
/C
gin
effective fanout ]
Appl y t o I nver t er Chai n
L N i
N
j gin
N
j
C C
C
t t t =
|
|
|
|
+ = =
+

1
1 ,
0
1
Delay equation has N-1 unknows, C
gin,2
C
gin,N
L N gin
j
j gin
p
j
j p p
C C
C
t t t =
|
|
.
\
+ = =
+
= =

1 ,
1
,
0
1
,
, 1
Make N-1 partial derivatives for C

gin j
zero for minimization:
( )
1 2 , 0
1
2
1 ,
1
0
= =
|
|
.
|
\
|
=
c
c
+
N j
C
C
C
t
C
t
j i
j gin
j gin
p
j gin
p
Make N 1 partial derivatives for C

gin,j
zero for minimization:
( )
,
1 , ,
|
.
\
c
C
C C
j gin
j gin j gin
b a c
c
b
a
= =
2
1
Size of each stage is geometric mean of 2 neighbors:
1 2 N j C C C
1 2 ,
1 , 1 , ,
= =
+
N j C C C
j gin j gin j gin

Opt i mal Taper i ng f or Gi ven N
1 2 ,
1 , 1 , ,
= =
+
N j C C C
j gin j gin j gin

Size of each stage is geometric mean of 2 neighbors:
, , , j g j g j g
1 , 1 ,
2
,
+
=
j gin j gin
j gin
C C C
j gin
j gin
j gin
j gin
C
C
C
C
,
1 ,
1 ,
, +
=
Load cap / input cap ratio
same for each stage
F = C
L
/C
gin,1
: path fan-out.
Same fan-out, same delay for
j gin j gin , 1 ,
N
N
L
j gin
j
F
C
C
C
C
f = = =
+1 ,
, y
each stage.
gin j gin
j
C C
1 , ,
|
|
|
|
|
|
|
|
|
+
N
j gin j F
t
C
t
f
t t 1 1 1
1 ,
|
|
.
\
+ =
|
|
.
\
+ =
|
|
.
\
+ =

p
j gin
j g
p
j
p j p
t
C
t t t 1 1 1
0
,
,
0 0 ,
Opt i mal Taper i ng f or Fi x ed-N
Summar y
In
Out
C
L
C = C
1 f f
2
C
1
= C
gin,1
|
|
|
|
+ =
|
|
|
|
+ =
|
|
.
|
\
|
+ =
+
N
p
j gin
p
j
p j p
F
t
C
C
t
f
t t 1 1 1
0
1 ,
0 0
Delay per stage and total Path Delay
|
|
|
|
+ =
j
p p
f
Nt t 1
0
|
.
\
|
.
\
|
.
\

p
j gin
p p j p
C
0
,
0 0 ,
|
.
\

p p 0
f
1
= f
2
= f
3
= ... = F
1/N
f
1
x f
2
x f
3
x = F F = C
L
/C
gin 1
f
1
f
2
f
3
... F f
1
x f
2
x f
3
x F F C
L
/C
gin,1
Ex ampl e
C = 8 C
In
Out
1 f f
2
C
L
= 8 C
1
C
1
= C
gin,1
1 f f
2
C
L
/C
1
has to be evenly distributed across N = 3 stages:
2 8
3
= = f 1 9
8
1 3
0
3
0
= =
|
|
.
|
\
|
+ =
for t t t
p p p
Opt i mum Number of St ages
For a given load, C
L
and given input capacitance C
in
find optimal f if N is free (and possibly non-integer)
f
F
N C f C F C
in
N
in L
ln
ln
with = = =
|
.
|
\
|
+ = |
.
|
\
|
+ =
f
f
f
F t
f
Nt t
p
p p
ln ln
ln
1
0
0

0
ln
1 ln
ln
2
0
=
+
=
c
c
f
f f
F t
f
t
p p
| |

Closed form solution
f
f

+ = 1 ln
|
.
|
\
|
+ =
f
f

1 exp
Closed-form solution
only for = 0
Opt i mum Ef f ec t i ve Fanout f
Optimum f for given process defined by
f
F
N
ln
ln
= |
.
|
\
|
+ =
f
f

1 exp
(In practice N must be rounded (In practice, N must be rounded
up or down to integer value)
=0 =1
f
opt
e=2.72 3.6
N
opt
lnF 0.78lnF
Nor mal i zed t
p
vs. f
With Self-Loading =1,
Slight increase of t
p
for
f > f
opt
g
f
opt
= 3.6
Choosing too few
stages (f > f
opt
) is
relatively harmless for
delay and saves area delay and saves area
Too many stages is
expensive in terms of
delay delay
Fan-out of 4 (FO4) is safe common practice
Fan-out of 4 (FO4) is safe common practice
http://en.wikipedia.org/wiki/FO4
Nor mal i zed del ay f unc t i on of F
|
|
.
|
\
|
+ =
N
p p
F
Nt t 1
0
( = 1)
F Unbuffered Two Stage
Inverter
Ch i
. \

F Unbuffered Two Stage
Chain
10 11 8.3 8.3
100 101 22 16.5
1000 1001 65 24.8
10,000 10,001 202 33.1
Buf f er Desi gn
N f t
p
( = 1)
1
64
1 64 65
1 8
64
2 8 18
1
64
4
16
3 4 15
1
64
2.8
8
22.6
4 2.8 15.3
Pow er
Dynamic Power
Static Power
Metrics
www.quietpc.com
5.5
24 hours audio
playback time
p y
CMOS Pow er Di ssi pat i on
Power dissipation is a very important circuit
characteristic
CMOS has relatively low static dissipation CMOS has relatively low static dissipation
Power dissipation was the reason that CMOS
technology won over bipolar and NMOS
technology for digital ICs technology for digital ICs
(Extremely) high clock frequencies increase
dynamic dissipation
Low V
T
increases leakage
Advanced IC design is a continuous struggle to
contain the power requirements! contain the power requirements!
1.3.4 5.5
Pow er Densi t y
Estimate
Furnace: 2000 Watt, r=10cm P ~ 6Watt/cm
2
,
Processor chip: 100 Watt, 3cm
2
P ~ 33Watt/cm
2
Power-aware design, design for low power, is
g , g p ,
blossoming subfield of VLSI Design
{TPS}: what is the difference in power between Bipolar and
CMOS technologies?
A: 10 years
Pow er Evol ut i on over Tec hnol ogy Gener at i ons
ASME 2004
12
14
Bipolar
CMOS IBM ES9000
Prescott
Jayhawk(dual)
w
a
t
t
s
/
c
m
2
)
8
10
Fujitsu VP2000
IBM 3090S
IBM GP
T-Rex
Squadrons
Mckinley

H
e
a
t

F
l
u
x
(
w
4
6
IBM 3090S
NTT
Fujitsu M-780
IBM 3090
IBM RY5
Pulsar
IBM RY7
Pentium 4
M
o
d
u
l
e
2
4
Vacuum
IBM 360
IBM 370
IBM 3033
IBM 3090
CDC Cyber 205
IBM 4381
IBM 3081
Fujitsu M380
IBM RY6
Apache
Merced
IBM RY4
P ti II(DSIP)
Start of
Water Cooling
Introduction of CMOS over bipolar bought industry 10 years
Year of Announcement
1950 1960 1970 1980 1990 2000 2010
0
Pentium II(DSIP)
Introduction of CMOS over bipolar bought industry 10 years
(example: IBM mainframe processors)
[From: Jan Rabaey, Low Power Design Essential, Ref: R. Chu, JEP04]
Low Pow er Desi gn Essent i al s
Recommended reading
(available online via University Library and site of book)
Wher e Does Pow er Go i n CMOS
Dynamic Power Consumption
Charging and discharging capacitors Charging and discharging capacitors
Short Circuit Currents
Short circuit path between supply rails during Short circuit path between supply rails during
switching (NMOS and PMOS on together)
Leakage
Leaking diodes and transistors
May be important for battery-operated equipment
Dynami c Pow er
Dynamic Power
E
i
= energy of switching event i
independent of switching speed independent of switching speed
depends on process, layout
Power = Energy/Time Power Energy/Time
=
i
i
E
T
P
1
E
i
= Power-Delay-Product P-D
important quality measure
Energy-Delay-Product E-D
combines powerspeed performance
p p p
Low -t o-Hi gh Tr ansi t i on Ener gy
v
DD DD
i(t)
Equivalent circuit for low-
to-high transition
C
v
0
(t)
C
E
C
- Energy stored on C E
C
Energy stored on C
=

0
0
dt iv E
C
) ( =
0 0
t v v
dt
dv
C t i i
0
) ( = =
=

0
0
0
dt
dt
dv
Cv
DD
V DD
V
1 1
=
DD
V
dv Cv
0
0 0
DD
V
Cv
0
2
0
2
1
=
2
2
1
DD
CV =
v
DD
i(t)
C
v
0
(t)
DD
DD
V
E Energy delivered by supply
DD
V
gy y pp y
( ) dt V t i E
DD V
DD

=
0
=
DD
V
DD
dt
dt
dv
CV
0
0
2
DD
CV =
0 0
2 2
2
1
DD
c
DD
V
CV E CV E
DD
= =
Wh i th t?
Where is the rest?
Dissipated in transistor
v
DD
i(t)
C
v
0
(t)
diss
E
Energy dissipated in transistor
diss
E
Energy dissipated in transistor
( )dt v V i E
DD diss

=
0
0
0

=
0 0
0
dt iv dt iV
DD
c V
E E
DD
=
Hi gh-t o-Low Tr ansi t i on Ener gy
E i l t i it Equivalent circuit
C
i
Exercise: Show that the energy that is dissipated
in the transistor upon discharging C from V
DD
to
0 equals E
di
= CV
DD
2
0 equals E
diss
CV
DD
Compar e Char gi ng St r at egi es
dV CV
C
dV
i C
dT
=
CV
I
T
= Constant voltage
Constant current
+
-
V
C
R
I
C
R
( ) ( )
2
0 0
T
R
E I RI dt I RI dt RI T
= = =
( )
0 0
C
R R C
dV
E V idt V V C dt
dt

= =

0 0
0 0
dt
( )
2
0
1
2
V
c C
V V CdV CV = =
2
RC
CV
T
=
Reduced dissipation if T > 2RC = t
76%
Difficult to reap benefits in practice
See Adiabatic Logic
CMOS Dynami c Pow er Di ssi pat i on
ti
s transition #
t iti
Energy
Ti
Energy
Power = =
time transition Time
f CV
DD
=
2
Independent of transistor on-resistances
Can only reduce C, V
DD
or f to reduce power
Shor t Ci r c ui t Cur r ent
Shaded area is where both pull-up
and pull-down transistors are on
(this is when short-circuit current
i t) Thi i i d t i d can exist). This region is determined
by crossings of input waveform with
V
Tn
and V
DD
-|V
Tp
|.
C
Load
|V
Tp
|
Short circuit current for output
going low is the current delivered by
the PMOS
V
input
waveform
(NMOS current is used for
discharging)
{TPS} Discuss the influence of C V
Tn
NMOS PMOS
{TPS} Discuss the influence of C
Load
on the amount of short circuit
dissipation
higher C
O
higher dissipation?
turns on turns off
higher C
LOAD
higher dissipation?
or not?
|V
DSp
|
Input and output waveforms of
inverter loaded with a large
capacitance (top) and with a small
capacitance (bottom)
input
|V
Tp
|
capacitance (bottom).
Short-circuit current increases with
|V
DSp
|. This is clearly much larger
waveform
V
Tn
output for
large CL
p
on average for small C
L
compared
to large C
L
.
Similarly, short-circuit current can
|V |
y,
exist for low-to-high transition at
output.
|V
Tp
|
|V
DSp
|
V
Tn
output for
small C
L
NMOS
turns on
PMOS
turns off
Pull-up turns off
before V
DSp
becomes
i ifi t significant
Best to maintain approximately equal input/output slopes
Leak age
Leakage current of reverse biased S/D junctions
Sub-threshold current of MOS devices
no channel parasitic bipolar device:
n+ (source) p (bulk) n+ (drain)
Important source of leakage
10
-2
Important source of leakage
10
-6
10
-4
Linear
Quadratic
)
10
-8
10
6
Exponential
Quadratic
I
D
(
A
)
3.3
( )
DS
kT
qV
nkT
qV
D
V e e I I
DS GS
+
|
|
|
|
|
=

1 1
0
10
-12
0 0.5 1 1.5 2 2.5
10
-10
V
T
Exponential
( )
DS D
|
|
.
\
0
V
GS
(V)
Sub-Thr eshol d
Cur r ent
Rapidly becomes y
bottleneck with lowering
threshold voltages
Modern technologies offer
low-Vt and hi-Vt devices
Balance speed and power
Y. Taur, CMOS design near the limit
of scaling IBMJRD Volume 46
of scaling, IBMJRD, Volume 46,
Numbers 2/3, 2002
Sub-Thr eshol d Cur r ent
Rapidly becomes bottleneck with lowering threshold
voltages
Modern technologies offer low-V
t
and hi-V
t
devices
Balance speed and power
10
-4
10
-2
Linear
10
-4
10
-2
Linear
10
-8
10
-6
10
-4
Quadratic
I
D
(
A
)
10
-8
10
-6
10
-4
Quadratic
I
D
(
A
)
10
-12
0 0.5 1 1.5 2 2.5
10
-10
V
T
Exponential
10
-12
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
10
-10
V
T
Exponential
V
GS
(V) V
GS
(V)
Tr ansi st or Si zi ng f or Mi ni mum Ener gy
In
Out
C
L
= FC
G1
C
G1
1 f
Goal: Minimize Energy of whole circuit
Design parameters: f and V
DD
52 . 0
'
DD L
pHL
V C
t ~
DD
t
p
s t
pref
of circuit with f = 1 and V
DD
= V
ref
F f | | | | | |
) 2 / ( ) / (
pHL
V V V V k L W
DD
p
p p
V
t
f
F f
t t
|
|
.
|
\
|
|
.
|
\
|
+ + |
.
|
\
|
+ =
0
0
1 1

See Eq. 5.21
Ex.
5.13
TE DD
p
V V
t
0
See Eq. 5.21
V
TE
= V
T
V
DSAT
: Effective V
T
Tr ansi st or Si zi ng f or Mi ni mum Ener gy
In
Out
C
L
= FC
G1
C
G1
1 f
Goal: Minimize Energy of whole circuit
DD
52 . 0
'
DD L
pHL
V C
t ~ Design parameters: f and V
DD
t
p
s t
pref
of circuit with f = 1 and V
DD
= V
ref
F f | | | | | |
) 2 / ( ) / (
52 . 0
'
pHL
V V V V k L W
t

DD
p
p p
V
t
f
F f
t t
|
|
.
|
\
|
|
.
|
\
|
+ + |
.
|
\
|
+ =
0
0
1 1

See Eq. 5.21
Ex.
5.13
TE DD
p
V V
t
0
See Eq. 5.21
V
TE
= V
T
V
DSAT
: Effective V
T
Tr ansi st or Si zi ng (2)
TE DD
DD
p p p
V V
V
t
f
F f
t t
|
|
.
|
\
|
|
.
|
\
|
+ + |
.
|
\
|
+ =
0 0
1 1

2 2
|
.
|
\
|
+ +
| | | |
|
.
|
\
|
+ +
F
f
V V V
F
f
t t
Performance Constraint (with = 1, t
pref
f=1):
V t h l (0 5 V) V t d d l (2 5 V)
( ) ( )
1
3 3
0
0
=
+
|
.
\
|
|
.
|
\
|
|
|
.
|
\
|
=
+
|
.
\
=
F
f
V V
V V
V
V
F
f
t
t
t
t
TE DD
TE ref
ref
DD
ref p
p
pref
p
V
TE
: technology (0.5 V), V
ref
: standard supply (2.5 V)
F: fanout
V
DD
, f: design parameters
V
DD
is a function of f, given a fixed performance
( )
( )
F f
V
DD
5 15
2
+
=
( ) fF F f f
V
DD
10 8 8 14
2
+
V f(f) V
DD
=f(f)
3 5
4
F=1
2
2.5
3
3.5
V
)
Supply voltage needed
as a function of f to
maintain reference
f
5
10
1.5
2
v
d
d

(
V
performance
Lowest supply voltage
needed for f = F
0.5
10
20
0
0.5
1
( )
( ) fF F f f
F f
V
DD
10 8 8 14
5 15
2
+
+
=
1 2 3 4 5 6 7
f
0
Energy for single Transition:
C
g1
+ C
int
Size of 1
st
+
2
nd
inverter
( )( ) | |
| |
| |
+ + + =
f V
F f C V E
g
DD
1 1
2
1
2
Energy for single Transition:

C
L
= FC
G1
|
.
|
\
|
+
+ +
|
|
.
|
\
|
=
F
F f
V
V
E
E
ref
DD
ref
4
2 2
2
( )
( )
F f
V
DD
5 15
2
+
=
( ) fF F f f
DD
10 8 8 14
2
+
E/E =f(f) E/E
ref
=f(f)
1.5
1
e
d

e
n
e
r
g
y
|
.
|
\
|
+
+ +
|
|
.
|
\
|
=
F
F f
V
V
E
E
ref
DD
ref
4
2 2
2
|
.
|
\
|
+
+ +
|
|
.
|
\
|
=
F
F f
V
V
E
E
ref
DD
ref
4
2 2
2
0.5
n
o
r
m
a
l
i
z
e
1 2 3 4 5 6 7
0
n
1 2 3 4 5 6 7
f
Device sizing is effective
Oversizing is expensive for power
Oversizing is expensive for power
Optimal sizing for energy slightly different from sizing for performance
Tec hnol ogy Sc al i ng Tec hnol ogy Sc al i ng
Also see: IBM JRD, Vol 46, no 2/3, 2002
Scaling CMOS to the limit
http://www.research.ibm.com/journal/rd46-23.html
5.6
Moor es Law
4004 4004
The number of transistors
th t b i t t d that can be integrated on a
single chip will double
every 18 months
Gordon Moore, co-founder of Intel
[Electronics, Vol 38, No. 8, 1965]
Why Sc al i ng
Reduce price per function:
Want to sell more functions (transistors) per Want to sell more functions (transistors) per
chip for the same money better products
Build same products cheaper, sell the same p p
part for less money larger market
Price of a transistor has to be reduced
B t l t t b f t ll l But also want to be faster, smaller, lower power
Sc al i ng Model s
Fixed Voltage Scaling
most common model until 1990s
only dimensions scale, voltages remain constant
Full Scaling (Constant Electrical Field) Full Scaling (Constant Electrical Field)
ideal model dimensions and voltage scale together by
the same factor S
General Scaling
most realistic for todays situation
voltages and dimensions scale with different factors
Sc al i ng f or Vel oc i t y Sat ur at ed Devi c es
Constant Field Scaling: S = U
Parameter Relation General Scaling
W, L, t
ox
1/S
Constant Field Scaling: S U
V
DD
, V
T
1/U
N
SUB
V / W
depl
2
S
2
/U
Area / Device WL 1/S
2
Area / Device WL 1/S
C
ox
1/t
ox
S
C
gate
C
ox
W L 1/S
k k C W / L S k
n
, k
p
C
ox
W / L S
I
sat
C
ox
W V 1/U
Current Density I
sat
/ Area S
2
/U
R
on
V / I
sat
1
Intrinsic Delay R
on
C
gate
1/S
Power / Device I
t
V 1/U
2
Power / Device I
sat
V 1/U
Power Density P / Area S
2
/U
2
I C Tec hnol ogy Sc al i ng
Scaling improves density and performance
First order scaling theory
dimensions, 1/S
voltages 1/S
2008 / 1971
0.007
0.007
intrinsic delay 1/S
power per transistor 1/S
2
0.007
0.00004
Scaling trend
2008
S~150
2010
S~200
1982
S~5
1971
S=1 (10um)
S~150 S~200 S~5 S=1
first uproc
(65nm)
(10um)
Tec hnol ogy Pr ac t i c e & I TRS
Scaling Technology Generations
S ~ 1.4 ~ 2
0.5
per generation
250 180 130 90 65 45 35 22 nm 250 180 130 90 65 45 35 22 nm
ITRS: International Technology Roadmap for Semiconductors
Industry wide organization for forecasting technology Industry-wide organization for forecasting technology
developments and (planning) requirements
http://www.itrs.net/home.html http://www.itrs.net/home.html
Not really it is more like science
Not really it is more like science
(and a self-fulfilling prophecy at the same time)
Summar y
Digital Gate Characterization ( 1.3)
Static Behavior (Robustness) ( 5 3) Static Behavior (Robustness) ( 5.3)
VTC
Switching Threshold
N i M i Noise Margins
Dynamic Behavior (Performance) ( 5.4)
Capacitances
Delay
Power ( 5.5)
Dynamic Power, Static Power, Metrics Dynamic Power, Static Power, Metrics
Scaling ( 5.6)

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12/03/22 1 TUD/EE ET4293 - DigIC - 11/12 - NvdM - 03 Inverter

12/03/22 47 TUD/EE ET4293 - DigIC - 11/12 - NvdM - 03 Inverter

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Make N-1 partial derivatives for C

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