THE P-CHANNEL MOSFET A p-channel enhancement-type MOSFET (PMOS transistor), fabricated on an n-type substrate with p+ regions for the

drain and source. The device operates in the same manner as the n- channel enhancement MOSFET except that vGS and vDS are negative and the threshold voltage Vt is negative. Also, the current iD enters the source terminal and leaves through the drain terminal. PMOS technology originally dominated MOS manufacturing. However, because NMOS devices can be made smaller and thus operate faster, and because NMOS historically required lower supply voltages than PMOS, NMOS technology has virtually replaced PMOS. COMPLEMENTARY MOS OR CMOS

Figure 1.7 Cross-Section of a CMOS IC.

As the name implies, complementary MOS technology employs MOS transistors of both polarities. Indeed, at the present time CMOS is the most widely used of all the IC technologies. Figure 1.7 shows a cross-section of a CMOS chip illustrating how the PMOS and NMOS transistors are fabricated. Observe that while the NMOS transistor is implemented directly in the p-type substrate. The PMOS transistor is fabricated in a specially created n region, known as an n well. The two devices are isolated from each other by a thick region of oxide that functions as an insulator.

OPERATING THE MOS TRANSISTOR IN THE SUBTHRESHOLD REGION

The n-channel MOSFET operation implies that for vGS < Vt, no current flows and the device is cut off. This is not entirely true, for it has been found that for values of vGS smaller than but close to Vt, a small drain current flows. In this subthreshold region of operation the drain current is exponentially related to vGS. Although in most applications the MOS transistor is operated with vGS > Vt, there are special, but a growing number of, applications that make use of subthreshold operation.

CURRENT-VOLTAGE CHARECTERISTICS Circuit Symbol

Figure 1.8 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Simplified circuit symbol to be used when the source is connected to the body.

The iD-vDS Characteristics

Figure 1.9 (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow indicated. (b) The iDvDS characteristics.

Figure 1.9 (a) shows an n-channel enhancement-type MOSFET with voltages vGS and vDS applied and with the normal directions of current flow indicated. This conceptual circuit can be used to measure the iD-vDS characteristics, which are a family of curves, each measured at a constant vGS. The characteristic curves in Fig. 4.11(b) indicate that there are three distinct regions of operation, the cutoff region, the triode region, and the saturation region. The device is cut off when vGS < Vt. To operate the MOSFET in the triode region , a channel must be induced, vGS Vt, and then keep vDS small enough so that the channel remains continuous. This condition can be stated explicitly in terms of vDS by writing vDS<vGS - Vt. In the triode region, the iD-vDS characteristics can be described by the relationship of

If vDS is sufficiently small so that we can neglect the v2DS.

This linear relationship represents the operation of the MOS transistor as a linear resistance rDS whose value is controlled by vGS.

To operate the MOSFET in the saturation region, a cannel must be induced, vGS Vt, and pinched off at the drain end by raising vDS to a value that results in the

gate-to-drain voltage falling below Vt. This condition can be stated explicitly in terms of vDS by writing vDSvGS - Vt. In the saturation region, the iD-vDS characteristics can be described by the relationship of

Thus in saturation the MOSFET provides a drain current whose value is independent of the drain voltage vDS and is determined by the gate voltage vGS. Since the drain current is independent of the drain voltage, the saturated MOSFET behaves as an ideal current source whose value is controlled by vGS.

Figure 1.10 Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region.

Figure 1.10 shows a circuit representation of MOSFET operation in the saturation region. Note that this is a large-signal equivalent-circuit model.

FINITE OUTPUT RESISTANCE IN SATURATION That in saturation, iD is independent of vDS. Thus a change in the drain-to-source voltage vDS causes a zero change in iD, which implies that the incremental resistance looking into the drain o f a saturated MOSFET is infinite. That once the channel is pinched off at the drain end, further increases in v DS have no effect on the channel's shape. But, in practice, as vDS is increased, the channel pinch-off point is slightly moved. Specifically, away from the drain, toward the source.

Figure 1.11 Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length.

This is illustrated in Fig. 1.11, from which we note that the voltage across the channel remains constant at vGS -Vt= vDSsat, and the additional voltage applied to the drain appears as a voltage drop across the narrow depletion region between the end of the channel and the drain region. This voltage accelerates the electrons that reach the drain end of the channel and sweeps them across the depletion region into the drain. Note that the channel length is reduced, from L to L-L. This phenomenon is known as channel-length modulation. Since iD is inversely proportional to the channel length, iD increases with vDS. We replace L with L-L.

Assume that L/L << 1, and L/L = vDS

The linear dependence of iD on vDS in the saturation region by the factor (1 + vDS) is shown in fig 1.12.

Figure 1.12 Effect of vDS on iD in the saturation region by the factor (1 + vDS).

In the saturation region the output resistance ro is

Where

Figure 1.13 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro.

Characteristics of the p-Channel MOSFET The circuit symbol for the p-channel enhancement-type MOSFET is shown in Fig.1.14 (a), in which an arrowhead pointing in the normal direction of current flow is included on the source terminal. The voltage and current polarities for normal operation are indicated in Fig. 1.14 (b). For t h e p-channel device the threshold voltage Vt is negative. To induce a channel we apply a gate voltage that is more negative than Vt, i.e. vGS Vt. When a drain voltage vDS is more negative than the source voltage, the current iD flows out of the drain terminal, as indicated in the figure. To operate in the triode region vDS must satisfy vDS vGS - Vt. The current iD is given by

Figure 1.14 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) The MOSFET with voltages applied and the directions of current flow indicated.

To operate in the saturation region vDS must satisfy vDS vGS - Vt. The current iD is given by

The Role of the Substrate-The Body Effect In many applications the source terminal is connected to the substrate (body) terminal B, which results in the pn junction between the substrate and the induced channel having a constant zero bias. In such a case the substrate does not play any role in circuit operation. In integrated circuits, the substrate is usually common to many MOS transistors. In order to maintain the cutoff condition for all the substrate-tochannel junctions, the substrate is usually connected to the most negative power supply in an NMOS circuit and the most positive in a PMOS circuit. The resulting reverse-bias voltage between source and body will have an effect on device operation. Let us consider an NMOS transistor and its substrate be made negative relative to the source. The reverse bias voltage will widen the depletion region. This in turn reduces the channel depth. To return the channel to its former state, vGS has to be increased. The effect of VSB on the channel can be most conveniently represented as a change in the threshold voltage Vt. Specifically, it has been shown that increasing the reverse substrate bias voltage VSB results in an increase in Vt, according to the relationship

Where Vto is threshold for VSB = 0; f is a physical parameter with (2 f) typically 0.6 V; i s a fabrication-process parameter given by

Where q is the electron charge (1.6 x 1 0 -19C), NA is the doping concentration of the p-type substrate, and s is the permittivity of silicon (11.7 o = 11.7 x 8.854 x 10-1 4 = 1.04 x 1 0-12 F/cm). The above equation indicates that an incremental change in VSB gives rise to an incremental change in Vt which in turn results in an incremental change in iD even though vGS might have been kept constant. It follows that the body voltage controls iD; thus the body acts as another gate for the MOSFET, a phenomenon known as the body effect.