A

ON

TRAINING AT THAPAR UNIVERSITY PATIALA

SUBMITTED TO: ER. AJAY PAL SINGH

SUBMITTED BY: SUMIT NARULA GEC 114404

ACKNOWLEDGEMENT
There is always a sense of gratitude, which is expressed to others for the helpful and needy service towards all this, which have been helpful to me in getting this task of project successfully accomplished. First of all I would express my sincere gratitude to Electronics and communication Department SLIET who helped me in some or other ways. I would like to express my sincere gratitude to Er. Ajaypal Singh, who rendered me busy possible help and patiently listening my problems. Furthermore, I would like to express my gratitude and thanks to my course counselor Dr.Anupama Marwaha who helped me in some or other way.

SUMIT NARULA GEC/114404

PREFACE
The ever-increasing use of micro controller system in device other than general purpose computing systems such as industrial control & common house hold devices created vacuum in terms of miniaturization required. The microprocessor - based system simply occupied too much space to be seriously considered for any further applications. The solution lay in a concept called micro controller where in the microcomputer with just enough computing power desired was present on a single chip. The project micro controller based temp. Indicator & printing system also uses a micro controller that makes it versatile device. The project repot is divided in to several sections to understand it clearly. Introduction part gives the idea about the project in brief. The block diagram & the circuit diagram represents the necessary operation required completing this project. The circuit is divide in to five section to understand it clearly that is A to D converter, micro controller chip, sensing part , power supply, display section. The PCB section includes the position of components that helps a lot during the assembling of the project. After that the working of project is explained in detail. The program necessary to provide the commands to the printer is explained in the software section. An estimation of the total cost is given in the cost analysis. The data sheets are explained in the architecture & functioning of the various ICs used. Finally reference section includes the various books & websites that helps in during the project.

INDEX
i) ACKNOWLEDGEMENT ii) PREFACE

1. ABOUT THAPAR UNIVERSITY 2. MICROCONTROLLER

A) B) C) D) E) F) INTRODUCTION TO 8051... PIN CONFIGURATION.. 8051 ARCHITECHTURE.................................... 8051 INSTRUCTION SET..................................................................................... ABOUT KEIL VISION3 SIMULATOR....... PROGRAMS IN KEIL VISION 3 SIMULATOR...............................................

3. VLSI DESIGNING
G) H) I) J) K) INTRODUCTION TO VLSI. SOFTWARES USED.. VLSI DESIGNED CIRUITS ON MENTOR GRAPHICS INTRODUCTION OF VHDL VHDL PROGRAMS IN MENTOR GRAPHICS MODELSIM

4. PCB DESIGNING
L) INTRODUCTION TO PRINTED CIRCUIT BOARD. M) PCB DESIGNING RULES N) PCB ETCHING PROCEDURE O) EXERCISE 1 P) EXERCISE 2

THAPAR UNIVERSITY
Thapar University, formerly Thapar Institute of Engineering and Technology, was founded in 1956 by Karam Chand Thapar. The university is situated in Patiala, Punjab. A Centre of Relevance and Excellence (CORE) has been set up at Thapar University by TIFAC Mission REACH of Department of Science & Technology, Government of India in its first phase of setting up eight CORES at various Institutes and Universities spread all over the country. Science and Technology Entrepreneurs Park (STEP) has been established jointly by Thapar University and DST, Govt. of India. Thapar University has grown in size and activities during the last five decades of its existence. Thapar University was granted full autonomy and the status of a Deemed University in 1985 UGC

HISTORY: The institute was established in 1956. The institute was

granted the status of a Deemed University in 1985 by the University Grants Commission. The Thapar University is one of three organisations located in the 250 acre campus, known as Thapar Technology Campus (TTC), in the historic city of Patiala. The university has been consistently ranked among the top 20 Engineering Colleges in India by India Today, Outlook and also among the top 20 private engineering colleges in the country by Dataquest and HT Mint. The University is also notable for its laurels in international forums like NASA Space Settlement Program and Society of Automobile Engineers (SAE) Formula Student, Europe. It is one of the oldest college which provide engineering degree even older than most of the NITs (government funded institutes)

CAMPUS: Thapar Institute of Engineering & Technology (TIET)

is a major institute in the 250-acre (1.0 km2) Thapar Technology Campus (TTC) in Patiala. Other than Thapar Institute of

Engineering and Technology, the Thapar Technology campus also has Thapar Polytechnic, Thapar Centre for Industrial Research and Development. It has been renovated with every modern facilities.It provides on-campus residence for all its students with better hostels than other government colleges.Chandigarh Campus is opening shortly.

DEPARTMENTS:
Biotechnology & Environment Sciences (BTESD) Chemical Engineering (CHED) Civil Engineering (CED) Computer Science & Engineering (CSED) Electrical & Instrumentation Engineering (EIED) Electronics & Communication Engineering (ECED) Mechanical Engineering Department (MED) Distance Education (DDE)

RANKINGS:
Thapar University was ranked #26 in the Outlook India Top Engineering Colleges of 2012[2] and #19 in the Dataquest India's Top Engineering Colleges 2011.[3] in the limited participation CSR-GHRDC Engineering Colleges Survey 2011 it was ranked #8.[4] In rankings limited to private schools it was ranked #5 in the Mint Top 50 Private Engineering Colleges of 2009[5] and #3 in the Electronics for You Top 50 Private Engineering Colleges of 2011

MICROCONTROLLER 8051
The Intel MCS-51 (commonly referred to as 8051) is a Harvard architecture, single chip microcontroller (C) series which was developed by Intel in 1980 for use in embedded systems.[1][2] Intel's original versions were popular in the 1980s and early 1990s. While Intel no longer manufactures the MCS-51, binary compatible derivatives remain popular today. In addition to these physical devices, several companies also offer MCS-51 derivatives as IP cores for use in FPGAs or ASICs designs. Intel's original MCS-51 family was developed using NMOS technology, but later versions, identified by a letter C in their name (e.g., 80C51) used CMOS technology and consumed less power than their NMOS predecessors. This made them more suitable for batterypowered devices.

IMPORTANT FEATURES AND APPLICATIONS:

The 8051 architecture provides many functions (CPU, RAM, ROM, I/O, interrupt logic, timer, etc.) in a single package

8-bit ALU, Accumulator and 8-bit Registers; hence it is an 8-bit microcontroller 8-bit data bus It can access 8 bits of data in one operation 16-bit address bus It can access 216 memory locations 64 KB (65536 locations) each of RAM and ROM On-chip RAM 128 bytes (data memory) On-chip ROM 4 kByte (program memory) Four byte bi-directional input/output port UART (serial port) Two 16-bit Counter/timers Two-level interrupt priority Power saving mode (on some derivatives)

8051 FAMILY:
Intel fabricated the original 8051 which is known as MCS-51. The other two members of the 8051 family are: i. 8052 This microcontroller has 256 bytes of RAM and 3 timers. In addition to the standard features of 8051, this microcontroller has an added 128 bytes of RAM and timer. It has 8K bytes of on chip program ROM. The programs written for projects using 8051 microcontroller can be used to run on the projects using 8052 microcontroller as 8051 is a subset of 8052. ii. 8031 This microcontroller has all the features of 8051 except for it to be ROM-less. An external ROM that can be as large as 64 K bytes should be programmed and added to this chip for execution. The disadvantage of adding external ROM is that 2 ports (out of the 4 ports) are used. Hence, only 2 ports are left for I/O operations which can also be added externally if required for execution.

PIN CONFIGURATION BASIC PINS:

PIN 9: PIN 9 is the reset pin which is used to reset the microcontrollers internal registers and ports upon starting up. (Pin should be held high for 2 machine cycles.) PINS 18 & 19: The 8051 has a built-in oscillator amplifier hence we need to only connect a crystal at these pins to provide clock pulses to the circuit. PIN 40 and 20: Pins 40 and 20 are VCC and ground respectively. The 8051 chip needs +5V 500mA to function properly, although there are lower powered versions like the Atmel 2051 which is a scaled down version of the 8051 which runs on +3V. PINS 29, 30 & 31: As described in the features of the 8051, this chip contains a built-in flash memory. In order to program this we need to supply a voltage of +12V at pin 31. If external memory is connected

then PIN 31, also called EA/VPP, should be connected to ground to indicate the presence of external memory. PIN 30 is called ALE (address latch enable), which is used when multiple memory chips are connected to the controller and only one of them needs to be selected.We will deal with this in depth in the later chapters. PIN 29 is called PSEN. This is "program store enable". In order to use the external memory it is required to provide the low voltage (0) on both PSEN and EA pins.

PORTS:
There are 4 8-bit ports: P0, P1, P2 and P3.

PORT P1 (Pins 1 to 8): The port P1 is a general purpose input/output

port which can be used for a variety of interfacing tasks. The other ports P0, P2 and P3 have dual roles or additional functions associated with them based upon the context of their usage.The port 1 output buffers can sink/source four TTL inputs. When 1s are written to portn1 pins are pulled high by the internal pull-ups and can be used as inputs. PORT P3 (Pins 10 to 17): PORT P3 acts as a normal IO port, but Port P3 has additional functions such as, serial transmit and receive pins, 2 external interrupt pins, 2 external counter inputs, read and write pins for memory access. PORT P2 (pins 21 to 28): PORT P2 can also be used as a general purpose 8 bit port when no external memory is present, but if external memory access is required then PORT P2 will act as an address bus in conjunction with PORT P0 to access external memory. PORT P2 acts as A8-A15, as can be seen from fig 1.1 PORT P0 (pins 32 to 39) PORT P0 can be used as a general purpose 8 bit port when no external memory is present, but if external memory access is required then PORT P0 acts as a multiplexed address and

data bus that can be used to access external memory in conjunction with PORT P2. P0 acts as AD0-AD7, as can be seen from fig 1.1 PORT P10: asynchronous communication input or Serial synchronous communication output.

INTERNAL ARCHITECTURE:

OSCILATOR CIRCUITS:

All operations in a microcontroller

are synchronized by the help of an oscillator clock. The oscillator clock generates the clock pulses by which all internal operations are synchronized. A resonant network connected through pins XTAL1 and XTAL2 forms up an oscillator. For this purpose a quartz crystal and capacitors are employed. The crystal run at specified maximum and minimum frequencies typically at 1 MHz to 16 MHz. When you read the spec a minimum frequencies would imply that some

internal memories must always operate above a minimum frequency or

data will be lost.

DATA AND PROGRAM MEMORY:

The 8051 Microcontroller can be programmed in PL/M, 8051 Assembly, C and a number of other high-level languages. Many compilers even have support for compiling C++ for an 8051. Program memory in the 8051 is read-only, while the data memory is considered to be read/write accessible. When stored on EEPROM or Flash, the program memory can be rewritten when the microcontroller is in the special programmer circuit.

Program Counter (PC):

A program counter fetches bytes from locations in memory that are addressed by the program counter. Program ROM is at addresses 0000h until 0FFFh. PC is automatically incremented after every instruction byte is fetched. PC does not have an internal address.

Data Pointer (DPTR):

DPTR or data pointer is made up of two 8-bit registers namely DPH and DPL needed for filling memory addresses internal and external code access. DPTR is specified by each individual byte name, DPH and DPL.

A B CPU registers:
8051 architecture has 34 general purpose or working registers. The logical and math operations are being hold by A and B registers. The other 32 registers hold the mathematical core operation. A register holds addition, subtraction, multiplication and division and Boolean bits manipulations. B register works together with A as storing data during multiplication and division.

Flags:
Flags is the 1-bit registers that stores results of certain program instructions. The flag make states that decisions can be made upon them. Flags are grouped inside program status word (PSW) and the power control (PCON) registers. 8051 architecture has four math flags function as a responder to the math operations results and three general purpose flags for setting or clearing 1 or 0 as the programmer desired. General purpose flags are named F0, GF0 and GF1 used to record some event. Math flags include 1. Carry (C) 2. Auxiliary Carry (AC) 3. Overflow (OV) 4. Parity (P)

Program status word:

Program status word or PSW contains math flags, user program flag F0 and register selected bits used to identify the four generalpurpose register banks that are currently in used. GF0 and GF1 are stored in PCON. See 8051 hardware.

Internal Memory
ROM and RAM have memory for program code bytes for variable data that can be altered when you run the program. You can provide external memory to internal memory by using suitable circuits.

Internal RAM:
Internal RAM has memory 128-byte. See 8051 hardware for further internal RAM design. Internal RAM is organized into three distinct areas: 1. 32 bytes working registers from address 00h to 1Fh 2. 16 bytes bit addressable occupies RAM byte address 20h to 2Fh, altogether 128 addressable bits 3. General purpose RAM from 30h to 7Fh

Stack Pointer:
There is an area inside internal RAM called stack that deals with certain op-codes for storing and retrieving data quickly. 8-bit Stack Pointer or SP is used by 8051 architecture for holding internal RAM address called top of stack. The stack operation stored last byte of data in the top of stack. When data send to stack, it will be incremented before data is stored. However SP will be decremented if data is retrieved from the stack. Operation of the stack is shown in 8051 hardware.

Special Function Registers (SFR):

Any 8051 architecture that do not use the internal 128-byte RAM addressees from 00h to 7Fh are being taken care of by Special Function register or SFR by using addresses from 80h to FFh. SFRs that has asterisk symbol shown are bit addressable that allows programming to change that needs to be changed and leave the remaining bits unchanged. SFR names and equivalent internal RAM addresses are given in 8051 hardware. SFRs are named in certain opcodes by their functional names such as A while referenced by other op-codes by addresses such as 0E0h.

Internal ROM:
Data memory and program code memory both are in different physical memory but both have the same addresses. An internal ROM occupied addresses from 0000h to 0FFFh. PC addresses program codes from 0000h to 0FFFh. Program addresses higher than 0FFFh that exceed the internal ROM capacity will cause 8051 architecture to fetch codes bytes from external program memory.

8051 INSTRUCTION SET

KEIL VISION3 8051 SIMULATOR

Keil was founded in 1982 by Gnter und Reinhard Keil, initially as a German GbR. In April 1985 the company was converted to Keil Elektronik GmbHto market add-on products for the development tools provided by many of the silicon vendors. Keil implemented the first C compiler designed from the ground-up specifically for the 8051 microcontroller. Keil provides a broad range of development tools like ANSI C compiler, macro assemblers, debuggers and simulators, linkers, IDE, library managers,real-time operating systems and evaluation boards for 8051, 251, ARM, and XC16x/C16x/ST10 families.

A51 ASSEMBLER:
The A51 Assembler is a macro assembler for the 8051 family of microcontrollers. It supports all 8051 derivatives. It translates symbolic assembly language mnemonics into relocatable object code where the utmost speed, small code size, and hardware control are critical. The macro facility speeds development and conserves maintenance time since common sequences need only be developed once. The A51 assembler supports symbolic access to all features of the 8051 architecture. The A51 assembler translates assembler source files into a relocatable object modules. The DEBUG directive adds full symbolic information to the object module and supports debugging with the Vision Debugger or an in-circuit emulator. In addition to object files, the A51 assembler generates list files which may optionally include symbol table and cross reference information.

8051 PROGRAMMING USING KEIL VISION3

When using the Keil tools, the project development cycle is similar to any other software development project. 1. Create a project, select the target device from the Device Data base, and configure the tool settings 2. Create your source files in C/C++ or Assembly 3. Build your application with the Project Manager 4. Debug and correct errors in source files, verify and optimize your application 5. Download your code to Flash ROM or SRAM and test the linked application.

QUES 1: WRITE A PROGRAM TO ADD 10 , 8 BIT NUMBERS

STARTING FROM THE LOCATION 30H AND STORE THE RESULT IN LOCATION FROM 3A ON KEIL VISION 3 SIMULATOR .

ANS:
PROGRAM:

ADDING PROGRAM TO SOURCE GROUP:

BUILDING OF THE PROGRAM:

MEMORY WINDOW AFTER DEBUGGING:

QUES 2: WRITE A PROGRAM TO GENERATE A SQUARE

WAVE USING A MICROCONTROLLER 8051 OF SOME CERTAIN FREQUENCY ON KEIL VISION 3 SIMULATOR .

ANS:
PROGRAM:

SQUARE WAVE ON LOGIC ANALYSER:

8051 MICROCONTROLLER KIT:

EXPERIMENT ON 8051 KIT:

QUES 3: WRITE A PROGRAM TO GLOW THE LED
ALTERNATIVELY ON AND OFF CONNECTED ON THE 8051 KIT ON KEIL VISION 3 SIMULATOR .

ANS:
PROGRAM:

QUES 4: WRITE A PROGRAM FOR DISPLAYING OUR

NAME ON THE LCD DISPLAY IN THE 8051 KITON KEIL VISION 3 SIMULATOR .

ANS:
PROGRAM:

QUES 5: WRITE A PROGRAM FOR GLOWING LEDS ,

NAME ON LCD AND DISPLAYING A NO. PATTERN FROM 1 TO 9 ON THE ALTERNATIVE 7 SEGMENT DISPLAYS ON KEIL VISION 3 SIMULATOR .

ANS:
PROGRAM:

VERY LARGE SCALE INTEGRATION

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. VLSI began in the 1970s when complexsemiconductor and communication technologies were being developed. The microprocessor is a VLSI device. Gone are the days when huge computers made of vacuum tubes sat humming in entire dedicated rooms and could do about 360 multiplications of 10 digit numbers in a second. Though they were heralded as the fastest computing machines of that time, they surely dont stand a chance when compared to the modern day machines. Modern day computers are getting smaller, faster, and cheaper and more power efficient every progressing second. But what drove this change? The whole domain of computing ushered into a new dawn of electronic miniaturization with the advent of semiconductor transistor by Bardeen (1947-48) and then the Bipolar Transistor by Shockley (1949) in the Bell Laboratory.

MENTOR GRAPHICS ARCHITECHTURE:

DESIGN

Complex design challenges characterized by shrinking geometry, functionality within both the hardware and software domains, and strict requirements for performance and power efficiency driven by the designated application, are changing how systems are being designed. In the consumer markets, users experience is a key for product success. It is determined by the performance of the combined hardware and software application. To achieve an optimal architecture and allow design scalability, design engineers must maintain visibility over the power and performance requirements ahead of production when the greatest impact on design implementation is still possible. Architecture design is the task carried by the system architects and SoC designers who need to architect, integrate and optimize complex systems meeting power and performance requirements. During the platform definition process, macro-architecture and micro-architecture decisions need to be made such as HW/SW tradeoffs, processors selection, interconnect and memory hierarchies, fabric infrastructures, and caching strategies. When designing complex interconnect fabrics (such as storage and networking), architecture exploration is usually done ahead of the functional design phase by using statistical non-functional models and traffic generators that simulate various data distributions and loads. Alternately, in SoC and embedded applications, performance can be explored along with functional validation and software execution. It is critical to be able to balance power and performance in conjunction with hardware and software functionality, and then trade hardware vs. software implementations in a methodical and predictable way.

FEATURES:

Set of configurable TLM 2.0-based architecture blocks Intuitive graphical platform assembly tool Tracing of data packets, model states and design attributes

Advanced analysis and visualization Hardware / software tradeoff analysis Early assessment of timing and power

MENTOR GRAPHICS IC STATION:

The Integrated Circuit (IC) tools that operate in the IC Environment are collectively called IC Station, The IC Environment is an IC development environment you invoke from the Design Manager or a shell. The Design Manager is a concurrent design environment comprised of both a graphical user interface and a set of management facilities that help you to create and manage your schematic, PC board, and IC layout designs. IC Station tools use the Falcon Framework, which provides the Common User Interface (CUI) for all Mentor Graphics tools, supports, multiple editing windows, and manages your layout's database. The IC Station tools provide you with the capability to design full custom cells and mixed standard cell and block hierarchical layouts. You can also use a C program interface; translate a design between the IC Environment, GDT, GDSII, and CIF formats; edit polygons; and automatically floorplan, place, route, and compact your design. Whether you are performing a full custom or automated layout, you can use the floorplanner to sketch out your design and the compactor to optimize it. Additionally, you can use the IC Station tools to verify your layout, compare your layout to a schematic, extract parasitics, and backannotate parasitic results to a schematic. The schematic capture, digital simulation, and design configuration tools, each of which you can independently invoke from the Design Manager or a shell, are collectively called Idea Station. The Idea Station tools provide you with the capability to describe a design using the Very High-Speed Integrated Circuit (VHSIC) hardware description language, perform both schematic capture and digital simulation, configure your designs, ANd manage backannotations.

VLSI DESIGNED CKTS

CIRCUIT 1: CMOS INVERTER

An inverter circuit outputs a voltage representing the opposite logiclevel to its input. Inverters can be constructed using a single NMOS transistor or a single PMOS transistor coupled with aresistor. Since this 'resistive-drain' approach uses only a single type of transistor, it can be fabricated at low cost. However, because current flows through the resistor in one of the two states, the resistive-drain configuration is disadvantaged for power consumption and processing speed. Alternatively, inverters can be constructed using two complementary transistors in a CMOSconfiguration. This configuration greatly reduces power consumption since one of the transistors is always off in both logic states. Processing speed can also be improved due to the relatively low resistance compared to the NMOS-only or PMOS-only type devices. Inverters can also be constructed with bipolar junction transistors (BJT) in either a resistor-transistor logic (RTL) or atransistor-transistor logic (TTL) configuration. Digital electronics circuits operate at fixed voltage levels corresponding to a logical 0 or 1 (see binary). An inverter circuit serves as the basic logic gate to swap between those two voltage levels. Implementation determines the actual voltage, but common levels include (0, +5V) for TTL circuits.

CIRCUIT ON MENTOR GRAPHICS DESIGN ARCHITECHTURE:

VOLTAGE TRANSFER CHARACTERSTICS:

TRANSIENT RESPONSE:

CIRCUIT 2: IMPLEMENTING NAND AND NOR GATE CIRCUITS:

Notice how transistors Q1 and Q3 resemble the series-connected complementary pair from the inverter circuit. Both are controlled by the same input signal (input A), the upper transistor turning off and the lower transistor turning on when the input is "high" (1), and vice versa. Notice also how transistors Q2 andQ4 are similarly controlled by the same input signal (input B), and how they will also exhibit the same on/off behavior for the same input logic levels. The upper transistors of both pairs (Q1 and Q2) have their source and drain terminals paralleled, while the lower transistors (Q3 and Q4) are seriesconnected. What this means is that the output will go "high" (1) if either top transistor saturates, and will go "low" (0) only if both lower transistors saturate. The following sequence of illustrations shows the behavior of this NAND gate for all four possibilities of input logic levels (00, 01, 10, and 11)

A CMOS NOR gate circuit uses four MOSFETs just like the NAND gate, except that its transistors are differently arranged. Instead of two paralleled sourcing(upper) transistors connected to Vdd and two series-connected sinking (lower) transistors connected to ground, the NOR gate uses two series-connected sourcing transistors and two parallel-connected sinking transistors like this:

As with the NAND gate, transistors Q1 and Q3 work as a complementary pair, as do transistors Q2 and Q4. Each pair is controlled by a single input signal. Ifeither input A or input B are "high" (1), at least one of the lower transistors (Q3 or Q4) will be saturated, thus making the output "low" (0). Only in the event of both inputs being "low" (0) will both lower transistors be in cutoff mode and both upper transistors be saturated, the conditions necessary for the output to go "high" (1). This behavior, of course, defines the NOR logic function.

CIRCUIT FOR NAND USING MOSFETS:

CIRCUIT FOR NOR USING MOSFETS:

TRANSIENT RESPONSE FOR NAND GATE:

TRANSIENT RESPONSE FOR NOR GATE:

CIRCUIT3: IMPLEMENT RESISTIVE LOAD INVERTER WITH SPECIFICATION RL=1K, (W/L)N=3.

The input voltage of the inverter circuit is also the gate-to-source voltage of the nMOS transistor (Vi' = VGs), while the output voltage of the circuit is equal to the drain-to-source voltage (V", = VDS). The source and the substrate terminals of the nMOS transistor, also called the driver transistor, are connected to ground potential; hence, the source-to substrate voltage is VSB = 0. In this generalized representation, the load device is represented as a two-terminal circuit element with terminal current IL and terminal voltage VL(IL). Oneterminal of the load device is connected to the drain of the nchannel MOSFET, while the other terminal is connected to VDD, the power supply voltage. We will see shortly that the chaRacteristics of

the inverter circuit actually depend very strongly upon the type and the characteristics of the load device.

CIRCUIT FOR RESISTIVE LOAD INVETER ON MENTOR GRAPHICS:

VOLTAGE TRANSFER CHARACTERSTICS:

TRANSIENT RESPONSE LOAD INVERTER:

OF

RESISTIVE

CIRCUIT4: XOR GATE USING MOSFETS ON MENTOR GRAPHICS :

The XOR gate (sometimes EOR gate, or EXOR gate) is a digital logic

gate that implements an exclusive or; that is, a true output (1) results if one, and only one, of the inputs to the gate is true (1). If both inputs are false (0) or both are true (1), a false output (0) results. Its behavior is summarized in the truth table shown on the right. A way to remember XOR is "one or the other but not both". It represents the inequality function, i.e., the output is HIGH (1) if the inputs are not alike otherwise the output is LOW (0). TRANSIENT RESPONSE:

CIRCUIT5: CMOS LAYOUT ON MENTOR GRAPHICS :

Complementary metaloxidesemiconductor (CMOS) ( /sims/) is a technology for constructing integrated circuits. CMOS technology is used inmicroprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters, and highly integrated transceivers for many types of communication. Frank Wanlass patented CMOS in 1967 (US patent 3,356,858). CMOS is also sometimes referred to as complementary-symmetry metaloxidesemiconductor (or COS-MOS).[1] The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions

Design Rule Checker (DRC):

This is a program that checks each piece of the layout against the process design rules. This is a slow process: canonicalize layout into a set of leading and trailing non-overlapping mask edges. Some boolean mask operations may be needed. determine electrical connectivity and label each edge with the node it belongs to. test each edge end point against neighboring edges to check for spacing (leading edges) and width (trailing edges) violations. Layout vs. Schematic (LVS): First a netlist is extracted from the layout. Use the electrical info generated by the DRC and then recognize transistors are juxtapositions of channel with diffusion. Then see if extracted netlist is isomorphic to the schematic netlist. This is done by a coloring algorithm: initialize all nodes to the same color

compute a new color for each node as some hashing function involving the colors of connected (ie, thru a fet) nodes. nodes that have a unique color are isomorphic to similarly colored node in other network worry about parallel fets, ambiguous nodes. CMOS LAYOUT:

CMOS SCHEMATIC:

LAYOUT VS SCHEMATICS:

VERY HIGH SPEED INTEGRATED CIRCUIT HARDWARE DESCRIPTION LANGUAGE

VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits). It is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. The complexity of the digital system being modeled could vary from that of a simple gate to a complete digital electronic system, or anything in between. The digital system can also be described hierarchically. Timing can also be explicitly modeled in the same description. The VHDL language can be regarded as an integrated amalgamation of the following languages: sequential language + concurrent language + net-list language + timing specifications + waveform generation language => VHDL Therefore, the language has constructs that enable you to express the concurrent or sequential behavior of a digital system with or without timing. It also allows you to model the system as an interconnection of components. Test waveforms can also be generated using the same constructs. All the above constructs may be combined to provide a comprehensive description of the system in a single model. The language not only defines the syntax but also defines very clear simulation semantics for each language construct. Therefore, models written in this language can be verified using a VHDL simulator. It is a strongly typed language and is often verbose to write. It inherits many of its features, especially the sequential language part, from the Ada programming language. Because VHDL provides an extensive range of modeling capabilities, it is often difficult to understand.

Fortunately, it is possible to quickly assimilate a core subset of the language that is both easy and simple to understand without learning the more complex features. This subset is usually sufficient to model most applications. The complete language, however, has sufficient power to capture the descriptions of the most complex chips to a complete electronic system.

VHDL is used to describe a model for a digital hardware device. This model specifies the external view of the device and one or more internal views. The internal view of the device specifies the functionality or structure, while the external view specifies the interface of the device through which it communicates with the

other models in its environment. Figure I.I shows the hardware device and the corresponding software model. The device to device model mapping is strictly a one to many. That is, a hardware device may have many device models. For example, a device modeled at a high leyel of abstraction may not have a clock as one of its inputs, since the clock may not have been used in the description. Also the data transfer at the interface may be treated in terms of say, integer values, instead of logical values. In VHDL, each device model is treated as a distinct representation of a unique device, called an entity in this text. Figure 1.2 shows the VHDL view of a hardware device that has multiple device models, with each device model representing one entity. Even though entity I through N represent N different entities from the VHDL point of view, in reality they represent the same hardware device.

MENTOR GRAPHICS MODELSIM

Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim the simulator of choice for both ASIC and FPGA designs. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows. OVERVIEW:

Unified mixed language simulation engine for the fastest regression suite throughput Native support of Verilog, SystemVerilog for design, VHDL, and SystemC for effective verification of the most sophisticated design environments Fast time-to-debug causality tracing and multi-language debug environment Advanced code coverage and analysis tools for fast time to coverage closure BENEFITS AND FEATURES: High-performance, high-capacity engine for the fastest regression suite throughput Native support of Verilog, VHDL, and SystemC for effective verification of the most sophisticated design environments Fast time-to-debug causality tracing and multi-language debug environment Advanced code coverage and analysis tools for fast time to coverage closure

EXAMPLE 1: WRITE VHDL CODE FOR HALF SUBTRACTOR IN BEHAVIOUR STYLE & PERFORM BEHAVIOUR SIMULATION AND SYNTHESIS

RTL SCHEMATIC:

SIMULATION WAVEFORMS:

EXAMPLE2: WRITE VHDL CODE FOR 4:1 MUX & 8:1 MUX USING CASE STATEMENT & PERFORM BEHAVIOUR SIMULATION AND SYNTHESIS VHDL CODE FOR 4:1 MUX:

VHDL CODE FOR 8:1 MUX:

RTL SCHEMATIC FOR 4:1 MUX:

RTL SCHEMATIC FOR 8:1 MUX:

SIMULATION WAVEFORM FOR 4:1 MUX:

SIMULATION WAVEFORM FOR 8:1 MUX:

EXAMPLE3: : WRITE VHDL CODE FOR FULL ADDER USING TWO HALF ADDERS IN STRUCTURAL STYLE

RTL SCHEMATIC:

SIMULATION WAVE FORM:

EXAMPLE4: WRITE VHDL CODE FOR D FLIP FLOP (+VE EDGE TRIGERRED):

RTL SCHEMATIC:

SIMULATION WAVE FORM:

EXAMPLE5: WRITE VHDL CODE FOR 4 BIT SERIAL IN SERIAL OUT SHIFT REGISTER

RTL SCHEMATIC:

SIMULATION WAVEFORM:

PRINTED CIRCUIT BOARD:

A printed circuit board, or PCB, is used to mechanically support and electrically connect electronic components using conductive pathways, tracks or signal traces etched from copper sheets laminated onto a nonconductive substrate. It is also referred to as printed wiring board(PWB) or etched wiring board. Printed circuit boards are used in virtually all but the simplest commercially produced electronic devices. A PCB populated with electronic components is called a printed circuit assembly (PCA), printed circuit board assembly or PCB Assembly(PCBA). In informal use the term "PCB" is used both for bare and assembled boards, the context clarifying the meaning. Alternatives to PCBs include wire wrap and point-to-point construction. PCBs must initially be designed and laid out, but become cheaper, faster to make, and potentially more reliable for high-volume production since production and soldering of PCBs can be automated. Much of the electronics industry's PCB design, assembly, and quality control needs are set by standards published by the IPC organization.

PCB DESIGNING RULES:

In the PCB design of electronics circuit, it is important that one plan and has a checklist of the do's and don'ts before proceeding to do the printed circuit board layout. The understanding of the circuit is critical to the design, for example one needs to understand the maximum current and voltage that are carried by each conductor in order to determine the track width of the conductor and the type of PCB that will be used. The voltage difference between each track will determine the clearance between each conductor. If the clearance is not enough, chances are that the electrical potential between each track will cause spark over and short circuit the PCB. This will cause functional failure to the product and the safety of the users that are using the product will be compromised. It is therefore critical for one to understand some of this basics requirements before one proceed to design the PCB.

TRACKS RESTRICTED AREA:

Tracks should not be located on the areas that can caused them to be peeled off easily. One of the restricted area is holes on the PCB which are used to mount screws or PCB spacers. These holes are usually used to secure the PCB to a casing or to secure it in a fixed place. The edges of the PCB should not have any tracks as these areas are usually used to transport the PCB from one process to another process by using a conveyor belt. These edges are places where the possibility of scratches and cracking of the PCB happens. The recommended areas that should not have any track is as shown in the diagram below assuming a hole diameter of 4 mm which is used to mount a PCB spacer.

CONDUCTOR THICKNESS AND WIDTH:

The PCB conductor thickness and width will determine the current carrying capacity of the track. The IPC standard for the conductor thickness and width of the common 1 oz/square-feet PCB is as shown below. However, it is always advisable to use a bigger value due to the tolerance and variation of the PCB processes. If higher current carrying capacity is required, a 2 oz/square-feet or 3 oz/square-feet type of PCB is preferred. Many electronics hobbyist prefer to solder a thick cooper conductor on the PCB track to increase the current carrying capacity of the track.

PCB DESIGN ELECTRICAL CONSIDERATION:

Many safety standards call for a minimum of 8mm clearance between 240V mains and other isolated signal tracks. These safetystandards are to ensure that the users that are using the products will be protected from any electrical hazards. For non main voltages, IPC recommend the electrical clearance between adjacent tracks. It is important to know the maximum difference in voltage that are applied on the adjacent tracks of a PCB. The electrical clearance specs of IPC standard is as shown below for various condition of the PCB. Coating the PCB will help to reduce the requirements of the track clearance. However, the quality of the coating as well as the material used are critical to ensure that these requirements are met. Again, it is always advisable to increase the clearance to cater for the variations of the PCB processes.

PCB ETCHING:
PCB etching in 5 steps presented on instructables.com. A simple 5step process to etch your own printed circuit boards at home. Youll need the following ingredients:

laser printer/photocopier & transparencies copper board scrubbing pads iron rubber gloves Ferric Chloride or Ammonium Persulphate drill and drill bits

1. PCB Design and print: Design your PCB. I use anything from Adobe Illustrator to Cadsoft Eagle. Once you think everything is perfect, print it on a piece of paper and test it by placing your components over it. You have to flip horizontal your final design so that the transfer from the transparency to the copper board restores the intended design Then print it on a transparency. It has to be a laser printer or a photocopier because we want toner on the transparency. If you can, ask the guy at the print shop to make it as dark as possible (more toner). Ive noticed that Ive had the best results at the worst print shops in town. 2. Transfer the toner: Now you want to transfer the toner (mostly made of molten plastic) onto the copper board. Set the iron to silk (youll have to experiement with the temperatureit took me quite a while to consistently get good results).

Clean and rinse the board with the scrubbing pads and soap. Dry it up. Place the transparency on the copper board, place a piece of paper on top if it all and start ironing! Depending on the size of your circuit, it takes about 2-3 minutes for the copper board to get hot enough so the toner sticks to it. When you think youre good, immerse the copper board (with the transparency stuck to it) in cold water. Then you should be able to peel off the transparency while the toner remains on the copper board. If the toner did not transfer completely, you didnt iron long enough and/or didnt set the temperature high enough. If the toner transfered but is smudged on the copper board, the temperature was too high and/or you ironed for too long. You can use a Sharpie or any other permanent marker to fix parts of the circuit that did not transfer properly. 3. PCB Etch: Youre almost done. Put the gloves on, pour some etchant in a plastic or glass container and immerse the board. At room temperature, it can take up to half an hour. Mixing the solution as its etching can speed up the process. Another good way to dramatically decrease the etching time is to warm up the solution. Now I strongly discourage you to get creative with the microwave or your precious pots and pans. You can however dip the container in warm water poured from the tap. When it looks good, clean the board in running water. 4. Clean the PCB Board: Use the scrubbing pads to remove the toner from the board. You can reuse the etching solution, so just pour it back in the original container. Do not pour it down the drain! It will corrode your copper pipes Over time, the etching process will take longer and longer. When the solution becomes unusable, contact the waste management organisation in your community to know where to dispose of the chemical.

5. PCB Drill: For those of you who do not use surface mount components, youll need to drill holes in your circuit board. I use a Dremel (you can find generic versions for less than 40$). Youll need tiny drill bits (#66#60). Most places youll go to will rip you off with those tiny precise bits (10-15$ each). However, some places like Lee Valley sells them for ~$0.50 each.

LAYOUT FOR EXERCISE 1:

LAYOUT FOR EXERCISE 2: