PHYS 162 - Chapter 8

Field Effect Transistor

CHAPTER 8 FIELD EFFECT TRANSISTOR (FETs)

INTRODUCTION
FETs are voltage controlled devices as opposed to BJT which are current controlled. There are two types of FETs. o Junction FET (JFET) o Metal Oxide Semiconductor FET (MOSFET) The basic difference between the two is in terms of their construction. Both have the advantage of high input resistance and low output resistance as compared to BJT. Both have an advantage of high power output.

8-1 THE JFET

JFET operate with a reverse biased pn junction to control the current in a channel. Depending upon the construction, JFETs fall in either of two categories, o n-channel o p-channel The basic representation of the both is given in Figure 1. Wires are connected to each end of the n-channel (Figure 1a). Upper end is the Drain while the lower end is the Source. Two p-types regions are diffused in the n-channel to form a channel. Both p-regions are connected to the Gate.

Figure 1 Basic structure of JFET

8.1.1 Basic Operation

The basic operation of the JFET is illustrated in Figure 2 which shows a biased n-channel JFET. VDD is the drain-to-source voltage and provides the drain current ID. VGG sets the reverse bias between the gate and the source. JFET is always operated with the gate-source pn junction reverse biased. The reverse bias produces a depletion region along the pn junction and increases the resistance of the channel which controls the current.

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Therefore, VGS, the gate-source voltage can be changed to control the amount of drain current ID flowing in the channel.

Figure 2 Biased n-channel JFET

Figure 3 Effect of VGS on channel width, resistance and drain current

8.1.2 JFET Symbols

The schematic symbols for n-channel and p-channel JFETs are shown in Figure 4. The in arrow on the gate indicates an n-channel JFET while the out arrow indicates p-channel.

Figure 4 JFET schematic symbols

8.2 JFET CHARACTERISTICS AND PARAMETERS

JFET is a voltage-controlled, constant-current device. The controlling voltage for JFET is VGS. Following is an explanation to understand the characteristics and parameters of JFET (Figure 5a): o Consider the case when gate-to-source voltage = 0. o As VDD and thus VDS is increased, ID will increase. This is highlighted in the graph of Figure 5b between points A and B. o This region is called the Ohmic Region and in this region channel resistance is constant. o At point B, the curve of Figure 5b levels and enters the active region. o In this region, ID is constant. o As voltage VDS is increased, the drain current ID remains constant between points B and C.
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Figure 5 Drain characteristic curve of a JFET for VGS=0V

8.2.1 Pinch Off

At = 0, the value of VDS where ID becomes constant (Point B on Figure 5b) is called Pinch-Off voltage, Vp. A given JFET has fixed value of Vp given in datasheets. At = 0, the value of the constant drain current is called IDSS (Drain to Source current gate Shorted). IDSS is given in datasheets. IDSS is the maximum current a JFET can produce.

8.2.2 Breakdown
Breakdown occurs at point C when ID increases very rapidly. Breakdown can damage the transistor. JFETs should be operated below breakdown in the active region (between point B and C).

8.2.3 VGS controls ID

Connect a bias voltage VGG from gate to source as shown in Figure 6a. As VGS becomes more negative ( < 0), the resistance of the n-channel increases with the increase in the depletion region. As we keep on decreasing VGS, a family of drain characteristic curves is produced as shown in Figure 6b. Drain current ID decreases with more negative VGS. This behavior illustrates that the drain current is controlled by VGS.

8.2.4 Cutoff Voltage

The value of VGS that makes ID approximately zero is the cutoff voltage VGS(off). A JFET must be operated between = 0 and VGS(off).

8.2.5 Comparison of Pinch-Off Voltage and Cutoff Voltage

VGS(off) and Vp are always equal in magnitude but opposite in sign. So = . Anyone one of the two parameters is mentioned in the datasheet but not both.
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NOTE: REFER EXAMPLE 8-1 PAGE 375

Figure 6 VGS controls ID

8.2.6 JFET Universal Transfer Characteristic

We now know that VGS controls ID. Therefore the relationship between VGS and ID is very important. Figure 7 shows a general characteristic curve that graphically shows how VGS and ID are related. This graph is known as a transconductance curve.

Figure 7 JFET universal transfer characteristic curve

Following points need to be noticed about the graph: o = 0 when = o = o =

2 4

when = 0.5 when = 0.3

o = when = 0 The mathematical relation between the drain current ID and VGS can be given approximately as

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PHYS 162 - Chapter 8

1 -

Field Effect Transistor

The above equation can determine ID for any given value of VGS if IDSS and VGS(off) are known. IDSS and VGS(off) are given in the datasheets. NOTE: REFER EXAMPLE 8-3 PAGE 377

8.2.7 JFET Forward Transconductance

Transconductance can be roughly defined as the inverse of resistance. The forward transconductance of the JFET is given by symbol gm. It is the change in the drain current ( ) for a given change in the gate-to-source voltage ( ) with constant VDS. It is expressed as a ratio and has a unit of Siemens (S) or mho. = As the JFET transfer curve is nonlinear, gm varies in value on different location of the curve.

gm is greater at the top (near = 0) of the curve as compared to the bottom (near shown in Figure 8. The datasheet normally gives values of gm at = 0 (gm0). Given gm0, we can calculate gm at any point on the curve using the following formula:

Figure 8 gm varies depending on VGS

) as

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= 0 1 -

If gm0 is not available, we can use the following formula to calculate it: 0 = 2

NOTE: REFER EXAMPLE 8-4 PAGE 379

8.2.8 Input Resistance

The input resistance of JFETs is extremely high as compared to BJTs. This is due to the reverse bias at the gate-to-source junction which increases the depletion region at the junction and thus increases the resistance. The input resistance can be determined by the following formula: =

8.3 JFET Biasing

The main purpose of DC biasing is to select the proper DC gate-to-source voltage VGS to establish a desired value of drain current ID which is the Q-point of the circuit. There are 3 types of bias circuit used with JFETs. o Self Bias o Voltage Divider Bias o Current Source Bias

8.3.1 Self-Bias
Self-bias is the most common type of bias circuit for JFET. Figure 9 shows the self-bias circuit for n-channel (Figure 9a) and p-channel (Figure 9b) JFETs. The gate terminal being grounded through RG results in = 0.

Figure 9 Self-bias JFET

This setup achieves the reverse bias condition of the gate required for proper biasing of JFET. NOTE: REFER EXAMPLE 8-6 PAGE 382
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8.3.2 Setting the Q-Point of a Self Biased JFET

For setting a Q-point, first either find ID for some VGS or vice versa. Then calculate the required RS by the following relation: = For a desired value of VGS, ID can be determined in two ways. o Graphical using the transfer curve. o Using Equation of 1

where IDSS and VGS(off) are given.

NOTE: REFER EXAMPLE 8-7 PAGE 383

8.3.2.1 Midpoint Bias

It is good to bias a JFET near the midpoint of the transfer curve. At the midpoint = 2 = 3.4 = 2 Select a value of RD to get the required VD. Choose RG large enough (mega ohm range). NOTE: REFER EXAMPLE 8-9 PAGE 384

8.3.3 Graphical Analysis of a Self-Biased JFET

The transfer characteristic curve of a JFET can be used to find the Q-point (ID and VGS) of a self biased circuit. If the curve is not given then it can be plotted using the equation of ID and using the datasheet values of IDSS and VGS(off). To determine the Q-point of the circuit, a DC load line must be drawn. The DC load line is established as follows (illustrated in Figure 10): o At = 0 find = = 0. This gives us the first point of the load line. o At = find = = . This gives the second point. Connecting these two points establishes the load line. o The point where the load line intersects the transfer curve is the Q-point. o Note the corresponding values of ID and VGS at the Q-point.

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Figure 10 Self-bias DC load line

NOTE: REFER EXAMPLE 8-10 PAGE 386

8.3.4 Voltage-Divider Bias

An n-channel JFET with voltage-divide bias is shown in Figure 11. For proper biasing, the voltage at the source must be more positive than the voltage at the gate. This ensures that the gate-source junction is reverse biased. NOTE: REFER EXAMPLE 8-11 PAGE 388

8.3.5 Graphical Analysis of a JFET with Voltage-Divider Bias

A similar approach as JFET self-biased circuit can be used to find the Q-point graphically. The DC load line is established as follows (illustrated in Figure 12): o At = 0 find = . This gives us the first point of the load line. o At = 0 find =

. This gives the second point. Connecting these

Figure 11 JFET voltagedivider bias

two points establishes the load line. o Extending the load line to intersect the transfer curve gives us the Q-point. o Note the corresponding values of ID and VGS at the Q-point.

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Figure 12 DC load line for JFET voltage-divider bias

NOTE: REFER EXAMPLE 8-12 PAGE 389

8.3.6 Q-Point Stability

The transfer characteristic curve differs from one JFET to the other of the same type. This behavior is not suitable for circuit parameter stability. This difference in curve may cause the Q-point to change significantly. Figure 13 shows a typical transfer curve of two JFETs 2N5459. Figure 13a is for self-biased while Figure 13b is for the voltage-divider biased. As can be seen, both have different transfer curves. Changing one with the other changes the Q-point dramatically. It is worth noting that in terms of Q-point stability, voltage-divider bias is better then the self-bias circuit. This can be seen by the amount of change in the drain current for both the circuits.

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Figure 13 Variation in transfer curve and Q-point of self-biased and voltage-divider biased JFET of the same type

The change in the drain current value for self-bias is more then the change for the same in voltagedivider. The reason for this is that the slope of the load line for voltage-divider is much gradual then the slope of the load line for self-biased and thus the change in y-axis is small.

8.3.4 Current-Source Bias

Current-source bias is a method for increasing the Q-point stability of a self-biased JFET. This is done by making drain current independent of VGS. This is accomplished by using a constant current source in series with JFET source as shown in Figure 14. In this circuit, the BJT acts as a constant current source so the emitter current is constant. This makes the drain current constant because

As can be seen from the transfer characteristic curve of 2 different JFET, the drain current remains constant thus providing highly stable Q-point.

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Figure 14 Current-source bias

8.4 THE OHMIC REGION

Ohmic region is the part of the FET characteristic curve where Ohms law can be applied. A proper biased JFET exhibits property of variable resistance in this region. Ohmic region extends from the point where = 0 to the point where ID becomes constant. The slope of the characteristic curve can be taken to be constant for small values of I D. The slope of the curve is the DC drain-to-source conductance given by = = As resistance is inverse of conductance, the DC drain-to-source resistance is given by 1 = =

Figure 15 Ohmic region in shaded area

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8.4.1 JFET as a Variable Resistance

A JFET is biased in the Ohmic region to be used a voltage-controlled variable resistor. The controlling voltage is VGS which determines the resistance by changing the Q-point.

Figure 16 Load line intersect the curves inside the Ohmic region

To bias the JFET in the Ohmic region, the load line must intersect the curves inside the Ohmic region as shown in Figure 16. This is done by setting the DC saturation current ID(sat) much less than IDSS. Figure 16 shows 3 Q-points in the Ohmic region. As you move along the load line or change the Q-point, the resistance RDS changes as the slope at each Q-point are different. If the Q-point is moved from = 0 to = 2, the slope at each point is less then the previous one. This means less ID and more VDS which results in increase in RDS. NOTE: REFER EXAMPLE 8-14 PAGE 394

8.5 THE MOSFET

Metal Oxide Semiconductor FET is another type of FET. It is different from JFET as it does not contain a pn junction instead the gate is insulated from the channel by a silicon dioxide (SiO2) layer. There are two types of MOSFET o Enhancement (E) MOSFET most commonly used. o Depletion (D) MOSFET

8.5.1 Enhancement MOSFET (E-MOSFET)

Enhancement MOSFET only operates in the enhancement mode and there is no depletion mode. Figure 17 shows the structure of an n-channel E-MOSFET. It does not contain any n-channel.
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Instead the channel is induced by a positive threshold voltage at the gate that pulls the electrons to make the channel.

Figure 17 E-MOSFET schematic symbols

Figure 18 E-MOSFET structure

This structure makes it possible to have more conduction by pulling more electrons in the channel. Figure 18 shows the schematic symbols of n-channel and p-channel E-MOSFETs.

8.5.2 Depletion MOSFET (D-MOSFET)

Another type of MOSFET is the Depletion MOSFET (D-MOSFET). The basic structure of n-channel and p-channel D-MOSFET is shown in Figure 19. Unlike the E-MOSFET, there is a small channel in the D-MOSFET. This channel enables it work in both the enhancement mode as well as the depletion mode.

Figure 19 D-MOSFET structure

It operates in depletion mode when < 0 and operates in enhancement mode when > 0. Applying negative VGS at the gate terminal of a D-MOSFET repels the electrons in the n-channel and replaces it by hole. This depletes the channel of any electrons and when = , the channel is totally depleted and drain current ID becomes zero. Applying positive VGS at the gate terminal of a D-MOSFET attracts more electrons in the n-channel.
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8.5.2.1 Depletion Mode

8.5.2.2 Enhancement Mode

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Field Effect Transistor

This increases or enhances the channel conductivity. Figure 20 shows the schematic symbols of n-channel and pchannel D-MOSFET.

8.5 MOSFET CHARACTERISTICS AND PARAMETERS

Most of the concepts of JFET characteristics and parameters apply equally to MOSFETs. We shall discuss the characteristics of both the MOSFETs separately.
Figure 20 D-MOSFET schematic symbols

8.5.1 E-MOSFET Transfer Characteristics

The E-MOSFET only operates in the enhancement mode. So an n-channel device requires positive VGS and p-channel requires negative VGS. Figure 21 shows the transfer characteristic curve of n-channel and p-channel E-MOSFET. = 0 at = 0 so there is no IDSS in E-MOSFETs. Ideally there is no drain current until VGS reaches a specific value called the threshold voltage, VGS(th).

Figure 21 E-MOSFET transfer curve

The equation for the drain current in E-MOSFET differs from JFET and is given by = = 2 Where values of ID(on) is specified in the datasheets at a given VGS. NOTE: REFER EXAMPLE 8-16 PAGE 402
2

8.5.2 D-MOSFET Transfer Characteristics

D-MOSFET can operate in both enhancement as well as the depletion mode. It means it can work with both positive and negative VGS. Figure 22 shows the transfer curve for n-channel and p-channel D-MOSFETs. The point on the curve where = 0 corresponds to IDSS. The point where = 0 correponds to VGS(off).
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The curve shows that with positive VGS (n-channel) or negative VGS (p-channel) the channel conduction increases allowing more current through the drain as than IDSS. The same equation of ID as in JFET also applies to D-MOSFET. NOTE: REFER EXAMPLE 8-17 PAGE 403

Figure 22 D-MOSFET transfer curve

8.6 MOSFET BIASING

MOSFET can be biased in three ways. o Voltage-divider bias (For E-MOSFET and D-MOSFET) o Drain-feedback bias (For E-MOSFET and D-MOSFET) o Zero-bias (only for D-MOSFET)

8.6.1 E-MOSFET Bias

The purpose of biasing an E-MOSFET is to make VGS greater than the VGS(th). Figure 23 shows the circuit arrangement for the voltage-divider and drain-feedback bias for an channel E-MOSFET. Equation for the voltage-divider bias are 2 = 1 + 2 = Equation for drain-feedback bias is
=
Figure 23 E-MOSFET bias arrangement

n-

NOTE: REFER EXAMPLE 8-18 & 8-19 PAGE 405 & 406

8.6.2 D-MOSFET Bias

The simplest bias method for D-MOSFET is to set = 0. This enables the AC voltage source to vary above and below this 0V bias point. Equations for the zero-bias are = 0 then = =
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Figure 24 shows an n-channel zero-biased D-MOSFET.

Figure 24 Zero-biased D-MOSFET

NOTE: REFER EXAMPLE 8-20 PAGE 407

Table 1 JFET Formula Sheet

Pinch-Off Voltage Drain Current JFET Forward Transconductance Input Resistance = 1 = 0 0 =

1 2

= = = = = = +

Self-Bias

Voltage-Divider Bias

RS at Q-point is given by = Midpoint Bias is given by = 2 = 3.414 = 2 = 2 = 1 + 2 = = = =

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Ohmic Region

= 1 = = =

Field Effect Transistor

Table 2 MOSFET Formula Sheet

E-MOSFET Drain Current = = 2 1 Voltage Divider Bias 2 = 1 + 2 = Drain Feedback Bias = = Zero-Bias = 0 = =
2

D-MOSFET Drain Current

E-MOSFET Bias

D-MOSFET Bias

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