P.S.G.R.

KRISHNAMMAL COLLEGE FOR WOMEN SUBJECT : DIGITAL PRINCIPLES

SEMESTER - II : SUBJECT DOE : IN08C03 UNIT I 1. ____________________ are used in communication, business transactions, traffic control, space guidance and medical treatment. a. Binary systems c. Digital systems 2. b. Binary systems & Digital systems. d. Binary Digits. CORE : 3

___________________ is a group of binary cells. a. Register b. Records c. Files d. Data

3.

A register with 16 cells can be in one of _______________. a. 3 16 b. 4 16 c. 2 16 d. 16 4

4.

A _______________ Operation is a basic operation in digital systems. a. Record transfer b. Data transfer c. Register transfer d. file transfer

5.

Which of the following is logical operators ________________. a. NOT b. NAND c. AND, OR, d. NOR

6.

A two-valued Boolean algebra is defined on a set of ______________. a. 2 binary bits b. two elements c. 4 bits d. 2n bits

7.

Binary logic consists of ________________. a. Binary systems b. Binary numbers c. binary logics d. Binary & logical operations.

8.

_________________ functions are expressed in terms of AND, OR, NOT a. Algebraic functions d. Relational functions. b. Arithmetic functions c. Boolean functions

9.

Boolean algebra is an algebra that deals with ________________ & logic operations. a. Variables d. Binary systems b. Binary variables c. Digital variables

10.

Exclusive OR functions are very useful in systems requiring __________________ a. Error detection d. Detecting bugs b. Error correction c. Correcting bugs

11.

C.E. Shannon introduced a two-valued Boolean algebra called _____________ a. Switching algebrab. Algebraic function d. Switching Boolean algebra c. Boolean algebra

12.

In a two-valued algebra. the identity elements and one elements of the set are different such as _______________ a. 0 & 0 b. 2 & 1 c. 1 & 0 d. 1 & 1

13.

________________ Represent only a finite number of discrete values. a. Digital signals. d. Digital systems. b. Binary signals c. Electric signals

14.

The voltage levels in a ideal digital circuit will have values of either _______________ or ________________ a. +10 vdc or ovdc d. 6 vdc or 7 vdc b. +5 vdc or ovdc c. + ovdc or + 5 vdc

15.

A _______________ is a switch rat is activated by applying a voltage to a coil. a. Delay b. Relay c. Signal d. Valve.

16.

___________________ is a circuit constructed using numerous transistors and registers. a. digital circuit b. Binary circuit c. Digital integrated circuits d. Integrated circuits.

17.

An AND gate is a _______________ circuit a. Binary circuit b. Binary system c. Digital system d. Digital circuit

18.

A group of ______________ can be connected together to store more than a single logic level. a. flip flop b. registers c. modules d. piles

19.

A system having only two status is said to be _______________ a. Digital b. tri state c. Binary d. Binary state

20.

The simplest _______________ issued as a memory element is called flip flop. a. Digital device d. System device b. Electronic device c. electricity device

21.

The signal such as MASTER RESET or Power on reset will be used to _______________ all storage elements. a. Stop b. Start c. Block d. Initialize

22.

The first bit of binary number is entered in _______________ a. Register b. File c. Flip flop d. Record

23.

Which one of the following is used to initialize the all storage elements? a. STOP b. START c. EXECUTE d. MASTER RESET

24.

The flip-flop's operation depends upon __________________ a. Supply voltage b. Voltage c. DC supply voltage d. V

25.

The product of sums is a Boolean expression containing OR terms called __________________ a. Product terms b. Standard terms c. Sum terms d. Products

UNIT II 1. The Map method, which is used to minimize the Boolean functions and can be described with pictorial form called ______________ a. R-Map 2. b. Pictorial Map c. K Map d. None of these.

The two variable map consists of ___________________ a. Two minterms b. Four minterms c. Five minterms d. Both a and b

3.

A prime implicates are a product term obtained by combining the __________ possible numbers. a. Maximum b. Minimum c. Both a & bd. None of the above.

4.

___________ Variable map needs 16 squares and six variable maps needs 64 squares. a. Four b. Three c. Five d. None of the above

5.

A _________________ is a product form obtained by combining all possibilities of maximum number of squares. a. Even implicant b. Prime implicant c. implicant d. Both b & c

6.

The procedure for obtaining minimized function is product sums follows from the basic properties of ______________ a. Algebraic functions c. Boolean functions b. Mathematical functions d. All the above

7.

The Kainaugh map method is also known as ______________ method. a. K-map b. R-map c. Pictorial map d. None of these

8.

A map is a diagram made up of ____________________ a. Rectangle b. Squares c. Circles d. none of the above

9.

The stimulus that tests the functionality of design is known as __________ a. test stimulus b. Test Bench c. Test Design d. all the above

10.

The _______________ is a building block of varilog. a. Modulus b. Module c. Modular d. None of the above.

11.

Don't care min term is a ________________ whose logical value is not specified. a. Combination of variables c. Combination of modules b. Combination of Data d. Combination of files.

12.

Digital circuits are frequently constructed with _____________ gates. a. NAND gates b. NOR gates c. AND gates d. None of the above.

13.

NAND and NOR gate are used to fabricate the _______________ a. electric components d. all the above. b. fabric components c. electronic components

14.

The ____________ gate is said to be universal gate. a. NOR gate b. OR gate c. NAND gate d. AND gate

15.

To implement the Boolean functions with NAND gates we need logical operation such as __________________ a. NAND, OR, NOR d. None of the above. b. AND, OR c. AND, OR, Complement

16.

HDL is the hardware of ______________.

b.digital systems d.electric systems c.hardware

a. Digital principles systems

17.

The Expansion of HDL is ________________. a. Hardware Description language b. Hardware Description language c. Hardware Designed language d. None of the above.

18.

HDL describes the hardware of digital systems in __________ form. a. Data form b. textual form c. texture form d. None of the above.

19.

HDL is used to represent ___________________ a. Boolean expressions c. logic expressions b. algebraic expressions d. none of the above

20.

HDL is __________________ language. a. Descriptionb. Documentation c. Designing d. Both a & b

21.

The two applications in HDL are a. Description and Documentation b. Simulation and synthesis c. Designing & Description d. None of the above.

22.

Expansion of VHDL is ________________ a. Virtual HDL b. Verilog HDL c. Variable HDL d. both a & b

23.

Logic synthesis producers ____________________ a. Informations d. All the above. b. Instructions c. Databases with instructions

24.

Logic synthesis is also called as a. net list b. byte list c. data list d. None of the above.

25.

A simulator produces the ______________ output a. Writable b. readable c. both a & b UNIT III d. None of the above.

1.

The Logic circuits for digital systems may be _______________ a. Combinational b. Sequencial c. Combinational or sequencial d. none of the above.

2.

_____________________ Circuits consists of input variables, logic gates and output variables. a. logical circuits c. Combinational circuits b. Sequencial circuits d. none of the above

3.

What is the expansion of MSI a. Medium Scale Integration b. Modern Scale Integration c. Module scale Integration d. None of the above.

4.

The combinational circuits that performs the additional of two bits is called __________ a. full adder b. half adder c. both a and b d. none of these

5.

One that performs the addition of three bits is a a. half adder b. full adder c. Binary adder d. all the above

6.

A Binary subtractor is a combinational circuit that performs the ____________ a. arithmetic operators d. Logical operators b. Boolean operators c. Relational operators

7.

The combinational circuit is developed by mean of ______________ a. Decision Tree Design d. None of the above. b. Hioraichiol Design c. both a and b

8.

Half adder circuits needs _____________ and _____________ a. two binary inputs & two binary outputs b. One binary outputs One binary inputs c. Two binary inputs, one binary output d. None of the above.

9.

The logic diagrams of the half adder is implemented by a. exclusive OR and AND gate b. OR Gate c. NAND gate d. NOR gate

10.

Full adder consists of ________________ and __________________ a. 3 inputs and 2 outputs d. 1 input & 2 outputs. b. 1 input & 1 output c. 4 input & 5 outputs

11.

A _______________ digital circuit that produces the arithmetic sum of two binary number. a. Binary adder b. Half adder c. full adder d. None of the above

12. 13.

The subtraction of unsigned binary number can be done by ______________ a. Binary digits b. algebric number c. complements a. Binary adder c. Binary subtractor b. Decimal adder d. none of the above d. none of the above. ________________ requires a minimum of nine inputs & five outputs.

14.

A decimal adder requires a minimum of ________________ a. Nine inputs & five outputs b. 8 inputs & 4 outputs

c. five inputs & nine outputs. 15.

d. 1 outputs & 9 inputs.

The multiplicand is multiplied by each bit of the multiplier starting from the ___________________ a. Compliment bit d. least bit. b. least significant bit c. Significant bit

16.

___________________ is a combinational circuit that compare two numbers A and B that determines their relative magnitude. a. Magnitude comparator c. Magnitude circuits b. Significant comparator d. Significant adder

17.

A binary code of a bits is capable of representing upto ________________ distinct elements of loaded information. a. 2 b. 2 n c. 2 x 1 d. 2 2

18.

A decoder is a combinational circuit that converts binary information of n input liner to a maximum of 2n unique output lines a. A Decoderb. Encoder c. Multiplexer d. Demultiplexer

19.

A __________ is a circuit is that receives information from a single line & directs it to be one of 2 n possible output liner. a. decoder b. encoder c. demultiplexer d. multiplexer

20. 21.

A decoder is a digital circuit that performs the inverse operation of a _______ a. Decoder b. encoder c. Demultiplexer d. Multiplexer A Decoder is a digital circuit not performs the _____________ of a decoder. a. inverse operations c. Boolean operation b. Arithmetic operation d. Algebraic operation.

22.

A ___________________ is a combinational circuit that selects binary information from one of many input lines & directs it to a single output line.

a. Multiplexer 23.

b. demultiplexer

c. encoder

d. decoder

The multiplexer is often labeled as ____________ in a block diagram. a. XUM b. MUX c. MUL d. MWP

24.

The Block Diagram of multiplexer are depicted using ________________ a. Circle shaped b. Wedge shaped c. Square shaped d. Sphere shaped.

25.

The multiplexer is also called as data structure. a. file structure b. Data structure c. Module d. Report structure

UNIT IV 1. The sequential circuit receives binary information from ___________ inputs. a. Internal 2. b. External c. Logical d. Sequential

Synchronization is achieved by a timing device called a _____________ a. Clock generator b. Storage element c. Sequential circuit d. reset state

3. 4.

The storage element used in clocked sequential circuits are called __________ a. Storage device information a. Four b. Three c. Two d. One b. binary storage c. flip flops d. clock pulses. A flip flop is a binary storage device capable of storing __________ bit of

5.

Synchronous circuits that use clock pulses in the inputs of storage element are called ______________ circuits. a. Combinational b. Sequential c. Clock pulses d. Clocked sequential

6.

___________________ Circuit can maintain a binary state indefinitely (as long as power is delivered to the circuit) until directed by an input signal 10 switch states a. Sequential b. Combinational c. flip flop d. Logical

7.

The normal conditions, both inputs of the latch remain at __________ unless the state has to be changed. a. 1 b. 0 c. 2 d. 3

8.

In indeterminate condition occurs when all three inputs are equal to _________ a. 4 b. 2 c. 1 d. 0

9.

The D latch provides a path from input D to the output and for this reason. The circuit is often called a ______________ latch. a. Input b. Output c. Sequential d. Transparent

10.

The state of latch or flip flop is switched by a change in the control input. This momentary change is called a _________ flip flop. a. Logical b. Combinational c. trigger d. Clock pulse

11.

Flip flop circuits are constructed in such a way as to make them operate properly when they are part of a ___________ that employs a common clock. a. Sequential circuit c. Transition circuit b. Combinational circuit d. Clock pulse

12.

The problem with the latch is that it responds to a change in the ______ of a clock pulse. a. Middle b.. Level c. flip flop d. triggered

13.

The construction of a D flip flop with two D latches are ______________

a. Master and slave d. logic and function. 14.

b. Input and output

c. Set or Reset

Very large scale integration circuits contains thousands of gates within __________ package. a. zero b. two c. Three d. One

15.

A state table consists of _____________ section. a. One b. Two c. Three d. four

16.

The first two state tables are obtained by listing all ___________ combination. a. binary b. input c. output d. Sequential

17.

The present state and input columns list the _________ binary combinations. a. 2 b. 4 c. 6 d. 8

18.

The flip flop input equations in terms of the present state and ________ variables. a. Input b. Output c. Control d. binary

19.

The binary values are obtained directly from the four input equations in the manner similar to that obtaining a truth table from a _________ expression. a. Boolean b. Binary c. Input d. Output

20.

The analysis of a sequential circuit with T flip flops follow the same procedure outlined for ______________ flip flop a. D b. T c. RS d. JK

21.

The gated or clocked RS and D flip flops might be considered as ________________

a. Transparent d. Edge triggered 22.

b. Semitransparent

c. Multi transparent

The master is _______________ edge triggered and the slave is __________ edge triggered. a. Input and output c. Middle and end b. Positive and negative d. condition and correction.

23.

While the clock is high, any change in J or K will immediately affect the ___________________ flip flop. a. JK b. Master c. Slave d. RS

24.

The master is set according to J and K while the clock goes __________ a. Low b. high c. Middle d. edge

25.

The content of the master are then shifted into the slave when the clock goes ________________ a. Low b. high c. Middle d. edge

UNIT 5 REGISTERS AND COUNTERS 1. A flip flop is capable of storing _______________ of information. a. One Byte b. 16 bit c. One bit d. 32 bit

2.

The serial output is taken from the output of the flip flop a. Right most flip flop d. JK flip flop b. Left most flip flop c. Gated flip flop

3.

The serial transfer of information from one register to another register is done with a. Parallel register c. Shift register b. Serial register d. Parallel & serial register.

4.

The carry out of the full adder 16 is transferred to a a. RS flip flop c. JK - flip flop b. D flip flop d. T - flip flop

5.

The parallel adder uses registers with parallel load, whereas the serial adder uses a. Shift registers c. Shift register b. Parallel register d. Parallel & serial register.

6.

The Parallel adder is a combinational circuit, whereas the serial adder is a a. logical circuits b. Sequential circuit c. Asynchronous sequential circuitd. Synchronous circuit

7.

Counters are available in two categories : a. BCD & ripple counter b. Binary counter & Asynchronous counter c. Ripple counters & synchronous counters d. Decode counters & presettable counters.

8.

In a downward counter, the binary count with every input count Pulse___________________ a. Incremented by 0 b. incremented & decremented by 1

c. remain same 9.

d. decremented by 1

The sequence of states in a decimal counter is dictated by the binary code used to represent a a. decimal digit b. binary digit c. octal digit d. hexadecimal digit

10.

The logic diagram of a BCD ripple counter using a. T-flip flop c. JK flip flop b. Master flip flop d. Cloked Rs flip flop

11.

A ripple counter is an sequential circuit a. logical circuit c. Synchronous circuit b. Asynchronous circuit d. Sequential circuit

12.

The complementing flip-flop in a binary counter can be either of JK-type or Ttype on the D-type with a. AND gates b. XOR gates c. OR gates d. NAND gates

13. 14.

The circuit of an Up-down binary counter using a. D flip-flop a. Up b. RS flip-flop b. down c. T flip-flop d. Gated flip-flop d.middle When the up and down inputs are both 1, the circuit counts c. both up & down

15.

A BCD counter counts in binary coded decimal from 0000 to 1001 and back to a. 1001 b. 1111 c. 0011 d. 0000

16.

The synchronous counter can be triggered with clock edge. a. only positive b. only negative

c. Either the positive or the negative 17.

d. Neutral

_______________ converts parallel data to serial data a. Serial adder b. full adder c. parallel adder d. half adder

18.

An asynchronous counter in which each flip-flop is triggered by the output of the previous flip-flop is called. a. Asynchronous counter c. Ripple counter b. BCD counter d. Synchronous counter.

19.

VART expanation : a. Unicode Asynchronous receiver transmitter. b. Unicode Asynchronous radar transmitter c. Universal Asynchronous receiver transmitter d. Universal Asynchronous radar transmitter.

20.

A counter has a natural count of a. 2 n + 1 b. 2n c. q n/2 d. 1 q log n

21.

An n-bit binary counter consists of n flip-flops and can count in binary frame a. 0 through 2n + 1 c. 0 through 2n-1 b. 0 through 2 n+1 1 d. 0 through 2n

22.

From the following options which is not a edge - triggered a. D types, b. SR types c. T types d. JK types counter.

23.

An increase in speed of operation can be achieved by use of a a. Synchronous counter c. Asynchronous counter b. BCD counter d. Decode counter.

24.

Are used to generate timing signals to central the sequence of operation in a digital system. a. Register b. Flip-flops c. Circuits d. Counters

25.

A binary counter with a reverse count is called a binary a. Count-up counter c. Count-down counter b. Decode counter d. Counter ripple ANSWERS UNIT - I 1 (C) 2 (A) 3 (C) 4 (A) 5 (C) 6 (C) 7 (D) 8 (C) 9 (B) 10(A) 11 (A) 12 (C) 13 (A) 14 (B) 15 (B) 16 (C) 17 (D) 18 (A) 19 (C) 20 (B) UNIT - II 1 (C) 2 (A) 3 (A) 4 (A) 5 (B) 6 (A) 7 (A) 8 (B) 9 (B) 10(A) 11 (A) 12 (A) 13 (B) 14 (C) 15 (C) 16 (A) 17 (B) 18 (B) 19 (C) 20 (B) 21 (B) 22 (B) 23 (C) 24 (A) 25 (B) 21 (D) 22 (C) 23 (D) 24 (C) 25 (D)

UNIT - III 1 (C) 6 (A) 11 (A) 16 (A) 21 (A)

2 (C) 3 (A) 4 (B) 5 (B)

7 (B) 8 (A) 9 (A) 10(A)

12 (A) 13 (B) 14 (A) 15 (B)

17 (B) 18 (A) 19 (C) 20 (A)

22 (A) 23 (B) 24 (B) 25 (B)

UNIT - IV 1 (B) 2 (A) 3 (C) 4 (D) 5 (D) 6 (C) 7 (B) 8 (C) 9 (D) 10(C) 11 (A) 12 (B) 13 (A) 14 (D) 15 (D) 16 (A) 17 (D) 18 (A) 19 (A) 20 (D) 21 (B) 22 (B) 23 (B) 24 (B) 25 (A)

UNIT - V 1 (C) 2 (A) 3 (C) 4 (B) 5 (A) 6 (B) 7 (C) 8 (D) 9 (A) 10(C) 11 (D) 12 (B) 13 (C) 14 (A) 15 (D) 16 (C) 17 (A) 18 (C) 19 (C) 20 (B) 21 (C) 22 (C) 23 (A) 24 (D) 25 (C)