Activities Compilation (Computer Aided Design of ICs)

ECE241 / COM September 08, 2012

Instructor

Electric and WinSpice Activities

o Inverter Static Characteristics o CMOS Gates Dynamic Characterisitcs (Schematics and Layout) Inverter NAND NOR AND OR

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CMOS Inverter Static Characteristics Inverter Schematic Diagram

Plot of Vout and Vin

At 3.3 V Wn 0.80 m 0.80 m 0.80 m At 5 V Wn 0.80 m 0.80 m 0.80 m

Wp 3.20 m 1.60 m 0.80 m

VOH 3.3000 V 3.3000 V 3.3000 V

VOL VIL 0.29229 V 1.6860 V 0.14086 V 1.2900 V 0.06804 V 0.7420 V

VIH 2.4250 V 2.0210 V 1.5260 V

VTH 1.9360 V 1.6410 V 1.2710 V

Wp 3.20 m 1.60 m 0.80 m

VOH 5.0000 V 5.0000 V 5.0000 V

VOL 4.78162 V 2.13984 V 0.86859 V

VIL 2.8840 V 2.2310 V 1.2610 V

VIH 4.1100 V 3.4090 V 2.4880 V

VTH 3.2240 V 2.7230 V 2.0580 V

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CMOS Gates Dynamic Characteristics Inverter Gate Schematic Diagram Inverter Gate Layout Diagram

Inverter Gate Circuit Test Schematic Diagram

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Plot of Vout and Vin of the Inverter Gate at Transient Analysis

Propagation Delay of the Inverter Gate. Note: Same measurement were obtained on both pre and post layout simulation. CL= 100fFarad Wn 0.80 m 0.80 m 0.80 m Wp 3.20 m 1.60 m 0.80 m PHL 0.6950 ns 0.6500 ns 0.6200 ns PLH 0.3050 ns 0.5350 ns 1.0400 ns fall 1.2150 ns 1.2250 ns 1.2350 ns rise 0.5600 ns 0.8900 ns 1.8700 ns P 0.5000 ns 0.5925 ns 0.8300 ns

CL=500fFarad Wn 0.80 m 0.80 m 0.80 m Wp 3.20 m 1.60 m 0.80 m PHL 2.7900 ns 2.7600 ns 2.7450 ns PLH 0.9500 ns 1.8750 ns 4.3400 ns fall 5.6150 ns 5.6050 ns 5.5950 ns rise 1.7750 ns 3.7500 ns 9.1450 ns P 1.8700 ns 2.3175 ns 3.5425 ns

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NAND Gate Schematic Diagram

NAND Gate Layout Diagram

NAND Gate Circuit Test Schematic Diagram

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Plot of inputs a and b, and output fout of the NAND Gate at Transient Analysis

Propagation Delay of the NAND Gate. Note: Same measurement were obtained on both pre and post layout simulation. CL= 100fFarad Wn 0.80 m 0.80 m 0.80 m Wp 3.20 m 1.60 m 0.80 m PHL 1.0800 ns 1.0200 ns 0.9750 ns PLH 0.2950 ns 0.5250 ns 1.0300 ns fall 1.9600 ns 1.9350 ns 1.9350 ns rise 0.5650 ns 0.8950 ns 1.8700 ns P 0.6875 ns 0.7725 ns 1.0025 ns

CL=500fFarad Wn 0.80 m 0.80 m 0.80 m Wp 3.20 m 1.60 m 0.80 m PHL 4.4000 ns 4.3500 ns 4.3200 ns PLH 0.9450 ns 1.8750 ns 4.3350 ns fall 9.4500 ns 9.4200 ns 9.4050 ns rise 1.7800 ns 3.7550 ns 9.1450 ns P 2.6725 ns 3.1125 ns 4.3275 ns

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NOR Gate Schematic Diagram

NOR Gate Layout Diagram

NOR Gate Circuit Test Schematic Diagram

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Plot of inputs a and b, and output fout of the NOR Gate at Transient Analysis

Propagation Delay of the NOR Gate. Note: Same measurement were obtained on both pre and post layout simulation. CL= 100fFarad Wn 0.80 m 0.80 m 0.80 m Wp 3.20 m 1.60 m 0.80 m PHL 0.3700 ns 0.3500 ns 0.3150 ns PLH 0.4000 ns 0.7700 ns 1.7050 ns fall 0.7350 ns 0.7450 ns 0.7450 ns rise 0.7850 ns 1.4900 ns 3.4800 ns P 0.3850 ns 0.5525 ns 1.0100 ns

CL=500fFarad Wn 0.80 m 0.80 m 0.80 m Wp 3.20 m 1.60 m 0.80 m PHL 1.4300 ns 1.4100 ns 1.4000 ns PLH 1.5450 ns 3.2700 na 7.8450 ns fall 2.8200 ns 2.8250 ns 2.8200 ns rise 3.2600 ns 7.0070 ns 17.235 ns P 1.4875 ns 2.3400 ns 4.6225 ns

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AND Gate Schematic Diagram

AND Gate Layout Diagram

AND Gate Circuit Test Schematic Diagram

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Plot of inputs a and b, and output fout of the AND Gate at Transient Analysis.

Propagation Delay of the AND Gate. Note: Same measurement were obtained on both pre and post layout simulation. CL= 100fFarad Wn 0.80 m 0.80 m 0.80 m Wp 3.20 m 1.60 m 0.80 m PHL 0.5450 ns 0.6100 ns 0.7200 ns PLH 0.5200 ns 0.6150 ns 1.0050 ns fall 1.1550 ns 1.1450 ns 1.1350 ns rise 0.3900 ns 0.7700 ns 1.8450 ns P 0.5325 ns 0.6125 ns 0.8625 ns

CL=500fFarad Wn 0.80 m 0.80 m 0.80 m Wp 3.20 m 1.60 m 0.80 m PHL 2.6800 ns 2.7450 ns 2.8600 ns PLH 1.1450 ns 1.9750 ns 4.3350 ns fall 5.6200 ns 5.6050 ns 5.6000 ns rise 1.7370 ns 3.7750 ns 9.1450 ns P 1.9125 ns 2.3600 ns 3.5975 ns

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OR Gate Schematic Diagram

OR Gate Layout Diagram

OR Gate Circuit Test Schematic Diagram.

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Plot of inputs a and b, and output fout of the OR Gate at Transient Analysis.

Propagation Delay of the OR Gate. Note: Same measurement were obtained on both pre and post layout simulation. CL= 100fFarad Wn 0.80 m 0.80 m 0.80 m Wp 3.20 m 1.60 m 0.80 m PHL 0.6250 ns 0.7050 ns 0.8300 ns PLH 0.2050 ns 0.2750 ns 0.6750 ns fall 1.1450 ns 1.1400 ns 1.1300 ns rise 0.3700 ns 0.7700 ns 1.8400 ns P 0.4150 ns 0.4900 ns 0.7525 ns

CL=500fFarad Wn 0.80 m 0.80 m 0.80 m Wp 3.20 m 1.60 m 0.80 m PHL 2.7650 ns 2.8450 ns 2.9700 ns PLH 0.8350 ns 1.6400 ns 4.0050 ns fall 5.6000 ns 5.5950 ns 5.5950 ns rise 1.7300 ns 3.7500 ns 9.1400 ns P 1.8000 ns 2.2425 ns 3.4875 ns

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VHDL Activities
o o o o o o o Counter (Tutorial) Addition Arithmetic Gray Code to Binary and Binary to Gray Code Count Ones BCD to Decimal and Decimal to BCD Calculator (ALU)

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Counter (Tutorial) Device Diagram:

DIRECTION

1 bit COUNTER 1 bit COUNT_OUT

CLOCK

1 bit

Device Description: The device will have a decremental output (COUNT_OUT) when the DIRECTION is low (0) and will have an incremental output when the DIRECTION is high (1).

VHDL Code: ----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 20:30:41 08/23/2012 -- Design Name: -- Module Name: counter - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM;

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--use UNISIM.VComponents.all; entity counter is Port ( CLOCK : in STD_LOGIC; DIRECTION : in STD_LOGIC; COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); end counter; architecture Behavioral of counter is signal count_int : std_logic_vector (3 downto 0) := "0000"; begin process (CLOCK) begin if CLOCK='1' and CLOCK'event then if DIRECTION='1' then count_int <= count_int + 1; else count_int <= count_int - 1; end if; end if; end process; COUNT_OUT <= count_int; end Behavioral;

Sample Simulation:

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Addition Device Diagram:

INA

8 bits 8 bits ADDITION 1 bit OUTB (OVERFLOW) OUTA

INB 8 bits CLK 1 bit

Device Description: The device will sum two inputs (INA and INB) with 8 bits each. Overflow (OUTB= 1) will happen when the summation is greater than 255 due to OUTA is limited to 8 bits only.

VHDL Code: ----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 20:58:29 08/22/2012 -- Design Name: -- Module Name: Addition - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.

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--library UNISIM; --use UNISIM.VComponents.all; entity Addition is Port ( INA : in STD_LOGIC_VECTOR (7 downto 0); INB : in STD_LOGIC_VECTOR (7 downto 0); CLK : in STD_LOGIC; OUTA : out STD_LOGIC_VECTOR (7 downto 0); OUTB : out STD_LOGIC); end Addition; architecture Behavioral of Addition is begin process (CLK) begin if CLK='1' AND CLK'event then if INA < "1111111"-INB then OUTA <= INA + INB; OUTB <= '0'; else OUTB <= '1'; end if; end if; end process; end Behavioral;

Sample Simulation:

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Arithmetic Device Diagram:

INA INB OPER CLK

8 bits 8 bits 2 bits 1 bit ARITHMETIC 1 bit OUTB (OVERFLOW) 8 bits OUTA

Device Description: The device has a function of addition, subtraction, division and modulo division. Elaboration of the OPER input: 00 ADD (INA + INB) 10 DIV (INA / INB) 01 SUB (INA INB) 11 MODULO DIV (INA mod INB)

OVERFLOW will happen in addition if the sum is greater than 255, in subtraction has a negative value, in division and modulo division if divisor is 0.

VHDL Code: ----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 21:16:33 08/22/2012 -- Design Name: -- Module Name: Arithmetic - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Arithmetic is Port ( INA : in STD_LOGIC_VECTOR (7 downto 0); INB : in STD_LOGIC_VECTOR (7 downto 0); OPER : in STD_LOGIC_VECTOR (1 downto 0); CLK : in STD_LOGIC; OUTA : out STD_LOGIC_VECTOR (7 downto 0); OUTB : out STD_LOGIC); end Arithmetic; architecture Behavioral of Arithmetic is begin process (CLK) variable innA, innB, outtA : integer; begin if CLK='1' AND CLK'event then innA := conv_integer(INA); innB := conv_integer(INB); if OPER="00" then if (INA <= 255 - INB) then OUTA <= INA + INB; OUTB <= '0'; else OUTB <= '1'; end if; elsif OPER="01" then if (INA >= INB) then OUTA <= INA - INB; OUTB <= '0'; else OUTB <= '1'; end if; elsif OPER="10" then if (INB > 0) then OUTA <= conv_std_logic_vector(inna / innb, 8); OUTB <= '0'; else OUTB <= '1';

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end if; elsif OPER="11" then if (INB > 0) then OUTA <= conv_std_logic_vector(inna mod innb, 8); OUTB <= '0'; else OUTB <= '1'; end if; end if; end if; end process; end Behavioral;

Sample Simulation:

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Gray Code to Binary and Binary to Gray Code Device Diagram: INA OPER CLK 16 bits 16 bits 1 bit 1 bit GRAY CODE / BINARY OUTA

Device Description: The device has a capability to convert from gray code to binary (OPER=1) or binary to gray code (OPER=0). VHDL Code: ----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 20:53:42 08/23/2012 -- Design Name: -- Module Name: Gray_to_Binary - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

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entity Gray_to_Binary is Port ( INA : in STD_LOGIC_VECTOR (15 downto 0); OPER : in STD_LOGIC; CLK : in STD_LOGIC; OUTA : out STD_LOGIC_VECTOR (15 downto 0)); end Gray_to_Binary; architecture Behavioral of Gray_to_Binary is begin process (CLK) variable outtA : std_logic_vector (15 downto 0); begin if CLK='1' and CLK'event then OUTA(15) <= INA(15); if OPER='0' then for i in 14 downto 0 loop OUTA(i) <= INA(i+1) XOR INA(i); end loop; else outtA(15) := INA(15); for i in 14 downto 0 loop outtA(i) := outtA(i+1) XOR INA(i); end loop; OUTA <= outtA; end if; end if; end process; end Behavioral;

Sample Simulation:

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Count Ones Device Diagram: 32 bits COUNT ONES

INA

6 bits

OUTA

CLK

1 bit

Device Description: The device has a capability to count 1 in INA input.

VHDL Code: ----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 21:33:02 08/23/2012 -- Design Name: -- Module Name: count_ones - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

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entity count_ones is Port ( INA : in STD_LOGIC_VECTOR (31 downto 0); CLK : in STD_LOGIC; OUTA : out STD_LOGIC_VECTOR (5 downto 0)); end count_ones; architecture Behavioral of count_ones is begin process (CLK) variable count_ones : integer; begin if CLK='1' and CLK'event then count_ones := 0; for i in 0 to 31 loop if INA(i)='1' then count_ones := count_ones + 1; end if; end loop; OUTA <= conv_std_logic_vector (count_ones, 6); end if; end process; end Behavioral;

Sample Simulation:

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BCD Code to Decimal and Decimal to BCD Code Device Diagram:

INA OPER CLK

12 bits 12 bits 1 bit 1 bit BCD / DECIMAL 1 bit OUTA ERR_FLAG

Device Description: The device has capability to convert BCD code to Decimal and Decimal to BCD code. Elaboration of the OPER input: OPER 0 BCD to DECIMAL *ERR_FLAG =1 if input is invalid OPER 1 DECIMAL to BCD *ERR_FLAG=1 if input is greater than 999.

VHDL Code: ----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 22:21:28 08/23/2012 -- Design Name: -- Module Name: BCD_Decimal - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity BCD_Decimal is Port ( INA : in STD_LOGIC_VECTOR (11 downto 0); OPER : in STD_LOGIC; CLK : in STD_LOGIC; OUTA : out STD_LOGIC_VECTOR (11 downto 0); ERR_FLAG : out STD_LOGIC); end BCD_Decimal; architecture Behavioral of BCD_Decimal is begin process (CLK) variable hundreds, tens, ones, inna : integer; variable inv_hundreds, inv_tens, inv_ones : std_logic_vector (11 downto 0); begin if CLK='1' and CLK'event then inna := conv_integer(INA); if OPER='0' then hundreds := conv_integer(INA(11 downto 8))*100; tens :=conv_integer(INA(7 downto 4))*10; ones := conv_integer(INA(3 downto 0)); if hundreds < 1000 AND tens < 100 AND ones < 10 then OUTA <= conv_std_logic_vector(hundreds + tens + ones, 12); ERR_FLAG <= '0'; else ERR_FLAG <= '1'; end if; else if (INA <= 999) then OUTA(11 downto 8) <= conv_std_logic_vector(inna / 100, 4); OUTA(7 downto 4) <= conv_std_logic_vector((inna mod 100) / 10, 4); OUTA(3 downto 0) <= conv_std_logic_vector((inna mod 10), 4); ERR_FLAG <= '0'; else ERR_FLAG <= '1'; end if; end if; end if;

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end process; end Behavioral; Sample Simulation:

Note: To easily check the BCD code to Decimal conversion, INA is in hexadecimal mode while OUTA is in decimal (unsigned) mode. Please see the dash-dot rectangular box in color maroon.

Note: To easily check the Decimal to BCD code conversion, INA is in decimal (unsigned) mode while OUTA is in hexadecimal mode. Please see the dash-dot rectangular box in color maroon.

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Calculator (Simple ALU) Device Diagram:

INA INB OPER CLK

16 bits 16 bits 4 bits 1 bit ALU 1 bit ERROR_INDICATOR 16 bits OUTA

Device Description: The device has a functionality of a calculator (simple ALU). Elaboration of the OPER (0 to 13) input: 0 INA + INB 1 INA INB 2 INB INA 3 INA / INB 4 INB / INA 5 INA mod INB 6 INB mod INA Error If: Divide by zero Output is more than 16 bits Output is negative VHDL Code:
----------------------------------------------------------------------------------

7 INA INB 8 INA + INB 9 INA + INB 10 INA INB 11 INA + INB 12 INA 13 INB

-- Company: -- Engineer: --- Create Date: 17:01:15 08/25/2012 -- Design Name: -- Module Name: Calculator - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision:

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-- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Calculator is Port ( INA : in STD_LOGIC_VECTOR (15 downto 0); INB : in STD_LOGIC_VECTOR (15 downto 0); OPER : in STD_LOGIC_VECTOR (4 downto 0); CLK : in STD_LOGIC; OUTA : out STD_LOGIC_VECTOR (15 downto 0); ERROR_INDICATOR : out STD_LOGIC); end Calculator; architecture Behavioral of Calculator is begin process (CLK) variable ina_int, inb_int : integer; begin if CLK='1' and CLK'event then ina_int := conv_integer(INA); inb_int := conv_integer(INB); if OPER="0000" then if (INA <= 65535 - INB) then OUTA <= INA + INB; ERROR_INDICATOR <= '0'; else ERROR_INDICATOR <= '1'; end if; elsif OPER="0001" then if (INA > INB) then OUTA <= INA - INB;

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ERROR_INDICATOR <= '0'; else ERROR_INDICATOR <= '1'; end if; elsif OPER="0010" then if (INB < INA) then OUTA <= INB - INA; ERROR_INDICATOR <= '0'; else ERROR_INDICATOR <= '1'; end if; elsif OPER="0011" then if (INB /=0) then OUTA <= CONV_STD_LOGIC_VECTOR(ina_int / inb_int, 16); ERROR_INDICATOR <='0'; else ERROR_INDICATOR <='1'; end if; elsif OPER="0100" then if (INA /=0) then OUTA <= CONV_STD_LOGIC_VECTOR(inb_int / ina_int, 16); ERROR_INDICATOR <='0'; else ERROR_INDICATOR <='1'; end if; elsif OPER="0101" then if (INB /=0) then OUTA <= CONV_STD_LOGIC_VECTOR(ina_int mod inb_int, 16); ERROR_INDICATOR <='0'; else ERROR_INDICATOR <='1'; end if; elsif OPER="0110" then if (INB /=0) then OUTA <= CONV_STD_LOGIC_VECTOR(inb_int mod ina_int, 16); ERROR_INDICATOR <='0'; else ERROR_INDICATOR <='1'; end if; elsif OPER="0111" then OUTA <= INA AND INB; ERROR_INDICATOR <='0'; elsif OPER="1000" then OUTA <= INA OR INB; ERROR_INDICATOR <='0'; elsif OPER="1001" then

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OUTA <= INA XOR INB; ERROR_INDICATOR <='0'; elsif OPER="1010" then OUTA <= NOT (INA AND INB); ERROR_INDICATOR <='0'; elsif OPER="1011" then OUTA <= NOT (INA OR INB); ERROR_INDICATOR <='0'; elsif OPER="1100" then OUTA <= NOT INA; ERROR_INDICATOR <= '0'; elsif OPER="1101" then OUTA <= NOT INB; ERROR_INDICATOR <= '0'; else ERROR_INDICATOR <= '1'; end if; end if; end process; end Behavioral; Sample Simulation:

OPER 1 to 6 are the arithmetic part and sample simulation showed the validity of each data plus the error_indicator.

OPER 7 to 10 are some of the logical part and sample simulation showed the validity of each data.

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OPER 11 to 13 are some of the logical part and sample simulation showed the validity of each data. Error_indicator happened at OPER 14 and 15 due to it did have neither an arithmetic nor logical operation.

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TSPICE Activities
o Inverter o NAND

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Inverter Netlist: * Inverter .model mn nmos (level=1 vto=0.8 kp=50u lambda=0) .model mp pmos (level=1 vto=-0.9 kp=20u lambda=0) vdd 1 0 dc 3.3 vin 2 0 dc 3.3 m1 1 2 3 1 mp l=0.35u w=1.6u m2 3 2 0 0 mn l=0.35u w=0.8u .dc vin 0 3.3 0.01 .print v(3) v(2) .end

Input and Output Waveform:

Input

Output

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NAND Netlist: *NAND .model mn nmos (level=1 vto=0.8 kp=50u lambda=0) .model mp pmos (level=1 vto=-0.9 kp=20u lambda=0) M1 D1 INA 0 0 mn l=0.35u w=0.8u M2 OUT INB D1 0 mn l=0.35u w=0.8u M3 OUT INA VDD VDD mp l=0.35u w=1.60u M4 OUT INB VDD VDD mp l=0.35u w=1.60u C1 OUT 0 100f VDD VDD 0 DC 3.3 VINA INA 0 PULSE(0 3.3 0 1n 1n 50n 100n) VINB INB 0 PULSE(0 3.3 0 1n 1n 25n 50n) .tran 5p 100n .print v(INA) v(INB) v(OUT)

Input and Output Waveform:

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