Copyright

by
RAVI GOURAPURA MURUGESHAPPA
2010


The Report Committee for RAVI GOURAPURA MURUGESHAPPA
Certifies that this is the approved version of the following report:


A low-voltage, low-power CMOS Bandgap Reference








APPROVED BY
SUPERVISING COMMITTEE:


Supervisor:

T.R. Viswanathan
Arjang Hassibi


A low-voltage, low-power CMOS Bandgap Reference


by
RAVI GOURAPURA MURUGESHAPPA B.E, M.Tech


Report
Presented to the Faculty of the Graduate School of
The University of Texas at Austin
in Partial Fulfillment
of the Requirements
for the Degree of

Master of Science in Engineering


The University of Texas at Austin
May 2010

iv
Acknowledgements

First and Foremost, I would like to acknowledge the help from my supervisor, Prof. T.R.
Viswanathan, who had inspired me to look at circuits from a different perspective and
obliged to have many discussions on circuits.
I would also like to acknowledge the help of Mr. Ajay Taparia, Ph.D student at UT,
Dallas, in understanding the working of this circuit as well as during circuit simulations.
I am deeply indebted to many of my colleagues at Silicon Laboratories, Inc., Austin,
Texas, who have helped me to understand IC design from bottoms up and I am grateful to
all of them.











28
th
April 2010
v
Abstract

A low-power, low-voltage CMOS Bandgap Reference



RAVI G MURUGESHAPPA, MSE
The University of Texas at Austin, 2010

Supervisor: T.R.VISWANATHAN
Co-supervisor: ARJANG HASSIBI

Abstract: Bandgap reference circuits are used in a host of analog, digital, and
mixed-signal systems to establish an accurate voltage reference for the entire IC. The
most used CMOS implementation for voltage references is the bandgap circuit due to its
high predictability, and low dependence of the supply voltage and temperature of
operation.

This work studies a CMOS implementation of a resistor-less bandgap reference,
which consumes low power. The most relevant and traditional approaches usually
employed to implement bandgap voltage references are investigated. The impact of
process, power-supply, load and temperature variations has been analyzed and simulated.
The functionality of critical components of the circuit has been verified through chip
implementation.
vi
Table of Contents
THE REPORT COMMITTEE FOR RAVI GOURAPURA MURUGESHAPPA II
LIST OF TABLES VIII
LIST OF FIGURES IX
CHAPTER 1 1
INTRODUCTION 1
1.1 The Basic Bandgap Reference ...........................................................................1
1.2 System Implications ........................................................................................4
1.3 Error Sources .....................................................................................................5
CHAPTER 2 7
WORKING PRINCIPLE OF THE CIRCUIT 7
2.1. Basic Function ..................................................................................................7
2.2. Concept .............................................................................................................7
2.3 Chip Implementation .......................................................................................12
CHAPTER 3 14
SIMULATIONS AND MEASUREMENT RESULTS 14
3.1 Simulation Results .........................................................................................14
3.1.1 Variation of bandgap voltage with respect to trim ...............................14
3.1.2 PSRR (Power Supply Rejection Ratio).......................................18
3.1.3 Stability analysis ..........................................................................19
3.1.4Start-up behavior ..................................................................................20
3.1.5 Power Consumption ....................................................................21
vii
3.2 Measurement Results .......................................................................................21
CHAPTER 4 23
CONCLUSIONS 23
4.1 Error due to V
Threshold
devices ...........................................................................23
4.2 V
PTAT
generating device mismatch error ........................................................23
4.3 Process induced errors ....................................................................................24
4.4 Package Shift .................................................................................................24
4.5 Load Variations ..............................................................................................25
4.6 Future work ....................................................................................................25
REFERENCES 26
VITA 27
viii
List of Tables
Table 3.1 Bandgap reference voltage measured for four different chips 21
ix
List of Figures
Fig 1.1: Temperature behavior of typical bandgap reference circuit. 2
Figure 1.2: Building Block of Bandgap Reference circuits 4
Fig 2.1: Basic scheme for generating PTAT and CTAT voltages 8
Fig 2.2: PTAT voltage generation 9
Figure 3.1: Variation of bandgap voltage with respect to trim at nominal
process parameters 14
Figure 3.2: Variation of bandgap voltage with respect to temperature at 15
fast-fast process corner 15
Figure 3.3: Variation of bandgap voltage at slow-slow process corner 16
Fig 3.4 Variation of Bandgap voltage at slow-fast process corner 17
Fig 3.5 Variation of Bandgap voltage at fast-slow process corner 17
Fig 3.6 Power supply rejection ratio at various CLoad 18
Fig 3.7 Gain and Phase for the outer loop 19
Fig 3.8 Gain and phase for the inner local loop 20
Fig 3.9 Start-up behavior of bandgap reference output 20
Figure 3.10 Bandgap Reference output for four different chips 22

1
CHAPTER 1
INTRODUCTION
Many Analog circuits require voltage references such as A/D and D/A converters. A
voltage reference must be, inherently, well defined and insensitive to temperature, power
supply and load variations. The bandgap voltage reference is required to exhibit both high
power supply rejection and low temperature coefficient. However, IC design is now
predominated by low power, low voltage objectives, making CMOS the technology of
choice.

1.1 The Basic Bandgap Reference
An accurate voltage or current reference is an important component of most integrated
circuits. As its name suggests, a reference establishes a stable point that the rest of the
circuits in the system can utilize for generating reliable and predictable results. The
accuracy of the reference directly impacts and often dictates the overall performance of
the system.

The circuit operates on the principle of adding a voltage that decreases linearly with
temperature to one that increases linearly with temperature to produce a reference voltage
that is stable with respect to temperature to the first order. Fig. 1.1 shows the reference
circuit which adds PTAT and CTAT voltages.


Fig 1.1: Temperature behavior of typical bandgap reference circuit.

The Brokaw cell shown in Fig 1.2 forms the building block of most bandgap references.
Same amount of current is passed through both transistors Q1 and Q2 by the current
mirror. The base-emitter drop of transistors voltages Q1 and Q2 are proportional to the
size of transistors Q1 and Q2. The difference in their base-emitter voltages is impressed
upon resistor R, which produces a PTAT current and consequently a PTAT voltage V
PTAT

across resistor R
PTAT
as given in equation 1.1
I
BL
= I
1
ln
Ic
]
S
Acu
(1.1)

I
P1A1
= I
C2
= I
C1
=
v
T
R
ln[C
I
C1
I
C2
=
v
T
R
lnC (1.2)
and

2
3
This voltage having a positive temperature coefficient, is then added to the base-emitter
voltage of Q1, which has a negative temperature coefficient to generate the temperature
stable reference voltage V
REF
, which is given by

V
REF
= V
CTAT
+ V
PTAT
= V
BE1
+ 2I
PTAT
R
PTAT
(1.3)
Or
I
RLP
= I
BL1
+ 2I
1
ln(C)
R
PTAT
R
(1.4)

One of the possible solution of Equation (1.2) occurs when both I
C1
and I
C2
are zero, or
in other words, the bandgap reference is in a zero-current or off state. The circuit can
be pulled out of this state if a perturbation of sufficient energy is applied which is why
most of bandgap circuits require a start-up block that supply this energy and thereby
prevent the reference from settling into this undesired yet stable state. In the circuit of Fig
1.2, the start-up block draws current from the low impedance node when the circuit is in
undesired off state. This current is then mirrored and forced into the collector of Q1
and the circuit eventually settles into the desired stable state.



Figure 1.2: Building Block of Bandgap Reference circuits

1.2 System Implications
The demand for higher levels of integration has led to smaller process geometries and the
fabrication of digital, RF and analog circuits on the same substrate to deliver solutions
that are multi-functional. Since System-on-chip (SoC) solutions are always cost
conscious, they demand references that have a high degree of precision while incurring
4
5
minimal manufacturing costs. The dc accuracy of bandgap references is particularly
sensitive to process variations and package and process induced mismatches whose
adverse effects on accuracy varies across devices, wafers, impacting each device
uniquely. As a result, trimming (i.e., tweaking) the output voltage is necessary to produce
predictable, and therefore reliable, reference values. Most state-of-art bandgap references
demand very high accuracy of 1%, making the task of obtaining high initial accuracy
challenging.
Cost conscious SoCs are also increasingly using standard CMOS processes that require
fewer masking steps, and hence incur lower costs, than their BiCMOS counterparts. This
trend is forcing designers to build critical analog blocks, including voltage references, in
the same cost-effective CMOS technologies. Given the low breakdown voltages of this
high resolution CMOS technologies, SoC solutions must survive low supply voltages and
generate low voltage references with high precision. In other words, the reference
designed in these state-of-the-art CMOS processes must incur low dropout voltages.

1.3 Error Sources
A number of factors degrade the accuracy of CMOS bandgap reference circuits,
including process variations and mismatch, package stresses, power-supply fluctuations,
load variations and temperature changes. E rrors in the bandgap reference voltage and
its temperature coefficient arise from non-idealities in the values and matching resistors
and transistors in the circuit. For example, mismatch between resistors R and R
PTAT
is a
source of PTAT error. Process variations can lead to error sources due to deviation of the
resistor values from their desired values. Deviation of resistor values is a CTAT error.
6
The temperature drifts of resistors R and R
PTAT
also deteriorate the performance of
reference. Since the PTAT term of the reference voltage involves the ratio of R and
R
PTAT
, it is unaffected by the temperature drift of resistors, as their temperature
coefficients track one another. However, the V
BE2
term is affected since I
PTAT
is affected.
The error is a non-PTAT error.
Transistor mismatch errors result from a deviation in the desired ratio of the areas of
transistors Q1 and Q2. The mismatch in the transistors adversely affects the PTAT
current. The error due to transistor mismatch is a PTAT error.
The current-mirror mismatch arises from the deviation in the required W/L ratio of the
mirroring MOS transistors, or, equivalently, a mismatch in the areas of BJT transistors.
This error has PTAT dependence.
Resistor tolerance and current-mirror mismatch are the largest sources of error in a
bandgap circuit and, hence, close attention must be paid to maximize the accuracy of the
resistors and to decrease the mismatch of mirror devices by appropriately designing
device dimensions, layout geometries and layout techniques. Transistor and resistor,
mismatch and tolerance errors can be trimmed out by tu ning a PTAT trimming resistor.
However resistor temperature coefficient errors cannot be trimmed.

One of the aspects that are explored in the current study is to have a bandgap reference
circuit without using any resistors.


7
CHAPTER 2
Working Principle of the Circuit

2.1. Basic Function
Bandgap references add the forward bias voltage across a p-n diode with a voltage that is
proportional to absolute temperature (PTAT) to produce an output that is insensitive to
changes in temperature. The relative weighting of the voltages added is usually adjusted
by trimming the ratio of two resistors. In standard digital CMOS technologies, models for
the resistors may not be available or reliable. Also, the length and area of the required
resistors not only increases the cost but also the susceptibility of the reference operation
to substrate noise coupling. When the supply voltage and power dissipation are to be
minimized the design runs into problems. Process variation has to be trimmed out and
PSRR specification is difficult to achieve. One way to overcome this problem is not to
use resistors. The circuit described here is based on the MOS transistors biased in
saturation or cut-off. The devices biased in saturation operate in strong inversion, for
which accurate device models are usually available, simplifying the design process.
2.2. Concept
To produce a temperature-insensitive output, the bandgap reference applies a
temperature-independent gain M to the difference between the forward bias voltages
across two diodes V
D
. The process is explained below. Figure 2.1 shows the building
block of generating a PTAT and CTAT voltage.
V
DD
V
SS
10
1
10
1
+ v
T
ln ( 100 ) -
-
+
V
BE
V
PTAT
V
CTAT
Current Density Ratio = 100
Small Current
Big Diode
Big Current
Small Diode

Fig 2.1: Basic scheme for generating PTAT and CTAT voltages
Traditional approach is to amplify V
PTAT
and add to V
CTAT.
The V
BE
(V
PTAT
) is
approximately given by V
T
ln 100, which is equal to 115mV. The PTAT voltage is
amplified by a gain 4 and when added to VBE 600mV will give the Bandgap
Voltage of1.1V. The scaling operation is obtained by using ratioed transistors together
with translinear function technique. Figure 2.2 shows a circuit using source follower as a
trans-linear transconductance. The circuit consists of super source follower using
transistors M1 and M2 which gives very low output resistance approximately given by
01 2 1
1
r g g
Rout
m m

=



8
I
B
V
DD
V
SS
i
Tiny
I
small I
big
V
PTAT
+ -
i = f ( V
PTAT
)
i
D1
D2
+
-
V
BE1
+
-
V
BE2
M1
M2
M3

Fig 2.2: PTAT voltage generation
Using Kirchhoffs voltage law we can write as
V
BE1
+ VGS1- VGS3 V
BE2
= 0
V
BE1
- V
BE2
= VGS3 VGS1
V
BE1
V
BE2
= V
TH3
+V
DSAT3
-(V
TH1
+V
DSAT1
) (2.1)
But transistor M1 is a much bigger device as compared to M3. Therefore, V
DSAT1
of
transistor M1 is small and can be neglected to the first order. Therefore Eq 2.1 can be
simplified as
V
BE1
- V
BE2
= V
DSAT3
(2.2)
as V
TH3
and V
TH1
are equal to the first order and dependent only the process.
From Eq 2.2, it is clear that V
DSAT3
gives us a good representation of PTAT voltage. As
we know, there is a direct relationship between V
DSAT
of a transistor and the current
through the transistor given by
V
DSAT
= K I
DS
.
9
To use V
BE
further, we need to amplify the V
DSAT3
by a factor 4. This can be
reliably achieved by using the current I
DS
through the transistor M3 and replicating it
using current mirror stages with a gain. Figure 2.3 explains the way this transformation is
achieved.

I
B
V
DD
V
SS
i
Tiny
I
small I
big
V
PTAT
+ -
i = f ( V
PTAT
)
i
= V
BE
+ V
PTAT
I
big
+i
Tiny
V
SS
V
DD
?V
PTAT
-
+
V
BE
-
+
V
BG
-
ni
M1
M2
M3
M4
M5
M6

Figure 2.3: Amplification of PTAT and addition with CTAT

The transistor M4 is chosen to be a device with large size to make its V
DSAT4
to be as
small as possible and can be neglected. The transistor M5 with current source load
whose current is n times the current through transistor M3. The current amplification
using a current mirror stage would give us the VGS of transistor M5 with an
amplification factor . Calculating the voltages around the loop consisting of diode,
transistor M4 and transistor M5 would give us the voltage at the source of transistor M5
as shown in equation 2.3 below.
10

V
BE
(V
TH4
+V
DSAT4
) +V
TH5
+ V
PTAT
(2.3)

Since V
DSAT4
is negligible and V
TH4
and V
TH5
are equal, the voltage available at the
output is equal to V
BE
+ V
PTAT
. The transistors M5 and M6 are connected as super-
source follower output stage to give low output resistance thereby making the circuit a
nice voltage source.

The final circuit with all the above explained features is shown in
Fig 2.4.

V
SS
V
DD
V
BE1 V
BE2
V
BE
+ kV
PTAT
R
S
V
BE1
M1
M2
M3
M4
Q2
MF
Q1
M5
M10
MC
M11
M12
M13
M14
M9
M7
M6
M8
M15

Figure 2.4: Complete schematic for Bandgap circuit

11
The V
PTAT
of transistor M2 is replicated by using current mirror stage which includes
transistors M4 and M3 and subsequently by other current mirror stages which includes
transistors M5, MC, M10, M11, M12, M13 and transistor M14.

2.3 Chip Implementation
The bandgap reference circuit was implemented in 0.18um silicon process technology.
Due care was taken in the layout to implement CMOS diodes to make both diodes
symmetric and reduce mismatch errors. The layout of current mirror stage transistors is
not optimal and could have been further improved. The trimming option is provided as a
current reduction trim, with transistor M11 (see Fig 2.4) size to be trimmed down from a
maximum multiplier of 90 to a minimum size of 80 in steps of 1. The trimming option
provided is limited in scope and is not well centered. The Fig 2.5 shows the trimming
circuit implemented.

M4
I
VDD
M2 M11
I
I
OUT Metal Fuse Metal Fuse


Fig 2.5 Trim circuit implemented on the chip
12
13
Trim circuit is composed of many transistors connected in parallel. Fig 2.5 only shows
two devices for simplicity. Through the connection of metal fuses, the number of
transistors in parallel is 90, and to trim the metal fuses have to be blown. Using this
method, it is possible to reduce current gain and thereby increase CTAT gain.








CHAPTER 3
Simulations and Measurement Results

3.1 Simulation Results

3.1.1 Variation of bandgap voltage with respect to trim
The bandgap reference circuit is simulated at nominal as well as at process corners.


Figure 3.1: Variation of bandgap voltage with respect to trim at nominal process
parameters

14
Figure 3.1 shows that at minimum current reduction trim, the CTAT is dominating and as
the current gain increases from its minimum value to its minimum, the PTAT becomes
more dominating.

Figure 3.2 shows the variation of bandgap voltage with respect to temperature at fast-fast
(fnfp) process corner at three trim options.



Figure 3.2: Variation of bandgap voltage with respect to temperature at
fast-fast process corner

At fast-fast process corner, the CTAT dominates for all trim options. The variation is
worse at low current gain trim.
15

The simulations at slow-slow process corner are shown in Fig 3.3. The variation in
bandgap voltage shows that PTAT dominates during this phase.


Figure 3.3: Variation of bandgap voltage at slow-slow process corner

The simulations at slow-fast and fast-low process corners are shown in Fig 3.4 and Fig
3.5 respectively.
16

Fig 3.4 Variation of Bandgap voltage at slow-fast process corner


Fig 3.5 Variation of Bandgap voltage at fast-slow process corner
17
3.1.2 PSRR (Power Supply Rejection Ratio)

The simulation results for PSRR are shown in Fig 3.4 for various values of load capacitor
(CLoad). At low frequencies the PSRR is about -40dB. At around 36MHz input
frequency the PSRR gradually decreases and has a resonant frequency at 82MHz. The
PSRR improves further with increasing load capacitor.





Fig 3.6 Power supply rejection ratio at various CLoad


18
3.1.3 Stability analysis

Figure 3.5 and 3.6 shows the simulation results when breaking the loop at two different
points. Since the circuit does have multiple feedback loops consisting of current mirror
stages, it is difficult to find a single point to break the loop. Therefore, stability analysis is
performed at local level for the super-source follower stage and at another point which is
analyzed as more global. At the global level, the simulation results show that the circuit is
unconditionally stable. The circuit is also stable at the local level.


Fig 3.7 Gain and Phase for the outer loop

19

Fig 3.8 Gain and phase for the inner local loop
3.1.4 Start-up behavior


Fig 3.9 Start-up behavior of bandgap reference output
20
3.1.5 Power Consumption
From simulations the power consumption is measured at 21uW (12uA at 1.8V).

3.2 Measurement Results

Temperature
degCelsius
Chip1 Chip2 Chip3 Chip4
0 1.13151 1.13 1.144 1.16
10 1.13151 1.13 1.145 1.161
20 1.1298 1.1287 1.143 1.159
25 1.127 1.1268 1.1428 1.157
30 1.1265 1.1247 1.1416 1.1556
40 1.12137 1.1224 1.139 1.1533
50 1.1186 1.117 1.1357 1.1494
60 1.1153 1.1103 1.1318 1.1454
70 1.1108 1.1079 1.13 1.139
80 1.098 1.102 1.1267 1.1346
90 1.093 1.098 1.1221 1.127
100 1.086 1.0935 1.117 1.12
Vbandgap(Volts)

Table 3.1 Bandgap reference voltage measured for four different chips
21
1.08
1.09
1.1
1.11
1.12
1.13
1.14
1.15
1.16
1.17
0 20 40 60 80 100 120
V
b
a
n
d
g
a
p

(
v
o
l
t
s
)
Temperature(degCel)
BandgapVoltagevsTemperature
Chip1
Chip2
Chip3
Chip4

Figure 3.10 Bandgap Reference output for four different chips

It is clear from measurement results that the bandgap reference temperature coefficient is
more than expected and the shape of the curve matches to some extent to that of
simulation results at fast-fast process corner.






22
23


CHAPTER 4
Conclusions

This report has tried to analyze a low-voltage, low-power bandgap reference based only
on CMOS. This chapter discusses various strategies for improvements that can be made
to the existing circuit.

4.1 Error due to V
Threshold
devices
As seen in chapter 2, and referring to Fig 2.3, the devices M1 and M4 are V
Threshold

generating devices. The size of these transistors is increased to ensure that V
DSAT
of these
devices are negligible. In the actual implementation, the size of these transistors is not big
enough to totally neglect their V
DSAT
. The measured V
DSAT
of these devices are 59mV
and 48mV which are still comparable to their threshold voltages.

4.2 V
PTAT
generating device mismatch error
Devices M3 and M5 (Fig 2.3) are minimum sized devices responsible for generating
V
PTAT
. The mismatch error between these two transistors can cause error in the
amplification factor in V
PTAT
. The current mirror mismatch arises from the deviation in
the required W/L ratio of the mirroring MOS transistors. The error due to current mirror
mismatch is normally PTAT type. Also the layout of these two transistors is not
symmetrical and this can lead to the mirrored current to be significantly different from
24
reference current. The parameters which are affected by mismatch errors are threshold
voltage (V
TH
), transconductance parameter, drain to source voltages of mirrored
transistors as well as their channel length modulation effects. Matching performance can
be improved by increasing the active area and overdrive voltage (V
DSAT
) of the MOS
devices. But increasing the active device area incurs the penalty of higher parasitic
capacitance at the mirror nodes. This ultimately leads to a reduction in the references
bandwidth which lowers the ability to respond to line and load fluctuations and degrades
its ac accuracy.

4.3 Process induced errors
Modern CMOS processes exacerbates the challenges to achieving high accuracy against
process variations, since MOS transistors exhibit higher mismatch than bipolar transistors
and high PSRR, since these processes typically exhibit low breakdown voltage and
consequently require low supply voltages, making the use of conventional cascodes
difficult to adopt. The spread in the base-emitter voltage of the bipolar transistor used to
generate the CTAT component can be a considerable source of error because it directly
translates to an error in reference voltage and is dictated entirely by the process used.

4.4 Package Shift

The Package shift is the deviation of the reference voltage of a packaged bandgap circuit
from its original, unpackaged value. It is an important source of error since it occurs after
the unit has been packaged and hence may deteriorate the accuracy of a reference that has
been precision trimmed at the wafer level. Package shift is caused by stresses imposed by
25
the package on the die surface. These mechanical stresses create parametric shifts in
bipolar transistors, MOS devices by altering carrier distributions and mobility.

4.5 Load Variations
Though regulated references do not typically source load currents in excess of 10mA,
they need to exhibit low output impedance to shunt high frequency noise that propagates
onto their output via parasitic coupling capacitance. In the present circuit, the output
impedance is kept very low by using super-source follower stage at the node.

4.6 Future work

The present implementation of the circuit has the trimming circuit which is not centered
and would certainly need to have a well centered implementation. The temperature
coefficient of the bandgap reference (in ppm/C) is more than expected and cannot be
trimmed out.









26
REFERENCES
1. Brito,J.P.M., Hamilton,K., Sergio,B. A Design Methodology for Matching
Improvement in Bandgap References IEEE Intl Symposium on Quality
Electronic Design, ISQED 8, 2007.
2. Gupta,V., Rincon-Mora,G.A. Predicting and designing for the impact of process
variations and mismatch on the trim range and yield of bandgap reference IEEE
Intl Symposium on Quality Electronic Design, ISQED , 2005
3. Song,B.S., Gray,P.R.,. A Precision Curvature-Compensated CMOS Bandgap
Reference IEEE Journal of Solid-State Cicuits, December,1983
4. Sengupta.S., Carastro,L., Allen,P.E. Design Considerations in Bandgap
References Over Process Variations IEEE Intl Symposium on circuits and
systems, 2007
5. Mok Philip.K.T., Leung,K.N., Design Considerations of Recent Advanced Low-
Voltage Low-Temperature-coefficient CMOS Bandgap Voltage Reference
IEEE Custom Integrated Circuits Conference, 2004
6. Hoon.S.K., Chen,J., Maloberti,F. Improved Bandgap Reference with Power
Supply Rejection IEEE Intl Symposium on circuits and systems, 2002
7. Buck.A.E., McDonald,C.L., Lewis,S.H.,Viswanathan,T.R. A CMOS Bandgap
Reference Without Resistors IEEE Journal of Solid State Circuits, 2002
8. Perry,R.T., Lewis,S.H., Brokaw,A.P., Viswanathan,T.R. A 1.4V Supply CMOS
Fractional Bandgap Reference, IEEE journal of Solid State Circuits, October
2007.


27
VITA
RAVI GOURAPURA MURUGESHAPPA

Ravi Gourapura Murugeshappa was born in Jog Falls, Karnataka, India in 1966.
He obtained his B.E. degree from Mangalore University, Karnataka, India in
1988. He began his graduate studies at Indian Institute of Technology, Kharagpur
in June, 1991 and obtained M.Tech degree in Electrical Engineering in January,
1993, with specialization in Power Electronics and Machine Drives. He has
worked in Philips Electronics, Singapore, as an R&D engineer from 1996 till
2000 and in Philips Electronics, Power Management group, Eindhoven,
Netherlands, from 1999 to 2001. He is working at Silicon Laboratories, Austin,
Texas since 2004. His area of interest is in the area of Power management IC
design, embedded power control and Analog IC design.

Contact Information: meeravi2000@yahoo.com






This report is typed by the author