ELEC6016 Clock Gating Laboratory Notes

CLOCK GATING USING SYNOPSYS DESIGN COMPILER

Aims: 1. To understand the principle of clock gating 2. To gain experience in using Synopsys Design Compiler to implement clock gating in RTL design 3. To demonstrate the benefit of clock gating in reducing power consumption Procedure: 1. Fig. 1 (a) shows the block diagram of the design used to incorporate clock-gating. The functionality of the design is covered in your lecture notes. The key functionality is: output only one 16 bit data from an incoming data stream by generating a single-cycle active-high enable signal generated using a counter and an enable generator module. (Fig. 1(b) shows the functionality, generated using Modelsim). 2. Download the zipped RTL files (written in VHDL format) of the blocks (as shown in Fig. 1) from the following link: https://secure.ecs.soton.ac.uk/notes/elec6016/lpd/clock-gating-lab.zip and copy to /home/[user]/clockgating/ ([user] is your user name). If the clockgating directory does not exist, type mkdir clockgating in command prompt, followed by cd clockgating command to change to newly created clockgating directory. The following files are included: (a) counter8.vhd creates a counter counting from 0 to 7 (b) en_gen.vhd creates one single-cycle active-high enable signal when counter value reaches 7. (See Fig. 1 (a) and (b)). (c) flop7.vhd - outputs one 16 bit data from the incoming data-stream when the enable signal is high. (d) top.vhd top design combining above three modules.

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Fig. 1 (a)

Fig. 1(b) ASIC SYNTHESIS USING SYNOPSYS DESIGN COMPILER (DC) PART-A : SYNTHESIZE WITHOUT CLOCK-GATING 1. From your Windows work-station connect to hind or esdcad5 UNIX server using NX client (Click Configure, enter hind.ecs.soton.ac.uk or esdcad5.ecs.soton.ac.uk as host) with your user name and password. 2. Right-click on UNIX desktop, click on Open Terminal. 3. In UNIX terminal command prompt type the following: >> source /home/esdcad/scripts/esd_tcshrc >> source /home/esdcad/scripts/synopsys_linux_galaxy_C-2009.06 >> source /home/esdcad/scripts/license 4. In UNIX command prompt type the following: dc_shell-xg-t

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5. It will take you to the dc_shell now. 6. This needs Technology Library information from you. dc_shell>>set search_path /home/esdcad/designkits/st/st12/v92/CORE9GPLL
_SNPS_AVT_4.1/SNPS/bc_1.32V_0C_wc_1.08V_105C/PHS

dc_shell>> set target_library [list CORE9GPLL_Worst.db] dc_shell>> set link_library [list {*} CORE9GPLL_Worst.db CORE9GPLL_Best.db] dc_shell>> set symbol_library [list CORE9GPLL.sdb] Now you need to read your design in DC. You can simply use read command to read your RTL level design (verilog/VHDL). Note: In the commands below, RTL_PATH is the path where your RTL files are saved. The commands are shown below: dc_shell>> dc_shell>> dc_shell>> dc_shell>> read_file -format vhdl ./RTL_PATH/counter8.vhd read_file -format vhdl ./RTL_PATH/en_gen.vhd read_file -format vhdl ./RTL_PATH/flop7.vhd read_file -format vhdl ./RTL_PATH/top.vhd 7.

(Note: you can type the following in the DC command prompt to know which file formats are supported >> man read_file. Currently DC supports VHDL, Verilog, System verilog (sverilog)) Now you need to link your design with the library specified earlier: dc_shell>> link 9. Now you need to apply design constraints (clock constraints, multicycle path, false path etc.) within dc_shell. In your dc_shell command window simply source the constraint file (clock.con) file as follows: dc_shell>> source ./RTL_PATH/clock.con (Note: You can open clock.con file using a text editor (e.g vi, emacs or nedit). 10. Now you are ready to do the compilation of your whole design under the available technology library. Command is as follows: dc_shell>> compile Note: does not insert clock gating ckt, so use this command if you do not want clock gating 11. Power Analysis: You can see approximate power consumption by typing the following command within dc_shell: 8.

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dc_shell>> report_power 12. See timing of your design: dc_shell>> report_timing Exercise 1 (a): Take a snapshot of the schematic and save it as an image file. (The following command will open DC GUI. dc_shell>> gui_start Then click on the create design schematic button at the top panel of the DC GUI window to view the schematic of your design.) Exercise 1 (b): Save the power result as a text file and also note it down in your logbook. 13. Type exit to close dc_shell. NOTE: Here is how the report file looks like:
## APPROXIMATE POWER CONSUMPTION REPORT WITHOUT GATING ### Library(s) Used: CORE9GPLL (File: /home/esdcad/designkits/st/st12/v92/CORE9GPLL_SNPS_AVT_4.1/SNPS/bc_1.32V_0C_wc _1.08V_105C/PHS/CORE9GPLL_Worst.db) Operating Conditions: Worst Library: CORE9GPLL Wire Load Model Mode: top

Design Wire Load Model Library -----------------------------------------------top area_1Kto2K CORE9GPLL

Global Operating Voltage = 1.08 Power-specific unit information : Voltage Units = 1V Capacitance Units = 1.000000pf Time Units = 1ns Dynamic Power Units = 1mW (derived from V,C,T units) Leakage Power Units = 1pW

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Cell Internal Power = 409.3364 nW (85%) Net Switching Power = 73.3264 nW (15%) --------Total Dynamic Power = 482.6628 nW (100%) Cell Leakage Power = 9.1498 uW

################################################################ PART-B : SYNTHESIZE WITH CLOCK-GATING 14. Follow Step-1 to Step-6 from PART-A. 15. Now, this step has to be followed if you want DC to insert clock gating circuits within your design. dc_shell>> set_clock_gating_style -sequential_cell latch -minimum_bitwidth 3 Note: type in dc_shell>> man set_clock_gating_style to know more about the available options/ switches for clock gating. 16. 17. Follow Step-7 to Step-9 from PART-A. Now clock gating will be inserted in the same design as follows: dc_shell> compile -gate_clock (Note: compile gate_clock command inserts clock gating within the generated netlist, so use this if you want your netlist to have clock gating circuit. If you are interested in optimizing it more try the following: dc_shell>> man compile_ultra ) 18. You can see approximate power consumption by typing the following command within dc_shell: dc_shell>> report_power 19. See timing of your design: dc_shell>> report_timing 20. report the clock gating insertion in your design: dc_shell>> report_clock_gating Exercise 2 (a): Take a snapshot of the schematic and save it as an image file. Exercise 2 (b): Save the power result as a text file and also note it down in your logbook. Exercise 2 (c): Compare the results of Exercise 1(b) with Exercise 2(b). Any difference can you find out? Exercise 2(d): Compare the results of Exercise 1(a) with Exercise 1(b). Any difference can you observe? (Snapshot of the sample schematic is shown in Fig. 1(c). Can you see

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the clock gating module?) NOTE: Here is how the report file looks like: ### APPROXIMATE POWER CONSUMPTION REPORT WITH CLOCK GATING ####
Library(s) Used: CORE9GPLL (File: /home/esdcad/designkits/st/st12/v92/CORE9GPLL_SNPS_AVT_4.1/SNPS/bc_1.32V_0C_wc _1.08V_105C/PHS/CORE9GPLL_Worst.db) Operating Conditions: Worst Library: CORE9GPLL Wire Load Model Mode: top Design Wire Load Model Library -----------------------------------------------top area_0to1K CORE9GPLL Global Operating Voltage = 1.08 Power-specific unit information : Voltage Units = 1V Capacitance Units = 1.000000pf Time Units = 1ns Dynamic Power Units = 1mW (derived from V,C,T units) Leakage Power Units = 1pW

Cell Internal Power = 136.7583 nW (65%) Net Switching Power = 74.1868 nW (35%) --------Total Dynamic Power = 210.9451 nW (100%) Cell Leakage Power = 6.8746 uW

NOTE: See the dynamic power consumption results of these two power reports (with and without gating). Design containing clock gating, as per expectation, consumes less dynamic power.

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Fig. 1(c)

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