CAD for VLSI Design - II

Lecture 2 V. Kamakoti and Shankar Balachandran

Overview of this Lecture

Modeling Delay and power Introduction to MOSFET Introduction to Layout Techniques Transistor level simulation

Power and Energy Dissipation

Power consumption determines how much energy is consumed per operation, and how much heat is dissipated. supply capacity and battery lifetime (determined by average power) sizing of supply lines (determined by peak power) packaging and cooling requirements Propagation delay is mostly determined by the speed at which a given amount of energy can be stored on the gate capacitors the faster the energy transfer (or higher power dissipation) the faster the gate. Energy consumed by the gate per switching event is simply the power-delay product (PDP). Ideal Gate: it is fast, and consumes little energy. ED product is a combined metric speed and energy.

Introduction to MOSFETs

A MOSFET is a Voltage Controlled Switch

MOSFETs as Switches for Gates

MOSFETs in SPICE

.MODEL NENH NMOS + Level= + .MODEL PENH PMOS + Level= +

CMOS Inverter

CMOS Logic Gate

NMOSFETs in Series/Parallel Network

PMOSFETs in Series/Parallel Networks

CMOS NAND Gate

CMOS NOR Gate

Magic Layout Layers

Magic Layout: CMOS Inverter

Vdd!

in

out

GND! Transistor level Schematic CMOS Layout

Magic Files
cell.mag
magic tech scmos timestamp 1011216956 << pdiffusion >> rect 13 12 14 16 rect 18 12 19 16 << ndcontact >> rect 14 -12 18 -8 rect 14 -20 18 -16 << pdcontact >> rect 14 12 18 16 rect 14 4 18 8 << polysilicon >> rect 10 9 13 11 rect 19 9 21 11 rect 10 -13 12 9 << metal1 >> rect 7 12 14 16 rect 18 12 23 16 rect 14 -8 18 4 << labels >> rlabel polysilicon 11 -2 11 -2 3 in rlabel metal1 9 -19 9 -19 2 GND! << end >>

cell.cif
( @@source : inv.mag ); ( @@technology : scmos ); ( @@version : 8.2.8 );( @@techdesc : MOSIS Scalable CMOS Technology ); DS 1 50 2; 9 inv; L CWN; B 64 88 64 40; L CWP; B 56 88 64 -56; L CMF; B 64 16 60 56; L CPG; B 44 8 62 40; L CAA; B 24 48 64 40; L CCA; B 8 8 64 56; L CSN; B 32 64 64 -56; L CSP; B 40 64 64 40; 94 in 44 -8 CPG; 94 out 64 -8 CMF; 94 Vdd! 32 52 CMF; 94 GND! 36 -76 CMF; DF; C 1; End

layout DRC

Mask info.

Extracted Netlists
timestamp 1011216956 cell.ext version 5.1 tech scmos style AMI0.5um(amic5)from:T01X scale 1000 1 30 resistclasses 82100 102500 827000 827000 1 26000 26500 26500 90 90 50 node "GND!" 443 1166.4 14 -20 ndc 19 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 40 0 0 0 0 node "out" 566 1411.2 13 4 pdif 19 24 30 22 0 0 0 0 0 0 0 0 0 0 0 0 80 48 0 0 0 0 node "in" 546 522.72 10 -15 p 0 0 0 0 0 0 0 0 0 0 84 88 0 0 0 0 0 0 0 0 0 0 node "Vdd!" 123 1166.4 13 11 pdif 0 0 30 22 0 0 0 0 0 0 0 0 0 0 0 0 64 40 0 0 0 0 fet nfet 14 -15 15 -14 6 10 "Gnd!" "in" 4 0 "GND!" 3 0 "out" 3 0 fet pfet 13 9 14 10 12 16 "Vdd!" "in" 4 0 "out" 6 0 "Vdd!" 6 0

ext2sim t! t# cell
| units: 30 tech: scmos format: SU p in out Vdd 2 6 13 9 g=S_Vdd s=A_30,P_22 d=A_30,P_22 n in GND out 2 3 14 -15 g=S_Gnd s=A_19,P_24 d=A_19,P_24 R GND 443 R out 566 R in 546 cell.sim R Vdd 123

ext2spice c0 t! t# -f spice3 cell

* SPICE3 file created from inv.ext - technology: scmos m1000 Vdd in out Vdd pfet w=1.8u l=0.6u + ad=2.7p pd=6.6u as=2.7p ps=6.6u m1001 out in GND Gnd nfet w=0.9u l=0.6u + ad=1.71p pd=7.2u as=1.71p ps=7.2u C0 out GND 1.4fF C1 in GND 0.5fF cell.spice C2 Vdd GND 1.2fF

SPICE Simulation
* SPICE3 file created from inv.ext - technology: scmos .LIB /home/cad/vlsi/models/spice3/cmos0.5um.model noprint .param PVCC 3.3V .param PStd_Load 0.05pF .param PFO 4 m1 + m2 + C1 C2 Vdd in out Vdd pfet w=1.8u l=0.6u ad=2.7p pd=6.6u as=2.7p ps=6.6u out in GND Gnd nfet w=0.9u l=0.6u ad=1.71p pd=7.2u as=1.71p ps=7.2u in GND 0.5fF Vdd GND 1.2fF

Cout out GND #PFO*PStd_Load# VVdd Vdd 0 #PVCC# VGND GND 0 0v Vin in GND PBIT 0v #PVCC# 10n 1n 10n 1n 20n & $01010101010101010101 .tran 0.02ns 400ns .punch trans V (in out) P(VVdd, ta) .end

Questions and Answers

Thank You