FIELD PROGRAMMABLE COMPRESSOR TREES

FPGA performance is currently lacking for arithmetic circuits. In particular, FPGAs cannot exploit one of the fundamental results of computer arithmetic: the use of carry-save (based) addition to efficiently add k > 2 integers. The addition of two integers requires the use of a carry propagate adder (CPA), e.g., a ripple carry or parallel-prefix adder, whose critical path delay is from the carry-in to the carry-out bit. The method to add k > 2 integers is to use an adder tree, i.e., a binary tree of CPAs; a compressor tree (e.g., a Wallace) is a circuit that uses carry-save addition to add k > 2 integers: the output is two integers, S (sum) and C (carry) such that S+C is the sum of the k integers. Thus, a CPA is only required to add S and C, rather than at every level of the tree.

Multi-operand integer addition occurs in a wide variety of applications including, but not limited to, FIR filters , video coding, and 3G wireless base station channel cards .Verma and Ienne have introduced a set of data flow transformations that can expose opportunities to exploit the carry save representation. First, each multiplication operation is decomposed into a partial product generator, compressor tree, and CPA. A sequence of sorting rules is applied to the flowgraph to reorder the operations such that disparate CPAs are merged with one another and with other compressor trees. Each subsumption of a CPA into a larger compressor tree replaces the carry-in to carry-out delay with a smaller delay due to a slightly enlarged compressor tree.

A circuit is partitioned into a (set of) compressor tree(s) with corresponding CPA(s) and a set of non arithmetic operations. The compressor tree is mapped onto an FPCA, which is

embedded within a larger FPGA. The fig. 2 assumes that a dedicated CPA is integrated into the FPCA; alternatively, the carry chains in the logic-block structure of the FPGA could be used to perform the final CPA. The arithmetic capabilities of FPGAs are not well attuned to the needs of carry-save arithmetic. Programmable LUTs have been augmented with fast carry chains that are good building blocks for CPAs but cannot be used for carry-save arithmetic. The fastest methods to synthesize compressor trees on FPGA general logic do not use the carry chains except for the final CPA.. The non arithmetic portions of the circuit are mapped onto the FPGA. Following the lead of Xilinx and Altera, the FPGA shown in fig. 2 is organized into columns. Each column contains a set of logic clusters [e.g., the Altera Logic Array Block (LAB)], which contain several logic blocks [e.g., the Altera Adaptive Logic Module (ALM)] connected by local routing. A global routing network connects the different logic clusters. Due to the column structure, the horizontal and vertical routing channels are non uniform.