Process ChaIIenges for Integrated

MEMS Devices
MichaeI Hornung, SUSS MicroTec
Technical Marketing Manager
OutIine
ntroduction
SUSS Business Update
MEMS Key Applications and Technology Trend
1
2
3
Lithography Exposure Optics Basics
4
Wafer Bonding Basics and SUSS Process Knowledge
5
Summary
6
OutIine
ntroduction
SUSS Business Update
MEMS Key Applications and Technology Trend
1
2
3
Lithography Exposure Optics Basics
4
Wafer Bonding Basics and SUSS Process Knowledge
5
Summary
6
30 Years of MEMS Manufacturing History
Some statements about MEMS:
MEMS remains a fragmented
market
MEMS packaging / integration
is clearly an added value
The YOLE MEMS law:
"One product, one process,
one package still rules
MEMS devices requires highly
specialized manufacturing
equipment.
> >> >Process SoIutions
Processing MEMS Devices
Wafer
Bonder
Mask Aligner Coater
Mask Aligner
Lift-off
System
Alignment
Verification
System
Spin/Spray
Coater
Developer
Grafiken: Silizium Airbagsensor (von Robert Bosch GmbH)
Cleaning Topography
Coating
Alignment
Verification
Wafer
Bonding
Metal Lift-
Off
Mounting
/ Dicing
Wafer Level
Packaging
nspection
/ Testing
Exposure
MEMS Fabrication - From Wafer to Sensor
OutIine
ntroduction
SUSS Business Update
MEMS Key Applications and Technology Trend
1
2
3
Lithography Exposure Optics Basics
4
Wafer Bonding Basics and SUSS Process Knowledge
5
Summary
6
SUSS MicroTec at a GIance
SUSS MicroTec: A global leader in semiconductor manufacturing equipment
Equipment and process solutions for creating the micro structures that build
and connect micro electronic devices
Focusing on high growth market segments: Semiconductors, MEMS, LEDs
More than 8,000 systems installed worldwide
Listed at TecDAX (Top 30 German technology companies)
60+ years of experience in semiconductor manufacturing equipment
Two facilities in Germany for development and manufacturing
One production facility in USA
Strong global support infrastructure with sales and service offices in USA,
Singapore, Korea, Taiwan, China and Japan
PO 1999: Listed in the TecDax of the German stock exchange
Strong competitive positioning: first or second in the target markets
Solid financial situation
Facts
SUSS MicroTec - A GIobaI PIayer
Singapore
Hwaseong City, KR
Shanghai, CN
Hsin Chu, TW
NORTH AMERICA EUROPE ASIA
Yokohama, JP
Headquarter
Production
Sales
Garching, DE
Sternenfels, DE
Hauterive, CH
Lyon, F
Coventry, UK
Sunnyvale, US
Corona, US
MaskTrack Pro Wafer Bonder
Process
Steps
Markets
Coater/DeveIoper
Coating
DeveIoping
Bond AIignment
Permanent Bonding
Temporary Bonding
Photomask
CIeaning
Frontend Backend
Products
Exposure Systems/
Laser Structuring
AIignment
Exposure
Nano Imprinting
Laser Structuring
Mask Making
Advanced Packaging
3D ntegration
MEMS
LED
9 Cost Effective Mask Aligner Lithography Techniques for LED Manufacturing
SUSS MicroTec Process SoIutions
SUSS Company Strategy
ConsoIidation of
Production Sites &
Equipment pIatforms
3D is major
Focus for growth
Three product Iines are manufactured under
one roof
One singIe 300 mm production pIatform for
bonders & coaters
Profit form experience of aImost > 700
instaIIed production systems
3D integration is major growth driver
Major focus & invest into bonder product Iine
esp. for temporary bonding
QuaIity, Efficiency
& Innovativeness
ConsoIidated R&D and Engineering
Organization
Grow & buiId up innovative R&D areas
CIear process & ownership for continuous
improvement
OutIine
ntroduction
SUSS Business Update
MEMS Key Applications and Technology Trend
1
2
3
Lithography Exposure Optics Basics
4
Wafer Bonding Basics and SUSS Process Knowledge
5
Summary
6
MEMS Devices: TechnoIogy Trend & Requirements
Smaller form factors
ntegration with active devices
High yield and short process cycle time
Photolithography Substrate Bonding
MEMS Lithography: TechnoIogy Trend & Requirements
Smaller form factors
Device scaling requires higher resolution and better pattern fidelity of the
lithography structures
mproved alignment accuracy and efficient alignment verification
ntegration with active devices
Requires 3D lithography over topography including high-topography spray
coat & develop
Combines thin and thick resist lithography
Thin and warped wafer handling
High yield and short process cycle time
High performance exposure optics with greatest light uniformity
High throughput and full wafer exposure
MEMS Wafer Bonding: TechnoIogy Trend & Requirements
Smaller form factors
Device scaling requires better hermeticity levels within the packages
Metal Seals provide a pathway to achieve higher hermeticity with smaller seal
ring geometries = smaller chip size
ntegration with active devices
Requires metal interconnects compatible with CMOS processes and materials
Low temperature bonding
Must eliminate sodium containing glass products
High yield and short process cycle time
Precise temperature and force control
mproved temperature and pressure uniformity
Capability of fast heating and cooling
OutIine
ntroduction
SUSS Business Update
MEMS Key Applications and Technology Trend
1
2
3
Lithography Exposure Optics Basics
4
Wafer Bonding Basics and SUSS Process Knowledge
5
Summary
6
OpticaI Lithography - ResoIution Iimits
Mask Aligner > ~ 1 .. 3 m
1x Stepper (Ultratech) > ~ 0.7 m
i-line Stepper (4x or more) > ~ 0.2 .. 0.5 m
DUV Stepper (193 nm) > ~ 0.1 .. 0.2 m
How reach the state-of-the-art
resolution of <45 nm with an
optical resolution limit of about
100 nm?
ResoIution enhancement techniques (RET)
Answer:
With Resolution Enhancement Techniques (RET)
Optical Proximity Correction (OPC)
Double Patterning / Multiple Patterning
mmersion Lithography
Off-Axis llumination (dipole, quadruple, annular)
Phase Shift Masks
Advanced llumination
Source Mask Optimization (SMO)
.
ResoIution enhancement techniques (RET)
Optical Proximity Correction (OPC)
Double Patterning / Multiple Patterning
mmersion Lithography
Off-Axis llumination (dipole, quadruple, annular)
Phase Shift Masks
Advanced llumination
Source Mask Optimization (SMO)
.
=
SUSS diffraction
reducing optics
Mask AIigner Lithography - Shadow Printing
Mask aligner lithography = shadow printing
Shadow Images
The quality of shadow image depends on the distance between object and screen
(= exposure gap) and on the shape of the illumination system (= exposure optics)
Shadow of a bough at different distances to the wall*
Shadow of a
chair for different
illumination
settings**
* W. Sommer, Lehrerseminar ber Goetheanismus
** T. Quick, Mathematische Beschreibung von Schattenbildern im Kontext der phnomenologischen Optik
MO Exposure Optics principIe
KhIer Integrator (I)
Uniform Angular Spectrum
KhIer Integrator (II)
IFP: IIIumination FiIter PIate
(exchangeabIe)
Defines AnguIar Spectrum
,

[
Uniform lllumination
Customised llumination!
= Source Optimization
MO Exposure Optics for MaskaIigner
Unmatched light uniformity and illumination stabilization
1
MO Exposure Optics - customized iIIumination
"Customized illumination filter plates
for the MO Exposure Optics
Some general recommendations
MO Exposure Optics for MaskaIigner
Unmatched light uniformity and illumination stabilization
1
Customized illumination
2
ResoIution enhancement techniques (RET)
Optical Proximity Correction (OPC)
Double Patterning / Multiple Patterning
mmersion Lithography
Off-Axis llumination (dipole, quadruple, annular)
Phase Shift Masks
Advanced llumination
Source Mask Optimization (SMO)
Why Mask AIigner Lithography SimuIation?
Square10m x 10m, Proximity Gap 50m, Photoresist AZ4110, 1.2um thick
Mask aligner lithography simulation reduces the number of experiments
Lithography SimuIation for SMO - ExampIes
Non-Optimized Layout
Conventional Source
Optimized layout
Optimized source
Lithography Simulation for SMO Examples
ExampIes - Topography Lithography
Conformal resist on trench
structures.
50 m and 150 m features
resolved across a 200 m
deep trench.
10 m holes resolved at the
bottom of 80 m deep vias
ExampIes - Thick Resist
Copper coil, 20 m high 200 m SU-8 Resist
Projection Lithography SoIutions
The DSC300 projection scanner combines the best of a traditional
stepper and mask aligner by utilizing a high-resolution projection lens
with a full-wafer mask, thus enabling high-throughput exposure of
wafers.
Broadband 1:1 catadioptric projection lens provides resolution down
to 2 m and a large depth of focus for accurate imaging of both thin
and ultra-thick resists
Ability to control resist sidewall angles by varying the numerical
aperture (0.07-0.14) and focal position at the resist surface
ExampIes - Projection Lithography Thick Resist
30 m vias in 100 m WBR2100
Honey comb in 860 m SU-8
40 m vias in 80 m AZ125nXT 5 m vias in 10 m AZ10XT
6 and 7 m L/S in 15 m AZ4620 6 m vias in 10 m HD8820 PBO
Coating of MEMS structures
Conformal coatings of high aspect ratio structures
Thick coatings of resists and dielectrics
Alignment and Exposure for MEMS devices
Advanced imaging techniques coupled with DirectAlign,
ThermAlign and alignment verification achieve optimum
pattern overlay
Customized exposure optics for high quality pattern fidelity
with best light uniformity for highest yield
Process adapted choice of full field mask aligner technology or
scanning projection lithography
Coating of MEMS structures
Conformal coatings of high aspect ratio structures
Thick coatings of resists and dielectrics
Alignment and Exposure for MEMS devices
Advanced imaging techniques coupled with DirectAlign,
ThermAlign and alignment verification achieve optimum
pattern overlay
Customized exposure optics for high quality pattern fidelity
with best light uniformity for highest yield
Process adapted choice of full field mask aligner technology or
scanning projection lithography
SUSS MicroTec - MEMS Lithography Process SoIutions
OutIine
ntroduction
SUSS Business Update
MEMS Key Applications and Technology Trend
1
2
3
Lithography Exposure Optics Basics
4
Wafer Bonding Basics and SUSS Process Knowledge
5
Summary
6
MEMS Wafer Bonding: TechnoIogy Trend & Requirements
Smaller form factors
Device scaling requires better hermeticity levels within the packages
Metal Seals provide a pathway to achieve higher hermeticity with smaller seal
ring geometries = smaller chip size
ntegration with active devices
Requires metal interconnects compatible with CMOS processes and materials
Low temperature bonding
Must eliminate Na containing glass products
High yield and short process cycle time
Precise temperature and force control
mproved temperature and pressure uniformity
Capability of fast heating and cooling
Bonding processes with typicaI bond temperatures
w/o ntermediate Layer w/ ntermediate Layer
Fusion
Eutectic
Metal
Diffusion
Anodic
Plasma
Activation
Wet
Chemical
Adhesive
AuSn/290
AuSi/390
AlGe/430
CuSn/240

Au-Au/300
Al-Al/400
Cu-Cu/350
BCB/250
Polyimide/300
Epoxy/160
Silicone/200

Glass
Frit
Pb-free/450
Si/SiO
2
/1000
Pyrex/370,400V
Hydrophilic/200
UHV/RT
Permanent Bonding
Temporary Bonding and De-Bonding
Thermal Slide
TraditionaI
CuSn/270
Aun/180
TLP/SLD
Laser Lift-Off
Future Trend
Room Temperature Peel-Off
MEMS Wafer Bonding: Low Temperature Bonding
Low temperature bonding > >> > metal bonding
Metal Diffusion Bonding
Cu to Cu
Au to Au
Ti to Ti/Si
Eutectic Alloy Bonding
Au/Si
Au/n
Au/Sn
Cu/Sn
Al/Ge
ExampIes MEMS Wafer Bonding: MetaI Bonding
= == =
SAM Analysis of a 200 mm
aligned Cu-Cu bond
= == =
SAM Analysis of a 150 mm
aligned 6 Au-Sn bond
> >> >
SAM Analysis of a 200 mm
aligned Al-Ge bond
> >> >
150 mm Au-Si bonding for
Gyros
Examples of various void free and uniform metal bonds
SUSS MicroTec MetaI Bonding PubIications (2009-2012)
Low-temperature MetaI Bonding by sub-m Au ParticIe
Enables low-temperature bonding by reaction < 200 C due to
particle size effect
Au particles densified to Au bulk provide hermetic sealing and
high temp. resistant
Sealing + electrical interconnect in one cycle
Fine patterns (~10 m) performend with lithography process
Absorbed surface roughness results in higher yield
Cap
Contact pad
Via
MEMS wafer
Seal ring nterconnect
MEMS Wafer Bonding: TechnoIogy Trend & Requirements
Materials: Process flow:
150qC 200qC
Reaction of Au particles by heating
Alignment
Wafer A
Bonding
Wafer B
Carrier Wafer
Au Particle
Patterning
Pattern Transfer
Alignment
Au particles
Purity: 99.95 %
Size: ~ 0.3m
Slurry
Dispersed Au particles in organic solvent,
including no organic binder > no organic
residues
Sub-m Au ParticIe Bonding
1. Photoresist patterning 3. Drying (Solvent removal)
2. Filling of Au particles
photoresist
Ti/Au metallization
Glass wafer
Au slurry
4. Au particle excess removal 5. Sintering of Au particles 6. Photoresist removal
blade
100 C
n air
Au particle pattern
Sub-m Au particle patterning
ExampIe of Surface-CompIiant Behavior of Sub-m Au ParticIe
Cross-section SEM images of
a 20 m-wide seal ring
2 bonded pair (glass + alumina)
Bonded at 180 C, 100 MPa, 30 min.
He leak rate < 1x10
-9
Pam
3
/s
Alumina
Glass
Alumina
Glass
Seal ring
(Au particle pattern)
OutIine
ntroduction
SUSS Business Update
MEMS Key Applications and Technology Trend
1
2
3
Lithography Exposure Optics Basics
4
Wafer Bonding Basics and SUSS Process Knowledge
5
Summary
6
Summary
MO Exposure Optics for the SUSS mask aligner improves the light
uniformity and therefore increases the yield and reduce
maintenance.
MO Exposure Optics allows to customize the angle distribution of
the light source and opens the field to optical proximity correction
and source mask optimization on mask aligners
Projection lithography with an optics with variable NA allows the
optimization of highest resolution and largest DoF
Wafer level pattern transfer of sub-micron Au particles was
successfully performed on commercially available production tools
at a low temperature of 150 C with an applied pressure of 20 MPa.
Acknowledgment
Thanks to my colleagues from SUSS MicroTec
Hiroyuki Ishida, SUSS MicroTec KK, Japan
Matt Souter, Tamarack Scientific, USA
Sumant Sood, SUSS MicroTec Inc, USA
Uwe Vogler, SUSS MicroOptics, Switzerland
Christian Weindel, SUSS MicroTec Lithography GmbH, Germany
and many more
Thanks to our partners
Fraunhofer Institute IISB, Germany
GenISys GmbH, Germany
Microresist Technology GmbH, Germany
Tanaka Kikinzoku Kogyo KK, Japan
Waseda University, Japan
)urther information's
@ www.suss.com
or visit our booth No. 576