Incremental Power Grid Verication

Abhishek
Department of Electrical and Computer Engineering
University of Toronto
September 5, 2012
Abhishek Incremental Power Grid Verication 1 / 32
Outline
1
Introduction
Vectorless Verication
Incremental Grid Verication
Contributions
2
Background
RC Grid Verication
RLC Grid Verication
Model Order Reduction
3
Proposed Approach
Efcient Bounds
Macromodeling
Results
4
Extensions
Dimensionality Reduction
Chip Power Model
5
Conclusions
Abhishek Incremental Power Grid Verication 2 / 32
Introduction Vectorless Verication
The Need
Modern integrated circuits (IC) designs are susceptible to supply
voltage uctuations:
Reduced supply voltage levels
Increase in active and leakage currents
Traditional verication ows based on circuit simulation has
serious drawbacks:
Number of traces to cover the space of voltage drops is intractable
Require complete knowledge of current waveforms
Grid verication should be done early in the design ow
Solution:
A vectorless and early power grid verication approach
Abhishek Incremental Power Grid Verication 3 / 32
Introduction Vectorless Verication
Constraints-based Verication
Vectorless approach based on partial current specications
Current constraints are used to capture uncertainty about circuit
behavior
Grid verication is reduced to nding worst-case voltage drop over
all possible currents satisfying the constraints
Two types of constraints:
Local constraints: upper bounds on individual current sources
Global constraints: upper bounds on sums of groups of currents
Combined together, local and global constraints form a feasible
space of currents F
Abhishek Incremental Power Grid Verication 4 / 32
Introduction Incremental Grid Verication
Motivation
Abhishek Incremental Power Grid Verication 5 / 32
Grid verication requires solving a linear program (LP) for every
node
Verication of the entire grid can become overkill:
Large size of modern power grids
Design changes made to local region of previously veried grid
need to be analyzed
Cases like IP reuse, where a portion of grid need not be veried
Incremental Power Grid Verication becomes a necessity!!!
Introduction Incremental Grid Verication
Introducing Incremental Verication
Abhishek Incremental Power Grid Verication 6 / 32
User identies part of the grid,
that need not be veried,
referred to as sub-grid
Verication is required for nodes
outside the sub-grid, also known
as external nodes
Nodes inside the sub-grid can
either be port or internal nodes:
Port nodes connect the
sub-grid to external nodes
All other sub-grid nodes are
internal nods
Introduction Contributions
Incremental Vectorless Verication
Abhishek Incremental Power Grid Verication 7 / 32
A technique for incremental vectorless verication for R grids
was proposed by Kouroussis et al. [ICCAD 05]
In this work, incremental vectorless verication is extended to
the transient case through the following two contributions:
Efcient computation of upper bounds on worst-case voltage
drops at internal nodes
Macromodeling of the internal grid section by:
Adapting multi-port Nortons theorem proposed in HiPRIME by
Lee et al. [TCAD 05] to our verication framework
Combining moment matching-based reduction by Liao and
Dai [ICCAD 95] with node elimination-based reduction proposed
by B. Sheehan [TCAD 07] to reduce the resultant passive RC
circuit
Background RC Grid Verication
Grid Model
Abhishek Incremental Power Grid Verication 8 / 32
g
c
g
g
c
g g
g
g
c c
V
dd
i
(s,1)
(t)
c
g
c
g g g
g
c c c
g g
c
g g g
c c
g
i (t)
(s,2)
System equation:
Gv(t ) +C

v(t ) = i (t )
Background RC Grid Verication
Verication
Applying a nite-difference approximation to RC system equation:
Av(t ) =
C
t
v(t t ) + i (t )
where
A = G+
C
t
An upper bound on the worst-case voltage drop vector was
proposed by Ferzli et al. [ICCAD 07]:
v
ub
=
_
I +G
1 C
t
_
V
a
where V
a
is the worst-case voltage drop vector at t = t in the
special case when i (t ) = 0, t 0 and is expressed as:
V
a
= emax
i F
(A
1
i )
with emax being an operator to perform element-wise
maximization of its vector argument.
Abhishek Incremental Power Grid Verication 9 / 32
Background RLC Grid Verication
Grid Model
Abhishek Incremental Power Grid Verication 10 / 32
g
i
(s,1)
(t)
g
l g
c
g g
g
V
dd
g
l g
l
c
g g
c c i (t)
(s,2)
c
g g
c c c
l g
g g
c
g g
c c c
g
System equations:
Gv(t ) +C

v(t ) Mi (t ) = i
s
(t )
M
T
v(t ) +L

i (t ) = 0
Background RLC Grid Verication
Verication
The RLC grid can be transformed into a reduced circuit by
eliminating the inductive branch currents as proposed by Abdul
Ghani et al. [TCAD 11]
v(t ) = D
1
Ev(t t ) +D
1
i
s
(t )
where D =
_
G+
C
t
+M
L
t
1
M
T
_
and E =
_
C
t
+M

G
_
To compute the bounds at innity, upper and lower bounds on
voltage drops for r time steps ahead in time are computed and are
given by:
w
r
= w
r 1
+ eopt
i
s
F
[(D
1
E)
r 1
D
1
i
s
]
The upper and lower bounds at innity are now given by:
_
v
ub
()
v
lb
()
_
= (I R)
1
w
r
where R is composed of N and element-wise absolute values of
the entries in N.
Abhishek Incremental Power Grid Verication 11 / 32
Background Model Order Reduction
RC MOR
A large RC interconnect network is partitioned into smaller
sub-networks
Admittance matrix looking into the ports is approximated using the
rst two order moments as:
Y(s) M
0
+M
1
s
where M
0
and M
1
are zero and rst-order moment matrices
respectively
A 2 model is constructed between each pair of ports by matching
the moments:
Circuit between pair of ports is synthesized using T-model
Port-to-ground elements are modeled using parallel RC model
Abhishek Incremental Power Grid Verication 12 / 32
Background Model Order Reduction
Node Elimination (TICER)
Abhishek Incremental Power Grid Verication 13 / 32
The reduction is based on the time
constant of a node
_

N
=
C
N
G
N
_
where C
N
and G
N
are respectively, the sums of
capacitances and conductances incident
on the node.
If
N
is less than a user-specied value of
time constant, the node is removed as
follows:
If nodes i and j were connected to node
N by conductances g
iN
and g
jN
, insert a
conductance
_
g
iN
g
jN
G
N
_
between i and j
If node i had a capacitor c
iN
and j had a
resistor g
jN
, insert a capacitor
_
c
iN
g
jN
G
N
_
between i and j
port - i
C
R
ij2
R
ij1
ij
port - j
T-model
ii
port - i R
ii
C
parallel RC model
Proposed Approach Efcient Bounds
Estimating Internal Nodes Voltage Drops
Partitioned system equation:
_
_
G
11
G
12
0
G
T
12
G
22
G
23
0 G
T
23
G
33
_
_
_
_
v
ext
(t )
v
prt
(t )
v
int
(t )
_
_
+
_
_
C
ext
0 0
0 C
prt
0
0 0 C
int
_
_
_
_

v
ext
(t )

v
prt
(t )

v
int
(t )
_
_
=
_
_
i
s,ext
(t )
i
s,prt
(t )
i
s,int
(t )
_
_
An upper bound on v
ub
can be found as:
v
ub

_
I +G
1 C
t
_
_
_
I
ext
0 0
0 I
prt
0
0 T
T
A
1
int
_
_
emax
i
s
F
_
_
v
ext
(t )
v
prt
(t )
i
s,int
(t )
_
_
Because emax
i
s
F
(i
s,int
(t )) = i
L,int
(vector of local constraint values
for internal current sources), computing an upper bound on v
ub
requires:
Solving LPs for external and port nodes,
Standard system solve
Abhishek Incremental Power Grid Verication 14 / 32
Proposed Approach Macromodeling
Norton Equivalent Current Sources
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To nd Norton equivalent currents at port nodes that will
replace the internal current sources:
Disconnect the sub-grid from rest of the grid
Connect each port node to ground
Evaluate current owing through short circuits
Proposed Approach Macromodeling
Modied Grid
System equation for the isolated sub-grid with port nodes
connected to ground:
G
33
v

int
(t ) +C
int

v

int
(t ) = i
s,int
(t )
Current through port node to ground will be given by:
i

(t ) = G
23
v

int
(t )
Using the special case used to dene V
a
, the voltage at time
t = t in this modied grid will be given by:

v(t ) = A
1

Ji
s
(t )
where

J =
_
_
I
ext
0 0
0 I
prt
T
0 0 0
_
_
Abhishek Incremental Power Grid Verication 16 / 32
Proposed Approach Macromodeling
Reducing the Passive Sub-grid
Abhishek Incremental Power Grid Verication 17 / 32
After moving internal current sources to port nodes, we are left
with a passive RC internal network:
To reduce the passive network:
RC MOR to give port-to-port connections using T-model and
parallel RC model
Node elimination on every new internal node generated by the
T-model
Conductance values smaller than a threshold are removed by
setting those entries to 0
Proposed Approach Macromodeling
Verication after Macromodeling
New system matrices:

G =
_
_
G
11
G
12
0
G
T
12

G

22

G
23
0

G
T
23

G
33
_
_
,

C =
_
_
C
ext
0 0
0

C
prt
0
0 0

C
int
_
_
Reduced size:

n = n
ext
+ n
prt
+

n
int
Voltage at time t = t for the reduced grid:

v(t ) =

A
1

Ji
s
(t )
Upper bound on worst-case voltage drop:

v
ub
=
_
I +G
1 C
t
_
_
_
I
ext
0 0
0 I
prt
0
0 T
T
A
1
int
_
_
_

_
emax
i
s
F
(

v
ext
(t ))
emax
i
s
F
(

v
prt
(t ))
i
L,int
_

_
Abhishek Incremental Power Grid Verication 18 / 32
Proposed Approach Results
Experimental Setup
A C++ implementation was written to test the proposed approach
Test grids were generated from user specications:
Grid dimensions
Metal layers, pitch and width per layer
Supply voltage sites and current source distribution
Consistent with 1.1 V 65nm CMOS technology
SPAI (Abdul Ghani et al. [DAC 09]) was used to compute
approximate inverse
Computations were done using a 2.6 GHz Linux machine with
24Gb of RAM
Abhishek Incremental Power Grid Verication 19 / 32
Proposed Approach Results
Experimental Results

1
= 0.1mV
2
= 0.01mV = 5ps = 5 10
3

Speed and accuracy after using efcient bounds computation

Power Grid Sub-grid Max Error Speed
Name Nodes n
int
n
prt
(mV) Up
G1 32,554 15,714 208 0.07 2.17x
G2 72,692 42,764 348 0.07 2.47x
G3 128,241 95,294 413 0.08 4.46x
G4 162,087 124,824 518 0.08 4.8x
Speed and accuracy after applying macromodeling
Power Max Error Avg. % CPU time Speed
Grid (mV) Error (s) Up
G1 1.35 1.05 1.06 h. 2.83x
G2 2.01 0.88 2.36 h. 3.26x
G3 3.13 1.11 2.64 h. 7.08x
G4 2.6 1.14 3.14 h. 8.05x
Abhishek Incremental Power Grid Verication 20 / 32
Proposed Approach Results
Error Analysis
0 0.02 0.04 0.06 0.08 0.1
30
20
10
0
10
20
30
voltage drop (V)
r
e
l
a
t
i
v
e

e
r
r
o
r

(
%
)


3mV
Relative Error Plot (macromodeling)
Abhishek Incremental Power Grid Verication 21 / 32
Proposed Approach Results
Runtime Analysis
0 20 40 60 80 100
0
10
20
30
40
50
60
70
80
Size of Subgrid (% of Full Grid)
S
p
e
e
d

u
p

(
x
)


0 20 40 60
0
2
4
1
3


Using Efficient Bounds
After Macromodeling
Theoretical
Abhishek Incremental Power Grid Verication 22 / 32
Extensions Dimensionality Reduction
New Feasible Space
In the original approach, the internal current sources were not
physically moved to port nodes
Since port nodes are less in number, runtime savings can be a
result if internal current sources are replaced by current sources
at port nodes
A new feasible space in the modied current source conguration:

F =
_
i

s
: i
s
F, for which i

s
= (

Ji
s
)|

_
where = n
ext
+ n
prt
and the notation |

implies either rst

entries of vector argument or the rst elements of a matrix
argument
The upper bound can now be computed as:

v
ub
=
_
I +G
1 C
t
_
_
_
I
ext
0 0
0 I
prt
0
0 T
T
A
1
int
_
_
_
emax
i

F
(

A
1
|

s
)
i
L,int
_
Abhishek Incremental Power Grid Verication 23 / 32
Extensions Dimensionality Reduction
Dening

F

F can be dened by nding the convex hull of the points lying

inside the space that is computationally very expensive
An approximate algorithm to compute multidimensional convex
hull of the points in space was proposed by Xu et al. [AMC 98]
Choose direction vectors that are distributed regularly on the unit
hypersphere
Maximize and minimize the inner product over all points inside

F
Above algorithm is modied to better approximate the space

F
Direction vectors are chosen based on transformation matrix and
original constraint matrix
Since extreme points of

F are not known, optimization operations
are done in F
Abhishek Incremental Power Grid Verication 24 / 32
Extensions Dimensionality Reduction
Experimental Results

1
= 0.1mV
2
= 0.01mV = 5ps = 5 10
3

Flat Original Modified

0
50
100
150
200
250
300
350
400


R
u
n
t
i
m
e

(
m
i
n
u
t
e
s
)
Verification Approaches
Original Modified
0
20
40


SPAI
Macro
LP
Abhishek Incremental Power Grid Verication 25 / 32
Extensions Dimensionality Reduction
Error Analysis
Relative Error Plot (modied approach)
Abhishek Incremental Power Grid Verication 26 / 32
Extensions Chip Power Model
Introducing CPM
Abhishek Incremental Power Grid Verication 27 / 32
CPM is a reduced order model that captures the electrical
behavior of the on-chip power grid
Such models are used to design the chip-package PDNs while
taking into account the behavior of on-chip interconnects
Similar to incremental verication:
Verify only the package (external) nodes
Macromodel the on-chip network (sub-grid)
V
dd
V
dd
RLC Package Interconnections RC On-chip Interconnections
Extensions Chip Power Model
Constructing CPM in Vectorless Verication Context
Incremental verication is adapted to RLC verication context
The lower and upper bounds on worst-case voltage drops at time
t = r t after macromodeling can be expressed as:
_

w
r ,ext

w
r ,prt
_
=
_

w
r 1,ext

w
r 1,prt
_
+ eopt
i

r t
[((

D
1

E)
r 1

D
1
)|

s
]
_
w
r ,int ,max

_
A
1
int
C
int
t
_
r 1
A
1
int
i
L,int
+T
T
r t

w
r ,prt ,max
w
r ,int ,min
T
T
r t

w
r ,prt ,min
_
where i

s
is the -vector of modied current source conguration,

r t
is an approximation for the new feasible space at t = r t
with the transformation matrix given by:
T
r t
= G
23
_
A
1
int
C
int
t
_
r 1
A
1
int
A
int
T
T
r t
=
C
T
int
t
T
T
(r 1)t
T
r t
can be computed iteratively by using the above relation
Abhishek Incremental Power Grid Verication 28 / 32
Extensions Chip Power Model
Experimental Results

1
= 0.1mV
2
= 0.01mV = 5ps = 5 10
3

Speed and accuracy after constructing the CPM using Approach I

Power Grid On-chip Grid Max Error (mV) Avg. % Error Speed
Name n n
int
n
prt
v
ub
v
lb
v
ub
v
lb
Up
A1 13,905 12,577 664 4 2.6 8.8 1.2 18.16x
A2 24,548 22,208 1,170 5.5 4 10.2 5.1 13.36x
A3 34,183 30,925 1,629 10.9 3.2 12.8 4.3 10.95x
A4 52,968 47,920 2,524 11.19 3.2 12.9 2.7 11.83x
Approaches to Construct CPM
Name Construct T
r t
Moving Current Sources Speed-up Rank Accuracy
Approach I Iterative Modied I II
Approach II SPAI Modied III II
Approach III Iterative Original II I
Relatively: I = best, II = better, III = good
Abhishek Incremental Power Grid Verication 29 / 32
Extensions Chip Power Model
Runtime Analysis
A1 A2 A3 A4
0
1
2
3
4
5
6
7
Test Grids
R
u
n
t
i
m
e

(
h
o
u
r
s
)


Flat
Approach I
Approach II
Approach III
Abhishek Incremental Power Grid Verication 30 / 32
Conclusions
To Sum Up
Power grid verication is essential to design verication
Constraints-based verication allows for early verication of the
power grids
We proposed a vectorless approach for incremental grid
verication for conductive-only and RC grid models:
It provides the ability to efciently perform verication of a part of
the grid
It reduces the size of the problem by macromodeling the sub-grid
It can efciently compute the upper bounds vector without verifying
the internal nodes
We also applied this approach to construct Chip Power Model for
on-chip interconnects that provide an efcient way to design the
package while considering the behavior of on-chip PDN.
Abhishek Incremental Power Grid Verication 31 / 32
Thank You
Questions
Abhishek Incremental Power Grid Verication 32 / 32