8051 Microcontrollers: MCS 51 and its Variants- Prof.

Satish Shah Variants-

Interrupts
An interrupt is the occurrence of a condition/event that causes a temporary suspension of a program while the condition is serviced by another program This allows us to deal with an event asynchronously while another program is executing The program that deals with an interrupt is called an ISR or an interrupt handler

8051 Microcontrollers: MCS 51 and its Variants- Prof. Satish Shah Variants-

Interrupts

When an interrupt occurs and is accepted by the CPU, then following events occur The current instruction completes execution The PC (IP) is saved on the stack The PC is loaded with the vector address of the ISR The ISR executes ISR executes and takes action in response to the interrupt ISR finishes with a RETI instruction

8051 Microcontrollers: MCS 51 and its Variants- Prof. Satish Shah Variants-

Interrupts: Priority& IP Register

Bit IP.7 IP.6 IP.5 IP.4 IP.3 IP02 IP.1 IP.0

Each interrupt source is individually programmed to be either High or Low priority Priorities allow an ISR to be interrupted by an interrupt of Higher priority than the one currently being serviced A higher priority ISR cannot be interrupted The main program executing at the base level can always be interrupted
Symbol PT2 PS PT1 PX1 PT0 PX0 Bit Address 0BDH 0BCH 0BBH 0BAH 0B9H 0B8H Description Undefined Undefined Priority for Timers 2 int(8052) Priority for serial port int Priority for Timer 1 int Priority for External 1 int Priority for Timer 0 int Priority for External 0 int

Interrupt Vector Table

Interrupt Reset Ext 0 Timer 0 Ext 1 Timer 1 Serial Port Timer 2 Flag RST IE0 TF0 IE1 TF1 RI or TI TF2or EXF2 Vector Address 0000H 0003H 000BH 0013H 001BH 0023H 002BH

8051 Microcontrollers: MCS 51 and its Variants- Prof. Satish Shah Variants-

Interrupts: IE Register
EA
Bit
IE.7 IE6 IE.5 IE.4 IE.3

---Symbol
EA ----ET2 ES ET1

ET2
Function

ES

ET1

EX1

ET0

EX0

Enable interrupts bit. Cleared to 0 by program to disable all interrupts; set to 1 to permit individual interrupts to be enabled by their enable bits. Not implemented Reserved for future use. Enable serial port interrupt. Set to 1 by program to enable serial Port interrupt; cleared to 0 to disable serial port interrupt. Enable timer 1 overflow interrupt. Set to 1 by program to enable timer 1 overflow interrupt; cleared to 0 to disable timer 1 overflow interrupt. Enable external interrupt 1. set to 1 program to enable INT1bar interrupt; cleared to 0 to disable INT1 bar interrupt. Enable timer 0 overflow interrupt. Set to 1 by program to enable timer 0 overflow interrupt; cleared to 0 to disable timer 0 overflow interrupt. Enable external interrupt 0. set to 1 by program to enable INT0bar Interrupt; cleared to 0 to disable INT0bar interrupt.

IE.2 IE.1 IE.0

EX1 ET0 EX0

Bit addressable as IE.0 to IE.7