Sei sulla pagina 1di 32

CSE325 Principles of Operating Systems

Computer System Overview

David Duggan

dduggan@sandia.gov

CSE325 Principles of Operating Systems Computer System Overview David Duggan dduggan@sandia.gov January 20, 2011

January 20, 2011

What is a Computer System?

What is a Computer System? 1/19/2011 CSE325 - Computer System 2

Computer System Functional Areas

Computer System Functional Areas 1/19/2011 CSE325 - Computer System 3

Major Computer Components

Major Computer Components 1/19/2011 CSE325 - Computer System 4

1/19/2011

CSE325 - Computer System
CSE325 - Computer System

4

Processor

Internal registers

Memory address register (MAR)

Specifies the address for the next read or write

Memory buffer register (MBR)

Contains data written into memory or receives data read from memory

I/O address register

I/O buffer register

User-Visible Registers

May be read by user processes

Available to all programs - application programs and system programs

Types of registers

programs and system programs  Types of registers  Data  Address  Index  Segment

Data

Address

Index

Segment pointer

Stack pointer

Control and Status Registers

Program Counter (PC)

Contains the address of an instruction to be fetched

Instruction Register (IR)

Contains the instruction most recently fetched

Program Status Word (PSW)

Condition codes

Interrupt enable/disable

Supervisor/user mode

)  Condition codes  Interrupt enable/disable  Supervisor/user mode 1/19/2011 CSE325 - Computer System 7

Simple Instruction Cycle

Simple Instruction Cycle 1/19/2011 CSE325 - Computer System 8

Interrupts

Suspends the normal sequence of execution

Used to improve processor utilization

Interrupt Cycle

Interrupt Cycle 1/19/2011 CSE325 - Computer System 10

Interrupt Timeline

Interrupt Timeline 1/19/2011 CSE325 - Computer System 11

Simple Interrupt Processing

1/19/2011

CSE325 - Computer System
CSE325 - Computer System

12

Multiple Interrupts

Disable interrupts while an interrupt is being processed

1/19/2011

CSE325 - Computer System
CSE325 - Computer System

13

Multiple Interrupts (Cont.)

Define priorities for interrupts

Multiple Interrupts (Cont.)  Define priorities for interrupts 1/19/2011 CSE325 - Computer System 14

Data Transfer on the Bus

CPU cache Memory memory bus I/O bus disk Net interface
CPU
cache
Memory
memory bus
I/O bus
disk
Net interface

cache-memory: cache misses, write-through/write-back

memory-disk: swapping, paging, file accesses

memory-network Interface : packet send/receive

I/O devices to the processor: interrupts

15

Two I/O Methods

Synchronous

Asynchronous

Two I/O Methods Synchronous Asynchronous 1/19/2011 CSE325 - Computer System 16

I/O Operation: Synchronous vs. Asynchronous

After I/O starts, control returns to user program only upon I/O completion

Wait instruction idles the CPU until operation completes

Wait loop (contention for memory access?)

At most one I/O request is outstanding at a time, no simultaneous I/O processing

After I/O starts, control returns to user program without waiting for I/O completion

System call – request to the operating system to allow user to wait for I/O completion

Device-status table contains entry for each I/O device indicating its type, address, and state

Operating system indexes into I/O device table to determine device status and to modify table entry to include interrupt

17

Programmed I/O

I/O module performs the action, not the processor

Sets appropriate bits in the I/O status register

No interrupts occur

Processor checks status until operation is complete

No interrupts occur  Processor checks status until operation is complete 1/19/2011 CSE325 - Computer System

Interrupt-Driven I/O

Processor is interrupted when I/O module ready to exchange data

Processor is free to do other work

No needless waiting

Consumes a lot of processor time because every byte read or written passes through the processor

processor time because every byte read or written passes through the processor 1/19/2011 CSE325 - Computer

Direct Memory Access (DMA)

Used for high-speed I/O devices able to transmit information at close to memory speeds.

Device controller transfers blocks of data from buffer storage directly to main memory without CPU intervention.

Only one interrupt is generated per block, rather than the one interrupt per byte.

Programming a DMA transfer

address of the I/O buffer

starting location in memory

number of bytes

direction of transfer (read/write from/to memory)

Bus arbitration between cache-memory and DMA transfers

Memory cache must be consistent with DMA

20

Storage-Device Hierarchy

Storage-Device Hierarchy  Decreasing cost per bit  Increasing capacity  Increasing access time  Decreasing

Decreasing cost per bit

Increasing capacity

Increasing access time

Decreasing frequency of access of the memory by the processor

Locality of reference

Increase size of the transfer unit

the processor  Locality of reference  Increase size of the transfer unit 1/19/2011 CSE325 -

Storage Hierarchy

Storage systems organized in hierarchy.

Speed

Cost

Volatility

Caching – copying information into faster storage system; main memory can be viewed as a last cache for secondary storage.

Performance of Various Levels of Storage

Movement between levels of storage hierarchy can be explicit or implicit

 Movement between levels of storage hierarchy can be explicit or implicit 1/19/2011 CSE325 - Computer

Cache-Memory Transfers

Cache-Memory Transfers 1/19/2011 CSE325 - Computer System 24

Cache Memory

The mismatch between processor and memory speed

closer to the processor than the main memory; smaller and faster than the main memory

contains the value of main memory locations that were recently accessed (temporal locality)

transfer between caches and main memory is performed in units called cache blocks/lines

contains also the value of memory locations that are close to locations which were recently accessed (spatial locality)

Cache performance: miss ratio, miss penalty, average access time

invisible to the OS, operated by the hardware/firmware

miss penalty, average access time  invisible to the OS, operated by the hardware/firmware CSE325 -

CSE325 - Computer System

25

Cache/Main Memory System

1/19/2011 CSE325 - Computer System
1/19/2011
CSE325 - Computer System

26

Cache Read Operation

CSE325 - Computer System
CSE325 - Computer System

1/19/2011

27

Cache Design

Mapping function

Determines which cache location the block will occupy

Direct-mapped vs. fully-associative vs. set- associative

Conflict misses

Replacement algorithm

Determines which block to replace

Least-Recently-Used (LRU) algorithm

Cache Design (Cont.)

Write policy

When the memory write operation takes place

Can occur every time block is updated: write through

Can occur only when block is replaced: write back

Minimizes memory write operations

Leaves main memory in an obsolete state

Disk Cache/Buffer Cache

A portion of main memory used as a buffer to temporarily to hold data for the disk

Disk writes are clustered

Some data written out may be referenced again. The data are retrieved rapidly from the software cache instead of slowly from disk

Multiprocessors

CPU CPU cache cache Memory memory bus I/O bus disk Net interface
CPU
CPU
cache
cache
Memory
memory bus
I/O bus
disk
Net interface

more than one processor on the same bus

memory is shared among processors-- cache coherency

goal: performance speedup

single-image operating systems

Multi-core processors (chip-level multiprocessors/CMP)

31

Clusters of Computers

CPU cache Memory memory bus I/O bus disk Net interface
CPU
cache
Memory
memory bus
I/O bus
disk
Net interface
CPU cache Memory memory bus I/O bus disk Net interface CPU cache Memory memory bus I/O
CPU cache Memory memory bus I/O bus Net interface
CPU
cache
Memory
memory bus
I/O bus
Net interface

disk

network

Memory memory bus I/O bus Net interface disk network  network of computers: “share-nothing” 

network of computers: “share-nothing”

communication through message-passing

fast interconnects: memory-to-memory communication

goals: performance and availability

each system runs its own operating system

32