DSP New Manual1

MOTHER TERASA COLLEGE OF ENGINEERING & TECHNOLOGY Mettusalai,Illupur
EC1315- DIGITAL SIGNAL PROCESSING LABORATORY
2012-13/ODD/V/DSP/LM
Page 1
EC1315 DIGITAL SIGNAL PROCESSING LABORATORY LIST OF EXPERIMENTS USING TMS320C5X
LTPC 0032
1) Study of various addressing modes of DSP using simple programming examples 2) Sampling of input signal and display 3) Implementation of FIR filter 4) Calculation of FFT USING MATLAB 1) Generation of signals 2) Linear and circular convolution of two sequences 3) Sampling and effect of aliasing 4) Design of FIR filters 5) Design of IIR filters 6) Calculation of FFT of a signal
LIST OF EQUIPMENTS Description of Equipment Quantity 1. MATLAB with 5 User Licenses 1 2. TMS 320 C 5X Trainer Kit 3 3. Cathode Ray Oscilloscope 3 4. Function Generator (1 MHzRange) 2 5 With adequate number of PCs and Printer
Page 2
LIST OF EXPERIMENTS
SI.NO 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.
EXPERIMENTS GENERATION OF BASIC SIGNALS DISCRETE CONVOLUTION FAST FOURIER TRANSFORM SAMPLING DESIGN OF FIR FILTER DESIGN OF IIR FILTER STUDY OF TMS320C50 ARCHITECTURE STUDY OF TMS320C5416 ARCHITECTURE ARITHMETIC OPERATION SAMPLING OF INPUT SIGNAL AND DISPLAY IMPLEMENTATION OF FIR FILTER CALCULATION OF FFT WAVEFORM GENERATION TABLE DATA TRANSFER
Page 3
INDEX EXP.NO 1. DATE TITLE GENERATION OF BASIC SIGNALS a. Unit step signal b. Unit impulse signal c. Unit ramp signal d. Unit exponential signal i)Growing exponential ii)decaying exponential e. Sinusoidal signal f. Cosine signal PAGE NO MARKS SIGNATURE
2.
DISCRETE CONVOLUTION a. Linear Convolution b. Circular Convolution FAST FOURIER TRANSFORM SAMPLING a.Up sampling b.Down sampling using MATLAB DESIGN OF FIR FILTER a. Rectangular window b. Hamming window c. Kaiser window DESIGN OF IIR FILTER
3. 4.
5.
6. a.low pass, b.high pass, c.band pass and d.band stop filters
Page 4
7. 8. 9. 10. 11. 12. 13. 14.
STUDY OF TMS320C50 ARCHITECTURE STUDY OF TMS320C5416 ARCHITECTURE ARITHMETIC OPERATION SAMPLING OF INPUT SIGNAL AND DISPLAY IMPLEMENTATION OF FIR FILTER CALCULATION OF FFT WAVEFORM GENERATION TABLE DATA TRANSFER
Page 5
EXP.NO:1 DATE: GENERATION OF BASIC SIGNALS Aim: To plot the basic signals in discrete time (DT) form using MATLAB in a single page. a) Unit step signal b) Unit impulse signal c) Unit ramp signal d) Unit exponential signal i)Growing exponential ii)decaying exponential e) Sinusoidal signal f) Cosine signal Apparatus required: 1. Personnel Computer 2. MATLAB Software Algorithm 1. Enter the range of the unit step signal 2. Generate the step signal as defined by u (n) = 1 ; n 0 0; n<0 3. Enter the range of the Impulse signal. 4. Generate the impulse signal as defined by (n) = 1; 0; 5. Enter the range of the ramp signal. 6. Generate the ramp signal as defined by r (n) = n; n 0 0; n<0 n =0 n0
Page 6
7. Enter the range of the exponential signal Generate the exponential signal as defined by y (n)=a^n For growing exponential a>1 For decaying exponential a<1 8. Generate the sinusoidal signal as defined by s (n) = A sin (2*pi*f*t), where A is the amplitude of the signal. 9. Generate the cosine signal as defined by s(n) = A cos (2*pi*f*t), where A is the amplitude of the signal
a.Unit Step Signal Program: clc; clear all; close all; a=input('Enter the range'); n=-a:1:a; y=[zeros(a,1);ones(a+1,1)]; disp(y); stem(n,y); xlabel('Samples'); ylabel('amplitudes'); title('Unit step signal');
Page 7
Input: Enter the range:4 Output: 0 0 0 0 1 1 1 1 1
Page 8
b. Unit Impulse Signal: Program: clc; clear all; close all; a=input('Enter the range'); n=-a:1:a; y=[zeros(a,1);ones(1,1);zeros(a,1)]; disp(y); stem(n,y); xlabel('Samples'); ylabel('Amplitude'); title('Unit impulse signal');
Page 9
Output: Enter the range:4 0 0 0 0 1 0 0 0 0
Page 10
c.Unit ramp signal: Program: clc; clear all; close all; a=input('Enter the range'); for[n=-a:1:a]; y(n+a+1,1)=n; end; n=-a:1:a; disp(y); stem(n,y); xlabel('Samples'); ylabel('amplitudes'); title('Unit ramp signal');
Page 11
Input: Enter the range:4 Output: -4 -3 -2 -1 0 1 2 3 4
Page 12
d.Exponential signal: i.Growing Exponential Signal: Program: clc; clear all; close all; b=input('Enter the range'); a=input('Enter the constant(a>1)'); for(n=-b:1:b); y(1,n+b+1)=a^n; end; n=-b:1:b; disp(y); stem(n,y); xlabel('Samples'); ylabel('amplitudes'); title('Growing exponential signal');
Page 13
Input: Enter the range:4 Enter the constant(a>1):2 Output: Columns 1 through 5 0.0625 0.1250 0.2500 0.5000 1.0000 Columns 6 through 9 2.0000 4.0000 8.0000 16.0000
Page 14
d.Exponential Signal: ii.Decaying Exponential Signal: Program: clc; clear all; close all; b=input('Enter the range'); a=input('Enter the constant(a<1)'); for(n=-b:1:b); y(1,n+b+1)=a^n; end; n=-b:1:b; disp(y); stem(n,y); xlabel('Samples'); ylabel('amplitudes'); title('decaying exponential signal');
Page 15
Input: Enter the range: 4 Enter the constant(a<1): 0.2 Output: Columns 1 through 5 625.0000 125.0000 25.0000 5.0000 1.0000 Columns 6 through 9 0.2000 0.0400 0.0080 0.0016
Page 16
e.Sinusoidal signal: Program: clc; clear all; close all; a=input('Enter the amplitude'); f=input('Enter the frequency'); t=0:0.1:2*pi; y=a*sin(2*pi*f*t); subplot(2,1,1); plot(t,y); xlabel('Samples'); ylabel('amplitudes'); title('continous time signal'); subplot(2,1,2); stem(t,y); xlabel('Samples'); ylabel('amplitudes'); title('Discrete time signal');
Page 17
Input: Enter the maximum frequency:.5 Enter the sampling frequency:10 Enter the sampling factor:2
Page 18
f.Cosine signal: Program: clc; clear all; close all; a=input('Enter the amplitude'); f=input('Enter the frequency'); t=0:0.1:2*pi; y=a*cos(2*pi*f*t); subplot(2,1,1); plot(t,y); xlabel('Samples'); ylabel('amplitudes'); title('continous time signal'); subplot(2,1,2); stem(t,y); xlabel('Samples'); ylabel('amplitudes'); title('Discrete time signal');
Page 19
Input: Enter the amplitude:4 Enter the frequency:0.2 Output:
Page 20
Result: Thus the basic signal were generated and plotted using MATLAB program. 2012-13/ODD/V/DSP/LM Page 21
EXP.NO:2 DATE: DISCRETE CONVOLUTION AIM: To find and plot the discrete convolution of two sequences using MATLAB program. a. Linear Convolution b. Circular Convolution Apparatus Required: 1. PC 2. MATLAB Software Algorithm: a) Linear Convolution: 1. Get the two input sequences x1(n) and x2(n) in matrix form. 2. Perform the linear convolution by the formula, y(n) = x1(k) x2(n-k) 3.Check the length of the convolved signal by the formula N3=N1+N2-1,where N1 is the length of x1(n) and N2 is the length of x2(n). 4. Display the output 5. Plot the input and convolved sequences. b) Circular Convolution 1. Get the two input sequences (n) and h (n) in matrix form. 2. Check for equal length sequences. If it is equal perform circular convolution, otherwise convert it into equal length sequences by adding zeros. 3. Obtain the maximum length of the two sequences. This gives the length of the circular convolved sequence. 4. Obtain the difference between the two sequence length, i.e. n3=n1-n2, where n1 is length of g(n) and n2 is length of h(n). 5. Add n3 zeros with smaller sequence. 6. Calculate the circular convolution by matrix method. 7. Display the output 8. Plot the input and convolved sequences.
Page 22
a.Linear convolution: clc; clear all; close all; x=input('Enter the input sequence:'); h=input('Enter the impulse sequence:'); y=conv(x,h); subplot(3,2,1); stem(x); xlabel('n'); ylabel('x(n)'); title('Input sequence'); subplot(3,2,2); stem(h); xlabel('n'); ylabel('h(n)'); title('Impulse sequence'); subplot(3,1,3); stem(y); xlabel('n'); ylabel('y(n)'); title('linear convolution');
Page 23
Input: Enter the input sequence:[4 3 2 1] Enter the impulse sequence:[ 1 2 3] Output:
Page 24
b.Circular convolution: clc; clear all; close all; x1=input('Enter the first sequence:'); x2=input('Enter the second sequence:'); n=length(x1); m=length(x2); if(n>m); for(n=m+1:1:n); x2(1,n)=0; end; else(n<m); for(n=n+1); x1(1,n); end; end; yk=fft(x1).*fft(x2); y=ifft(yk); subplot(3,2,1); stem(x1); xlabel('n'); ylabel('x1(n)'); title('first sequence'); subplot(3,2,2); stem(x2); xlabel('n'); ylabel('x2(n)'); title('second sequence'); subplot(3,1,3); stem(y); xlabel('n'); ylabel('y(n)'); title('circular convolution');
Page 25
Input: Enter the first sequence:[1 2 3 4] Enter the second sequence:[2 3 5] Output:
Page 26
Result: 2012-13/ODD/V/DSP/LM Page 27
Thus the discrete convolution of two sequences was found and plotted using MATLAB program. EXP.NO:3 DATE: FAST FOURIER TRANSFORM Aim: To find the Fast Fourier transform of the given input sequence using MATLAB commands. Requirements: 1. PC 2. MATLAB Software Algorithm: FFT 1. 2. 3. 4. Enter the input sequence and the length of the input sequence. Get the output sequence using FFT formula. Display the output Plot magnitude response and phase response of output sequence
Algorithm: IFFT 1. 2. 3. 4. Enter the input sequence and the length of the input sequence. Get the output sequence using IFFT formula Display the output Plot magnitude response of input sequence and phase response of output sequence
Page 28
Fast Fourier transform: clc; clear all; close all; xn=input('Enter the input sequence:'); N=length(xn); for(k=0:1:N-1) sum=0; for(n=0:1:N-1) sum=sum+(xn(1,n+1)*exp(-i*2*pi*n*k/N)); end; xk(1,k+1)=sum; end; subplot(3,2,1); stem(xn); xlabel('n'); ylabel('Magnitude'); title('Input sequence'); subplot(3,2,2); stem(abs(xk)); disp(abs(xk)); xlabel('n'); ylabel('Magnitude'); title('Magnitude response of FFT'); subplot(3,1,3); stem(angle(xk)); disp(angle(xk)) xlabel('n'); ylabel('Phase'); title('Phase response of FFT');
Page 29
Input: Enter the input sequence:[2 3 4 5] Output: 14.0000 2.8284 2.0000 2.8284 2.3562 -3.1416 -2.3562 0 2.3562 -3.1416 -2.3562
Page 30
Inverse Fast Fourier Transform: clc; clear all; close all; xk=input('Enter the input sequence:'); N=length(xk); for(n=0:1:N-1) sum=0; for(k=0:1:N-1) sum=sum+(xk(1,k+1)*exp(i*2*pi*n*k/N)/N); end; xn(1,n+1)=sum; end; subplot(3,2,1); stem(abs(xk)); disp(abs(xk)); xlabel('n'); ylabel('Magnitude'); title('Magnitude response of FFT'); subplot(3,2,2); stem(angle(xk)); disp(angle(xk)) xlabel('n'); ylabel('Phase'); title('Phase response of FFT'); subplot(3,1,3); stem(abs(xn)); disp(abs(xn)); xlabel('n'); ylabel('Magnitude'); title('Inverse fast fourier transform');
Page 31
Input: Enter the input sequence:[14 -2+2i -2 -2-2i] Output: 14.0000 2.8284 2.0000 2.8284 0 2.3562 3.1416 -2.3562 2 3 4 5
Page 32
Result: Thus the Fast Fourier transform and Inverse Fast Fourier transform of two sequences was found and output was plotted using MATLAB. 2012-13/ODD/V/DSP/LM Page 33
EXP.NO:4 DATE: SAMPLING Aim: To sample the sinusoidal signal and show the effect of aliasing on sampled signal by following methods a. Up sampling b. Down sampling using MATLAB program. Requirements: 1. PC 2. MATLAB Software Algorithm: a. Up sampling 1. Enter the maximum frequency. 2. Enter the sampling frequency . 3. Enter the sampling factor. 4. Plot the sinusoidal waveform using formula sin(2*pi*fm*t). 5. Plot the up sampled waveform using formula up sample() b. Down sampling
1. Enter the maximum frequency. 2. Enter the sampling frequency . 3. Enter the sampling factor. 4. Plot the sinusoidal waveform using formula sin(2*pi*fm*t). 5. Plot the down sampled waveform using formula down sample()
Page 34
a.Upsampling (Without Alaising ): program: clc; clear all; close all; fm=input('Enter the maximum frequency:'); fs=input('Enter the sampling frequency:'); s=input('Enter the sampling factor:'); t=0:1/fs:2*pi; y=sin(2*pi*fm*t); subplot(2,1,1); plot(t,y); xlabel('t->'); ylabel('y->'); title('signal to be sampled:'); y1=upsample(y,s); subplot(2,1,2); stem(y1); xlabel('t->'); ylabel('y->'); title('sample without alaising');
Page 35
Input: Enter the maximum frequency:.4 Enter the sampling frequency:10 Enter the sampling factor:4
Page 36
Downsampling ( With Aliasing): program: clc; clear all; close all; fm=input('Enter the maximum frequency:'); fs=input('Enter the sampling frequency:'); s=input('Enter the sampling factor:'); t=0:1/fs:2*pi; y=sin(2*pi*fm*t); subplot(2,1,1); plot(t,y); xlabel('t->'); ylabel('y->'); title('signal to be sampled:'); y1=downsample(y,s); subplot(2,1,2); stem(y1); xlabel('t->'); ylabel('y->'); title('sample with alaising');
Page 37
OUTPUT Enter the maximum frequency:0.5 Enter the sampling frequency:10 Enter the sampling factor:5
Page 38
Result: Thus the sinusoidal signal was sampled and its effect of aliasing was shown by up sampling and down sampling methods using MATLAB program.
Page 39
EXP.NO:5 DATE: DESIGN OF FIR FILTER AIM: To design FIR low pass, high pass, band pass and band stop filters by following techniques a. Rectangular window b. Hamming window c. Kaiser window Requirements: 1.PC 2. MATLAB software Algorithm: a.Rectangular window 1. Enter the number of samples 2. Find the window coefficients 3. Find the finite impulse response of the all filters. 4. Plot the magnitude response of all filters. b.Hamming window 1.Enter the number of samples 2.Find the window coefficients 3.Find the finite impulse response of the all filters. 4.Plot the magnitude response of all filters. c.Kaiser window 1. Get the pass band and stop band ripples. 2. Get the pass band and stop band edge frequencies. 3. Get the sampling frequency. 4. Get the beta value. 5. Calculate the order of the filter 6. Find the window coefficients. 7. Plot the magnitude response
Page 40
RECTANGULAR WINDOW: Program: clc; clear all; close all; N=input('Enter the number of samples:'); wc=.2*pi; n=0:1:(N-1); alp=(N-1)/2; w=0:.01:pi; eps=0.001; wr=boxcar(N); %Low pass filter hd=[sin(wc*(n-alp+eps))]./(pi*(n-alp+eps)); hn=hd.*wr'; hz=freqz(hn,1,w); subplot(2,2,1); Plot (w,20*log(abs(hz))); xlabel('Frequency in radians'); ylabel('Magnitude in db'); title('Low pass filter'); %High pass filter hd=[sin(pi*(n-alp+eps))-sin(wc*(n-alp+eps))]./(pi*(n-alp+eps)); hn=hd.*wr'; hz=freqz(hn,1,w); subplot(2,2,2); plot(w,20*log(abs(hz))); xlabel('Frequency in radians'); ylabel('Magnitude in db'); title('High pass filter'); %Band pass filter wc1=.25*pi; wc2=.75*pi; hd=[sin(wc2*(n-alp+eps))-sin(wc1*(n-alp+eps))]./(pi*(n-alp+eps)); hn=hd.*wr'; hz=freqz(hn,1,w); subplot(2,2,3); plot(w,20*log(abs(hz))); xlabel('Frequency in radians'); ylabel('Magnitude in db'); title('Band pass filter'); %Band stop filter hd=[sin(wc1*(n-alp+eps))-sin(wc2*(n-alp+eps))+sin(pi*(n-alp+eps))]./(pi*(n-alp+eps)); hn=hd.*wr'; hz=freqz(hn,1,w); subplot(2,2,4); 2012-13/ODD/V/DSP/LM Page 41
plot(w,20*log(abs(hz))); xlabel('Frequency in radians'); ylabel('Magnitude in db'); title('Band stop filter');
OUTPUT: Enter the number of samples:25
Page 42
HAMMING WINDOW: clc; clear all; close all; N=input('Enter the number of samples:'); wc=.2*pi; n=0:1:(N-1); alp=(N-1)/2; w=0:.01:pi; eps=0.001; wh=hamming(N); %Low pass filter hd=[sin(wc*(n-alp+eps))]./(pi*(n-alp+eps)); hn=hd.*wh'; hz=freqz(hn,1,w); subplot(2,2,1); plot(w,20*log(abs(hz))); xlabel('Frequency in radians'); ylabel('Magnitude in db'); title('Low pass filter'); %High pass filter hd=[sin(pi*(n-alp+eps))-sin(wc*(n-alp+eps))]./(pi*(n-alp+eps)); hn=hd.*wh'; hz=freqz(hn,1,w); subplot(2,2,2); plot(w,20*log(abs(hz))); xlabel('Frequency in radians'); ylabel('Magnitude in db'); title('High pass filter'); %Band pass filter wc1=.25*pi; wc2=.75*pi; hd=[sin(wc2*(n-alp+eps))-sin(wc1*(n-alp+eps))]./(pi*(n-alp+eps)); hn=hd.*wh'; hz=freqz(hn,1,w); subplot(2,2,3); plot(w,20*log(abs(hz))); xlabel('Frequency in radians'); ylabel('Magnitude in db'); title('Band pass filter'); %Band stop filter hd=[sin(wc1*(n-alp+eps))-sin(wc2*(n-alp+eps))+sin(pi*(n-alp+eps))]./(pi*(n-alp+eps)); hn=hd.*wh'; hz=freqz(hn,1,w); subplot(2,2,4); plot(w,20*log(abs(hz))); 2012-13/ODD/V/DSP/LM Page 43
xlabel('Frequency in radians'); ylabel('Magnitude in db'); title('Band stop filter'); OUTPUT: Enter the number of samples:25
Page 44
KAISER WINDOW: clc; clear all; close all; rp=input('Enter the pass band ripple:'); rs=input('Enter the stop band ripple:'); wp=input('Enter the pass band ripple:'); ws=input('Enter the stop band frequency:'); fs=input('Enter the sampling frequency:'); beeta=input('Enter the sampling value:'); wc=(ws+wp)/2; wcr=(wc*2*pi)/fs; d=(rs-7.9)/14.36; b=ws-wp; N=[fs*(d/b)+1]; alp=(N-1)/2; n=0:1:(N-1); w=0:.01:pi; eps=0.001; wk=kaiser(N,beeta); %Low pass filter hd=[sin(wc*(n-alp+eps))]./(pi*(n-alp+eps)); hn=hd.*wk'; hz=freqz(hn,1,w); subplot(2,2,1); plot(w,20*log(abs(hz))); xlabel('Frequency in radians'); ylabel('Magnitude in db'); title('Low pass filter'); %High pass filter hd=[sin(pi*(n-alp+eps))-sin(wc*(n-alp+eps))]./(pi*(n-alp+eps)); hn=hd.*wk'; hz=freqz(hn,1,w); subplot(2,2,2); plot(w,20*log(abs(hz))); xlabel('Frequency in radians'); ylabel('Magnitude in db'); title('High pass filter'); %Band pass filter wc1=.25*pi; wc2=.75*pi; hd=[sin(wc2*(n-alp+eps))-sin(wc1*(n-alp+eps))]./(pi*(n-alp+eps)); hn=hd.*wk'; hz=freqz(hn,1,w); subplot(2,2,3); plot(w,20*log(abs(hz))); 2012-13/ODD/V/DSP/LM Page 45
xlabel('Frequency in radians'); ylabel('Magnitude in db'); title('Band pass filter'); %Band stop filter hd=[sin(wc1*(n-alp+eps))-sin(wc2*(n-alp+eps))+sin(pi*(n-alp+eps))]./(pi*(n-alp+eps)); hn=hd.*wk'; hz=freqz(hn,1,w); subplot(2,2,4); plot(w,20*log(abs(hz))); xlabel('Frequency in radians'); ylabel('Magnitude in db'); title('Band stop filter');
Page 46
OUTPUT: Enter the pass band ripple:.2 Enter the stop band ripple:50 Enter the pass band ripple:100 Enter the stop band frequency: 150 Enter the sampling frequency: 400 Enter the sampling value: .04
Page 47
Result: Thus the FIR low pass, high pass, band pass and band stop filters were designed by windowing techniques using MATLAB program. 2012-13/ODD/V/DSP/LM Page 48
EXP.NO:6 DATE: DESIGN OF IIR FILTER AIM: To design IIR low pass, high pass, band pass and band stop filters (Butterworth) using MATLAB program. Requirements: 1. PC 2. MATLAB software Algorithm: 1. Get the pass band and stop band ripples. 2. Get the pass band and stop band edge frequencies. 3. Get the sampling frequency. 4. Calculate the order of the filter 5. Find the filter coefficients. 6. Plot the magnitude and phase response.
Page 49
Low pass filter; clc; clear all; close all; rp=input('Enter the pass band ripple:'); rs=input('Enter the stop band ripple:'); fp=input('Enter the pass band frequency:'); fs=input('Enter the stop band frequency:'); f=input('Enter the sampling frequency:'); w1=(2*fp)/f; w2=(2*fs)/f; [n,wc]=buttord(w1,w2,rp,rs,'s'); [b,a]=butter(n,wc,'low','s'); w=0:.01:pi; [h,omega]=freqs(b,a,w); m=20*log(abs(h)); theta=angle(h); subplot(2,1,1); plot(omega,m); xlabel('Normalized frequency'); ylabel('Gain in db'); title('Magnitude response'); subplot(2,1,2); plot(omega,theta); xlabel('Normalized frequency'); ylabel('Gain in db'); title('Phase response');
Page 50
Input: Enter the pass band ripple:.2 Enter the stop band ripple:40 Enter the pass band frequency:100 Enter the stop band frequency:150 Enter the sampling frequency:400
Page 51
High pass filter: clc; clear all; close all; rp=input('Enter the pass band ripple:'); rs=input('Enter the stop band ripple:'); fp=input('Enter the pass band frequency:'); fs=input('Enter the stop band frequency:'); f=input('Enter the sampling frequency:'); w1=(2*fp)/f; w2=(2*fs)/f; [n,wc]=buttord(w1,w2,rp,rs,'s'); [b,a]=butter(n,wc,'high','s'); w=0:.01:pi; [h,omega]=freqs(b,a,w); m=20*log(abs(h)); theta=angle(h); subplot(2,1,1); plot(omega,m); xlabel('Normalized frequency'); ylabel('Gain in db'); title('Magnitude response'); subplot(2,1,2); plot(omega,theta); xlabel('Normalized frequency'); ylabel('Gain in db'); title('Phase response');
Page 52
Page 53
Band pass filter: clc; clear all; close all; rp=input('Enter the pass band ripple:'); rs=input('Enter the stop band ripple:'); fp=input('Enter the pass band frequency:'); fs=input('Enter the stop band frequency:'); f=input('Enter the sampling frequency:'); w1=(2*fp)/f;w2=(2*fs)/f; [n]=buttord(w1,w2,rp,rs,'s'); [wc]=[w1,w2]; [b,a]=butter(n,wc,'bandpass','s'); w=0:.01:pi; [h,omega]=freqs(b,a,w); m=20*log(abs(h)); theta=angle(h); subplot(2,1,1); plot(omega,m); xlabel('Normalized frequency'); ylabel('Gain in db'); title('Magnitude response'); subplot(2,1,2); plot(omega,theta); xlabel('Normalized frequency'); ylabel('Gain in db'); title('Phase response');
Page 54
INPUT: Enter the pass band ripple:.2 Enter the stop band ripple:40 Enter the pass band frequency:100 Enter the stop band frequency:150 Enter the sampling frequency:400
Page 55
Bandstop filter: clc; clear all; close all; rp=input('Enter the pass band ripple:'); rs=input('Enter the stop band ripple:'); fp=input('Enter the pass band frequency:'); fs=input('Enter the stop band frequency:'); f=input('Enter the sampling frequency:'); w1=(2*fp)/f;w2=(2*fs)/f; [n]=buttord(w1,w2,rp,rs,'s'); [wc]=[w1,w2]; [b,a]=butter(n,wc,'stop','s'); w=0:.01:pi; [h,omega]=freqs(b,a,w); m=20*log(abs(h)); theta=angle(h); subplot(2,1,1); plot(omega,m); xlabel('Normalized frequency'); ylabel('Gain in db'); title('Magnitude response'); subplot(2,1,2); plot(omega,theta); xlabel('Normalized frequency'); ylabel('Gain in db'); title('Phase response');
Page 56
Page 57
Result: Thus the IIR low pass, high pass, band pass and band stop filters (Butterworth) were designed using MATLAB program. 2012-13/ODD/V/DSP/LM Page 58
EXP.NO:7 DATE: STUDY OF TMS320C50 ARCHITECTURE AIM: To study the architecture TMS320C50 fixed point processor Introduction: It is needless to say that in order t utilize the feature of the DSP chip TMS320C50, the DSP engineer must have a complete knowledge of the DSP device. this chapter is an introduction to the hardware aspects of the TMS320C50. the important units of TMS320C50 are discussed THE DSP CHIP TMS320C50: The TMS320C50 is a 16-bit fixed point digital signal processor that combines the flexibility of a high speed controller with the numerical capability of an array processor, thereby offering an inexpensive alternative to multichip bit-processors. The highly paralleled architecture and efficient instruction set, provide speed and flexibility capable of executing 10 MIPS(Million Instructions Per Second) The TMS320C50 optimizes speed by implementing functions in hardware that other processors implement through microcode or software. this hardware intensive approach provides the design engineer with processing power previously unavailable on a single chip. The TMS320C50 is the third generation digital signal processor in the TMS320 family. its powerful instruction set, inherent flexibility, high-speed number-crunching capabilities, and innovative architecture have made this high-performance, cost-effective processor the ideal solution to many telecommunication, computer, commercial, industrial, and military applications. KEY FEATURES OF TMS320C50: The key features of the digital signal processor TMS320C50 are: * 35-/50-ns single-cycle fixed-point instruction execution time (28.6/20 MIPS) * Upward source-code compatible with all C1X and C2X devices * RAM-based memory operation (C50) *9k x 16-bit single-cycle on-chip program/data RAM (C50) *2k x 16-bit single-cycle on-chip boot ROM (C50) *1056x16-bit dual-access on-chip data RAM 2012-13/ODD/V/DSP/LM Page 59
*224k x 16-bit maximum addressable external memory space (64k program, 64k data 64k I/o and 32k global) *32-bit arithmetic logic unit (ALU), 32-bit accumulator (ACC) and 32-bit accumulator buffer (ACCB) *16-bit parallel logic unit (PLU) *16 x 16-bit parallel multiplier with a 32-bit product capability. Single-cycle multiply/accumulate instructions *Eleven auxiliary registers with a dedicated auxiliary register arithmetic unit for indirect addressing. *Eleven context-switch register (shadow registers) for storing strategic CPU-controlled registers during an interrupt service routine *Eight-level hardware stack *0 to 16-bit left right data barrel-shifters and a 64-bit incremental data shifter *Two indirectly addressed circular buffers for circular addressing *Single-instruction repeat and block repeat operations for program code *Block memory move instructions for better program /data management *Full-duplex synchronous serial port for direct communication between the c5x and another serial device *Time-division multiple-access (TDM) serial port *Interval timer with period, control, and counter registers for software stop, start and reset *64k parallel I/O ports, 16 of which are memory mapped *Sixteen software programmable wait-state generators for program, data, and I/o memory spaces ARCHITECTURE: A detailed architectural block diagram of TMS320C50 is illustrated in figure. The TMS320C50 utilizes a modified Harvard architecture for speed and flexibility. In a strict Harvard architecture, program and data memory are in two separate spaces, permitting a full overlap of instruction fetch and execution.
Page 60
The TMS320 familys modification of the Harvard architecture allows transfer between program and data spaces, thereby increasing the flexibility of the device. This modification permits coefficients stored in program memory to be read into the data RAM, eliminating the need for a separate coefficient ROM. It also makes available immediate instructions and subroutines based on computed values. 32-BIT ACCUMULATOR: The TMS320C50 contains a 32-bit ALU and accumulator for support of double-precision, twos complement arithmetic. The ALU is a general purpose arithmetic unit that operates on 16-bit words taken from the data RAM or derived from immediate instructions. In addition to the usual arithmetic instructions, the ALU can perform Boolean operations, providing the bit manipulation ability required of a high-speed controller. The accumulator stores the output from the ALU and is often an input to the ALU. Its word length is 32-bit. The accumulator is divided into a high-order word (bits 31 through 16) and a low-order word (bits 15 through 0). Instructions are provided for storing and loading the high and lower order accumulator words to memory.
Page 61
16 x 16-BIT PARALLEL MULTIPLIER: The multiplier performs a 16 x16-bit twos complement multiplication with a 32-bit result in a single instruction cycle. The multiplier consists of three units: the T-Register, P-Register, and multiplier array. The 16-bit T-Register temporarily stores the multiplicand and the P-Register stores the 32-bit product. Multiplier values either come from the data memory or are derived immediately from the MPY (multiply immediate) instruction word. The fast on-chip multiplier allows the device to perform Two multiply/accumulate fundamental operations such as convolution, correlation, and filtering. operands to be processed simultaneously. SHIFTERS: A 16-bit scaling shifter is available at the accumulator input. This shifter produces a left shift of 0to16-bits on the input data to accumulator.TMS320C50 also contains a shifter at the accumulator output. This shifter provide a left shift of 0to 7, on the data from either the ACCH or ACCL register. In addition one shifter at the output of P-register can shift the product by 1 or 4-bits left or 6-bits right, before transferring the product to accumulator.
instructions in the instruction set fully utilize the computational bandwidth of the multiplier, allowing both
Page 62
DATA AND PROGRAM MEMORY: Since the TMS320C50 uses Harvard architecture, data and program memory reside in two separate spaces. Additionally TMS320C50 has one more memory space called I/O memory space. The total memory capacity of TMS320C50 is 64KW each of Program. Data and I/O memory. The 64KW of data memory is divided into 512 pages with each page containing 128 words. Only one page can be active at a time. One data access on chip data RAM and 9K words of single access Data/Program RAM. The 1056 words of on chip data memory is divided as three blocks B0,B1 & B2, of which B0 can be configured as program or data RAM. Out of the 64KW of total program memory, TMS320C50 has 2K words of on-chip program ROM.The TMS320C50 offers two modes of operation defined by the state of the MC/MP pin: the microcomputer mode (MC/MP=1) or the microprocessor mode (MC/MP=0). In the microcomputer mode, on-chip ROM is mapped into the memory space with up to 2K words of memory available. In the microprocessor mode all 64K words of program memory are external. INTERRUPTS AND SUBROUTINES: The TMS320C50 has three external mask able user interrupts available for external devices that interrupt the processor.The TMS320C50 contains a eight-level hardware stack for saving the contents of the program counter during interrupts and subroutine calls. Instructions are available for saving the devices complete context. PUSH and POP instructions permit a level of nesting restricted only by the amount of available RAM. SERIAL PORT: A full-duplex on-chip serial port provides direct communication with serial devices such as codes, serial A/D converters and other serial systems. The interface signals are compatible with codes and many others serial devices with a minimum of external hardware.
Page 63
INPUT AND OUTPUT: The 16-bit parallel data bus can be utilized to perform I/O functions in two cycles. The I/O ports are addressed by the four LSBs on the address lines, allowing 16 input and 16 output ports. In addition, a polling input for bit test and jump operations (BIO) and three interrupt pins(INT0-INT2) have been incorporated for multitasking.
Page 64
Result: Thus the Architecture of TMS320C50 DSP processor was studied.
Page 65
EXP.NO:8 DATE: STUDY OF TMS320C5416 ARCHITECTURE AIM: To study the architecture TMS320C5416 fixed point processor ARCHITECTURE The VC5416 DSP implements the standard C54X CPU which uses an advanced, modified Harvard architecture that maximizes processing power maintaining three separate bus structures for data memory and one for program memory . Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. For example, two read operation and one write operation can be performed in a single cycle. Instructions with parallel store and application specific instructions fully utilize this architecture; in addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. In addition the VC5416 includes the control mechanisms to manage interrupts, repeated operatrions, and function calls. MEMORY The VC5416 device provides both on-chip ROM and RAM memories to aid in system performance and integration. On-chip ROM with bootloader The VC5416 features a 16k-word x 16-bit on-chip mask able ROM that can only be mapped into program memory space. Customers can arrange to have the ROM of the 5416 programmed with contents unique to any particular application. A bootloader is available in the standard VC541 0 on-chip ROM. This bootloader can be used to automatically transfer user code from an external source to any where in the program memory at power up. If MPFM-C- of the device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM.
Page 66
This location contains a branch instruction to the start of the bootloader program. The standard VC541 0 devices provide different ways to download the code to accommodate various system requirements. * Parallel from 8-bit or 16-bit wide EPROM * Parallel from I/O space, 8-bit or 16-bit mode * Serial boot from serial ports, 8-bit or 16-bit mode * Host-port interface boot * Warm boot The standard on-chip ROM layout is shown below table. ADDRESS RANGE C000h-D4FFh D500h-D6FFh D700h-DCFFh DD00h-DEFFh DF00h-F7FFh F800h-FBFFh FC00h-FCFFh FD00h-FDFFh FE00h-FEFFh FF00h-FF7Fh FF80h-FFFFh DESCRIPTION ROM tables for the GSM EFR speech codec 256 point complex radix-2 DIF FFT with looped code FFT twiddle factors for a 256 point complex radix-2 FFT 1024 point complex radix-2 DITFFT with looped code FFT twiddle factors for a 1024 point complex radix-2 FFT Bootloader -law expansion table A-law expansion table Sine look up table Reserved + Interrupt vector table
ON-CHIP RAM The VC5410 device contains 8k words x 16-bit on-chip dual-access RAM(DARAM) and 56K words x 16-bit of on-chip single-access RAM(SARAM).The DARAM is composed of four blocks of 2k 2012-13/ODD/V/DSP/LM Page 67
words each. Each block in the DARAM can support two reads in one cycle, or a read and a write in one cycle. The DARAM is located in the address range 0080h-1 FFFH in data space, and can be mapped into program/data space by setting the OVLY bit to one. The SARAM is composed of seven blocks of 8K words each. Each of these seven blocks is a single-access memory. For example, an instruction word can be fetched from one SARAM block in the same cycle as a data word is written to another SARAM block. The SARAM located in the address range 2000h-7FFFh in data space can be mapped into program space by setting the OVLY bit to one, while the SARAM located in the address range 18000h-1 FFFFH in program space can be mapped into data space by setting the DROM bit to one.
ONCHIP MEMORY SECURITY The VC5416 device has a maskable option to protect the contents of on-chip memories. When the ROM protect bit is set, no externally originating instruction can access the on-chip memory spaces. In addition, when the ROM protect option is enabled, HP18 read access is limited to address range 0001 2012-13/ODD/V/DSP/LM Page 68
000h-0001 FFFH. Data located outside this range cannot be read through the HP18. Write access to the entire HP18 memory map is still maintained. PROGRAM MEMORY Software can configure their memory cells to reside inside or outside of the program address map. When the cells are mapped into program space, the device automatically accesses them when their address with in bounds. When the program-address generation (PAGEN) logic generates an address outside its bounds, the device automatically generates an external access. The advantages of operating from on-chip memory are as follows. Higher performance because no wait states are required Lower cost than external memory Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space, relocatable interrupt vector table The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location to accommodate a delayed branch branching to the appropriate interrupt service routine without the overhead. At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page. Instruction which allows
DATA MEMORY The data memory space address up to 64K of 16-bit words. The device automatically accesses the on-chip RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device automatically generates an external access. 2012-13/ODD/V/DSP/LM Page 69
The advantages of operating from on-chip memory are as follows: Higher performance because no wait states are required Higher performance because of better flow within the pipeline of the central arithmetic logic unit(CALU) Lower cost than external memory Lower power than external memory
ON-CHIP PERIPHERALS The VC541 0 devices have the following peripherals: Software-programmable wait-state generator Programmable bank-switching A host-port interface (HP18) Three multi-channel buffered serial pots(MCBSPs) A hardware timer A clock generator with a multiple phase-locked loop(PLL) Enhanced external parallel interface(X102) A DMA controller (DMA)
SOFTWARE-PROGRAMMABLE WAIT-STATE GENERATOR The software-programmable wait-state generator can extend external bus cycles by up to fourteen CLKOUT cycles, providing a convenient means of interfacing the VC541 0 with slower external devices. Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are shut off; shutting off these paths from the internal clocks allows the device to run with lower power consumption. The software-programmable wait-state generator is controlled by the 16-bit software wait-state register (SWWSR), which is memory-mapped to address 0028h in data space. The program and data spaces each consist of two 32k-word blocks; the I/O space consists of one 64K-word block. Each of these blocks has a corresponding 3-bit field in the SWWSR. The value of a 3-bit field in SWWSR, in conjunction with the software wait-state multiplier (SWSM) bit in the software wait-state control register 2012-13/ODD/V/DSP/LM Page 70
(SWCR), specifies the number of wait states to be inserted for each access in the corresponding space and address range. When SWSM = 0, the possible values for the number of wait states are 0, 1, 2, 3, 4, 5, 6, and 7. This is the default configuration. When SWSM =1, the possible values for the number of wait states are 0, 2, 4, 6, 8, 10, 12, and 14. At reset, the SWWSR is set to 7FFFh and SWSM to 0, configuring seven wait states for all external accesses.
Result: Thus the study of TMS320C5416 Processor was studied. EXP.NO:9 DATE: ARITHMETIC OPERATION 2012-13/ODD/V/DSP/LM Page 71
AIM: To perform 16 bit addition and multiplication in various addressing modes using TMS320C5416 Processor. Apparatus Required: 1. PC 2. Debugger software Algorithm: 1. Initialize the data pointer by 140h.,which denotes the data memory A000h. 2. Get the two 16 bit data in the memory location A000h,A001h. 3. Perform the addition/multiplication. 4. Store the result in the memory location A002h. 5. Halt the program. Procedure: 1. Turn on the DSP processor kit 2. Open the debugger software. 3. In the menu go to view then click workspace. 4. Go to project and open a new project and create the project file 5. Go to file-new-assembly file 6. Type the assembly level program and save the file. 7. Go to project-add file to project which links the assembly file with the project 8. Click cmd file- add file to project which creates the cmd file associated with assembly file and project file 9. Go to project the click build which creates the ASCII file 10. Go to serial in the menu and click port settings which give the connection between system and the kit. 11. Go to serial then click load program which downloads the ASCII file from system to the kit.
Page 72
12. a) Go to serial then click communication window. In the communication window type SD (Substitute Data memory) then space the the data memory address. Give the input data in the memory location. b) Press dot key in the keyboard to come out from the data memory. c) Type GO then space enter the starting address of the program memory (C000).Press enter which executes the downloaded ASCII file in the DSP processor. d).Press the reset button in the DSP kit and see the output by typing the SD then space the memory location of the output.
Page 73
DIRECT ADDRESSING ADDITION INP1 INP2 OUT .MMREGS

.TEXT
.SET 0H .SET 1H .SET 2H
START: LD RSBX NOP NOP NOP NOP LD ADD STL HLT: B INPUT: Data Memory: A000h A001h
#140H,DP CPL
INP1,A INP2,A A,OUT HLT OUTPUT: Data Memory: A002h
0004h 0004h
0008h
DIRECT ADDRESSING-MULTIPLICATION .MMREGS .TEXT START: STM #0140H,STO RSBX CPL RSBX FRCT NOP NOP NOP NOP LD #000H,A LD 00h,T MPY 01H,A STL A,02H STH A,03H H B H INPUT MEM A000H 2012-13/ODD/V/DSP/LM
DATA 1234H Page 74
A001H
1234H
MEM A000H A001H
DATA 5A90H 014BH
OUTPUT INDIRECT ADDRESSING -ADDITION START LD STM STM STM LD ADD STL B #00H, A #1000H,AR4 #2000H,AR5 #300H,AR6 *AR4,A *AR5,A A,*AR6+ H
INPUT: Memory Data 100h 200h OUTPUT: Memory Data 3000h A2F7h 2343h C63A
AUXILLARY REGISTER ADDRESSING ADDITION .MMREGS .TEXT START: LD STM STM LDM ADD STL H B
#00H,A #1000H,AR4 #300H,AR6 AR4,A #22H,A A,*AR6 H
Page 75
OUTPUT: Memory Data 3000H 1022H
Result: Thus the 16 bit addition and multiplication were performed in various addressing modes using TMS320C5416 Processor. EXP.NO:10 DATE: 2012-13/ODD/V/DSP/LM Page 76
SAMPLING OF INPUT SIGNAL AND DISPLAY AIM: To perform sampling on input signal using TMS320C5416 Processor. Apparatus Required: 1. PC 2. Debugger software 3.CRO Procedure: 13. Turn on the DSP processor kit 14. Open the debugger software. 15. In the menu go to view then click workspace. 16. Go to project and open a new project and create the project file 17. Go to file-new-assembly file 18. Type the assembly level program and save the file. 19. Go to project-add file to project which links the assembly file with the project 20. Click cmd file- add file to project which creates the cmd file associated with assembly file and project file 21. Go to project the click build which creates the ASCII file 22. Go to serial in the menu and click port settings which give the connection between system and the kit. 23. Go to serial then click load program which downloads the ASCII file from system to the kit.
24. a) Go to serial then click communication window. In the communication window type SD (Substitute Data memory) then space the the data memory address. Give the input data in the memory location. 2012-13/ODD/V/DSP/LM Page 77
b) Press dot key in the keyboard to come out from the data memory. c) Type GO then space enter the starting address of the program memory (0000).Press enter which executes the downloaded ASCII file in the DSP processor. d).Press the reset button in the DSP kit and see the output on CRO.
PROGRAM: TXD .SET 0H 2012-13/ODD/V/DSP/LM Page 78
STS .SET 1H DATA .SET 2H DELAY .SET 3H B3 .SET 0F000H B2 .SET 0F00H B1 .SET 00F0H B0 .SET 000FH .mmregs .text START: LDP #100H LAR AR0,#9000H LAR AR1,#359 REP: IN 0,06 RPT #0FH NOP IN 0,04 SPLK #5FFH,DELAY RPT DELAY
NOP LACC 0 AND #0FFFH SUB #7FFH MAR *,AR0 SACL *+,0,AR1 BANZ REP,*LACC SACL CALL REPSER: LAR LAR DELAY DATA SERIAL AR2,#9000H AR0,#719
REPSAMP: 2012-13/ODD/V/DSP/LM Page 79
MAR LACC SACL CALL MAR BANZ LAR LAR REP1: IN RPT NOP IN
*,AR2 *+ DATA SERIAL *,AR0 REPSAMP,*AR0,#9000H AR1,#359 0,06 #0FH
0,04
SPLK #5FFH,DELAY RPT NOP LACC 0 AND #0FFFH DELAY
SUB #7FFH MAR *,AR0
SACL *+,0,AR1 BANZ REP1,*LACC DELAY SACL DATA
Page 80
CALL SERIAL LAR LAR AR2,#9000H AR0,#719
REPSAMP1: MAR *,AR2
LACC *+ SACL DATA CALL SERIAL MAR *,AR0
BANZ REPSAMP1,*REPSER1 B REPSER1 SERIAL SPLK #25H,TXD CALL TXDATA RPT #0FFFH NOP LACC AND BSAR SACL CALL CALL RPT NOP DATA #B3 12 TXD HEXASC TXDATA #0FFFH
LACC DATA 2012-13/ODD/V/DSP/LM Page 81
AND BSAR SACL CALL CALL RPT NOP LACC AND BSAR SACL CALL CALL RPT NOP LACC AND SACL CALL CALL RPT NOP
#B2 8 TXD HEXASC TXDATA #0FFFH DATA #B1 4 TXD HEXASC TXDATA #0FFFH DATA #B0 TXD HEXASC TXDATA #0FFFH
SPLK #24H,TXD CALL TXDATA RPT #0FFFH NOP RET HEXASC: LACC SUB BCND LACC ADD SACL RET TXD #9H GRT9,GT TXD #30H TXD
GRT9: LACC TXD 2012-13/ODD/V/DSP/LM Page 82
ADD #37H SACL TXD RET TXDATA: REPCHK: IN STS,9 LACC STS AND #04H BCND REPCHK,EQ OUT RET TXD,8
Page 83
Result: Thus the sampling was performed on input signal using TMS320C5416 Processor.
Page 84
EXP.NO:11 DATE: IMPLEMENTATION OF FIR FILTER AIM: To implement FIR low pass and band pass filter using TMS320C5416 Processor. Requirements: 1. PC 2. Debugger software 3.CRO Procedure: 1. Turn on the DSP processor kit 2. Open the debugger software. 3. In the menu go to view then click workspace. 4. Go to project and open a new project and create the project file 5. Go to file-new-assembly file 6. Type the assembly level program and save the file. 7. Go to project-add file to project which links the assembly file with the project 8. Click cmd file- add file to project which creates the cmd file associated with assembly file and project file 9. Go to project the click build which creates the ASCII file 10. Go to serial in the menu and click port settings which give the connection between system and the kit. 11. Go to serial then click load program which downloads the ASCII file from system to the kit. 12. a) Go to serial then click communication window. In the communication window type SD (Substitute Data memory) then space the the data memory address. Give the input data in the memory location. b) Press dot key in the keyboard to come out from the data memory. c) Type GO then space enter the starting address of the program memory (0000).Press enter which executes the downloaded ASCII file in the DSP processor. 2012-13/ODD/V/DSP/LM Page 85
d).Press the reset button in the DSP kit and see the output on CRO. PROGRAM: LOWPASS FILTER B3 B2 B1 B0 DATA TXD .SET .SET .SET .SET .SET .SET .mmregs .text START: STM #01h,ST0 RSBX CPL RSBX FRCT NOP NOP STM LD RPT STL REPFIRL: STM STM LOOP: PORTR 06,0 #0A200H,AR4 #359,AR5 #150H,AR1 #0H,A #34H A,*AR1+ 0F000H 0F00H 00F0H 000FH 50H 51H
Page 86
CHK_BUSY: PORTR 07,0 BITF 0,#20H BC LD AND XOR SUB STM STL STM LD RPT STH LD ADD ; ; STL STL CHK_BUSY,TC 0,A #0FFFH,A #0800H,A #800H,A #150H,AR1 A,*AR1 #183H,AR2 #0H,A #33H A,1,0H 0H,A #800H,A A,1H A,*AR4+ PORTR 04,0
MACD *AR2-,TABLE,A
PORTW 1H,04H BANZ LOOP,*AR5STM STM #0A200H,AR2 #359,AR3
REPSER: 2012-13/ODD/V/DSP/LM Page 87
STM NOP NOP NOP NOP LD STL
#140H,ST0
RSBX CPL
*AR2+,A A,DATA
SUB #7FFH,A CALL SERIAL BANZ REPSER,*AR3STM #01h,ST0 RSBX CPL RSBX FRCT NOP NOP B SERIAL: STM NOP NOP NOP NOP LD #25H,A #140H,ST0 RSBX CPL REPFIRL
Page 88
CALL TXDATA STM NOP NOP NOP NOP LD AND DATA,A #B3,A ;1st digit (from msb) #140H,ST0 RSBX CPL
SFTL A,-12 CALL HEXASC CALL TXDATA STM NOP NOP NOP NOP LD AND DATA,A #B2,A ;1st digit (from msb) #140H,ST0 RSBX CPL
SFTL A,-8 CALL HEXASC CALL TXDATA STM #140H,ST0 RSBX CPL
Page 89
NOP NOP NOP NOP LD AND DATA,A #B1,A ;1st digit (from msb)
SFTL A,-4 CALL HEXASC CALL TXDATA STM NOP NOP NOP NOP LD AND DATA,A #B0,A ;1st digit (from msb) #140H,ST0 RSBX CPL
CALL HEXASC CALL TXDATA STM NOP NOP NOP NOP #140H,ST0 RSBX CPL
Page 90
LD STM NOP NOP NOP NOP RET HEXASC: ADD LD SUB BC ADD LESS9: RET TXDATA:
#24H,A #140H,ST0
CALL TXDATA RSBX CPL
#30H,A A,B #3AH,B LESS9,BLT #7H,A
CALL 8C69H SSBX INTM rpt nop RET #2ffh ;delay
;8C38H for 5416 mode 1
;fs = 41khz ; fc = 4khz ; N = 52
Page 91
TABLE: .word 01FH .word 010EH .word 01ABH .word 01B4H .word 0117H .word 0H .word 0FECDH .word 0FDEEH .word 0FDC2H .word 0FE6EH .word 0FFCDH .word 016FH .word 02C0H .word 0333H .word 0274H .word 097H .word 0FE19H .word 0FBCBH .word 0FA9BH .word 0FB53H .word 0FE50H .word 0362H .word 09C5H .word 01048H .word 01599H .word 01895H .word 01895H .word 01599H .word 01048H .word 09C5H 2012-13/ODD/V/DSP/LM Page 92
.word 0362H .word 0FE50H .word 0FB53H .word 0FA9BH .word 0FBCBH .word 0FE19H .word 097H .word 0274H .word 0333H .word 02C0H .word 016FH .word 0FFCDH .word 0FE6EH .word 0FDC2H .word 0FDEEH .word 0FECDH .word 0H .word 0117H .word 01B4H .word 01ABH .word 010EH .word 01FH
PROGRAM:BAND PASS FILTER 2012-13/ODD/V/DSP/LM Page 93
B3 B2 B1 B0 DATA TXD
.SET .SET .SET .SET .SET .SET
0F000H 0F00H 00F0H 000FH 50H 51H
.mmregs .text START: STM #01h,ST0 RSBX CPL RSBX FRCT NOP NOP STM #150H,AR1 LD #0H,A RPT #34H STL A,*AR1+ REPFIRL: STM #0A200H,AR4 STM #359,AR5 LOOP: PORTR 06,0 CHK_BUSY: PORTR 07,0 BITF 0,#20H BC CHK_BUSY,TC PORTR 04,0 LD 0,A AND #0FFFH,A XOR #0800H,A SUB #800H,A STM #150H,AR1 STL A,*AR1 STM #183H,AR2 LD #0H,A RPT #33H
MACD *AR2-,TABLE,A STH A,1,0H 2012-13/ODD/V/DSP/LM Page 94
; ;
LD 0H,A ADD #800H,A STL A,1H PORTW 1H,04H STL A,*AR4+ BANZ LOOP,*AR5-
STM #0A200H,AR2 STM #359,AR3 REPSER: STM #140H,ST0 RSBX CPL NOP NOP NOP NOP LD *AR2+,A SUB #07FFH,A STL A,DATA CALL SERIAL BANZ REPSER,*AR3STM #01h,ST0 RSBX CPL RSBX FRCT NOP NOP B REPFIRL
SERIAL: STM #140H,ST0 RSBX CPL NOP NOP NOP NOP
LD CALL STM RSBX NOP
#25H,A TXDATA #140H,ST0 CPL
Page 95
NOP NOP NOP LD DATA,A AND #B3,A SFTL A,-12 CALL HEXASC CALL TXDATA STM #140H,ST0 RSBX CPL NOP NOP NOP NOP LD DATA,A AND #B2,A SFTL A,-8 CALL HEXASC CALL TXDATA STM #140H,ST0 RSBX CPL NOP NOP NOP NOP LD DATA,A AND #B1,A SFTL A,-4 CALL HEXASC CALL TXDATA STM #140H,ST0 RSBX CPL NOP NOP NOP NOP ;1st digit (from msb)
;1st digit (from msb)
LD DATA,A AND #B0,A CALL HEXASC CALL TXDATA
Page 96
STM #140H,ST0 RSBX CPL NOP NOP NOP NOP LD #24H,A CALL TXDATA STM #140H,ST0 RSBX CPL NOP NOP NOP NOP RET HEXASC: ADD #30H,A LD A,B SUB #3AH,B BC LESS9,BLT ADD #7H,A LESS9: RET TXDATA: CALL 8C69H ;8C38H for 5416 mode 1 SSBX INTM rpt #2ffh ;delay nop RET ;fs = 41khz ; fc = 4khz ; N = 52
TABLE: .word 208H .word 257H .word 218H 2012-13/ODD/V/DSP/LM Page 97
.word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word
143H 0H 0FE9EH 0FD7AH 0FCE7H 0FD08H 0FDD1H 0FEECH 0FFE4H 3DH 0FFA1H 0FDFCH 0FB8FH 0F8ECH 0F6D4H 0F608H 0F713H 0FA21H 0FEE6H 4A7H 0A60H 0EF8H 1187H 1187H 0EF8H 0A60H 4A7H 0FEE6H 0FA21H 0F713H 0F608H 0F6D4H 0F8ECH 0FB8FH 0FDFCH 0FFA1H
.word 3DH .word 0FFE4H 2012-13/ODD/V/DSP/LM Page 98
.word .word .word .word .word .word .word .word .word .word .word
0FEECH 0FDD1H 0FD08H 0FCE7H 0FD7AH 0FE9EH 0H 143H 218H 257H 208H
Page 99
Result: Thus the FIR low pass and band pass filters were implemented using TMS320C5416. EXP.NO:12 DATE: CALCULATION OF FFT 2012-13/ODD/V/DSP/LM Page 100
Aim: To find Fast Fourier Transform for given input sequence using TMS320C5416 Processor. Apparatus Required: 1. PC 2. Debugger software Algorithm: 6. Initialize the data pointer by 140h.,which denotes the data memory A000h. 7. Get the two 16 bit data in the memory location A000h,A001h. 8. Perform the addition/multiplication. 9. Store the result in the memory location A002h. 10. Halt the program. Procedure: 25. Turn on the DSP processor kit 26. Open the debugger software. 27. In the menu go to view then click workspace. 28. Go to project and open a new project and create the project file 29. Go to file-new-assembly file 30. Type the assembly level program and save the file. 31. Go to project-add file to project which links the assembly file with the project 32. Click cmd file- add file to project which creates the cmd file associated with assembly file and project file 33. Go to project the click build which creates the ASCII file 34. Go to serial in the menu and click port settings which give the connection between system and the kit.
35. Go to serial then click load program which downloads the ASCII file from system to the kit. 2012-13/ODD/V/DSP/LM Page 101
36. a) Go to serial then click communication window. In the communication window type SD (Substitute Data memory) then space the the data memory address. Give the input data in the memory location. b) Press dot key in the keyboard to come out from the data memory. c) Type GO then space enter the starting address of the program memory (C000).Press enter which executes the downloaded ASCII file in the DSP processor. d).Press the reset button in the DSP kit and see the output by typing the SD then space the memory location of the output.
Page 102
K .SET DNS .SET TWIDC .SET TWIDS .SET INC .SET BFY .SET BFYC .SET DNSC .SET GRP .SET GRPC .SET STG .SET STGC .SET INCTF .SET AR11 .SET AR12 .SET AR13 .SET AR14 .SET B3 .SET B2 .SET B1 .SET B0 .SET DATA .SET TXD .SET MULF .SET ADDSUBF .SET BITREVF .SET INCLUDEF .SET REPS .SET .mmregs .text
8H 2H 0A500H 0A550H 0A400H 0H 1H 3H 4H 5H 6H 7H 9H 11H 12H 13H 14H 0F000H 0F00H 00F0H 000FH 30H 31H 09650H 09680H 09700H 09710H 09890H
START: ; STM #40H,PMST RSBX CPL STM #140H,ST0 2012-13/ODD/V/DSP/LM Page 103
RSBX FRCT NOP NOP NOP NOP CALL BITREVF CALL INCLUDEF ST #1H,BFY ST #4H,GRP ST #2H,DNS ST #3H,STG LD STG,A SUB STL #1H,A A,STGC
STM RPT
#TWIDC,AR0 #3H
MVPD TABCOS,*AR0+
STM RPT
#TWIDS,AR0 #3H
MVPD TABSIN,*AR0+ STM #2H,AR5 ;AR5 = STAGE LOOP
STGLOP: ST #0H,K 2012-13/ODD/V/DSP/LM Page 104
LD SUB STL LD SUB STL LD
BFY,A #1H,A A,BFYC GRP,A #1H,A A,GRPC DNS,A
STLM A,AR0 SUB STL LD LD #1H,A A,DNSC DNSC,A GRP,A ;N/2=8/2=4H
CMPM GRP,#4H BC LD NO_CHG,NTC #0H,A
NO_CHG: STL A,INCTF 2012-13/ODD/V/DSP/LM Page 105
LD
GRPC,A ;AR3 = GROUP LOOP
STLM A,AR3 STM GRPLOP: ST LD #0H,K BFYC,A #INC,AR1
;k is initially 0 in all groups
STLM A,AR4 BFYLOP: LD *AR1+0,A
;AR4 = BFLY LOOP
CALL MULF LD DNS,A
STLM A,AR0 LD *AR1-0,A
CALL ADDSUBF LD ADD STL K,A INCTF,A A,K
BANZ BFYLOP,*AR4LD DNS,A 2012-13/ODD/V/DSP/LM Page 106
STLM A,AR0 LD *AR1+0,A
BANZ GRPLOP,*AR3MPY STL MPY STL BFY,#2,A A,BFY DNS,#2,A A,DNS ;DNS * 2 = DNS ;BFY * 2 = BFY
STLM A,AR0 LD STL GRP,A A,-1,GRP ;GRP / 2 = GRP
BANZ STGLOP,*AR5CALL REPS hlt: B hlt TABCOS: .word .word .word .word 00100H 000B5H 00000H 0FF4BH
TABSIN: .word .word 00000H 0FF4BH 2012-13/ODD/V/DSP/LM Page 107
.word .word
0FF00H 0FF4BH
INPUT 0A200
DATA MEMORY 0700
Page 108
0A201 0A202 0A203 0A204 0A205 0A206 0A207 OUTPUT: 0A400 0A401 0A402 0A403 0A404 0A405 0A406 0A407 0A408 0A409
0B00 0F00 0B00 0700 0300 0000 0300 DATA MEMORY 3900 0000 0000 E5B0 FF00 0000 0000 03B0 0100 0000
; ;
0A40A 0A40B
0000 FC50 2012-13/ODD/V/DSP/LM Page 109
; ; ; ;
0A40C 0A40D 0A40E 0A40F
FF00 0000 0000 1A50
Page 110
Result: Thus the Fast Fourier Transform of given input sequence was found using TMS320C5416 processor EXP.NO:13 DATE: WAVEFORM GENERATION AIM: To generate square wave and sawtooth wave using TMS320C5416 Processor. 2012-13/ODD/V/DSP/LM Page 111
Requirements: 1. PC 2. Debugger software 3.CRO Algorithm: 1. Initialize the data pointer by 100h., which denotes the data memory 8000h. 2. Set the maximum amplitude of the waveform. 3. Set the frequency of the waveform. 4. Set the output port address(DAC) 5. Complement the maximum amplitude to get the minimum amplitude of the waveform 6. Repeat the maximum amplitude and minimum amplitude to get the square waveform. 7. Halt the program. Procedure: 1. Turn on the DSP processor kit 2. Connect the CRO in the DAC output pin. 3. Open the debugger software. 4. In the menu go to view then click workspace. 5. Go to project and open a new project and create the project file 6. Go to file-new-assembly file 7. Type the assembly level program and save the file. 8. Go to project-add file to project which links the assembly file with the project 9. Click cmd file- add file to project which creates the cmd file associated with assembly file and project file 10. Go to project the click build which creates the ASCII file 11. Go to serial in the menu and click port settings which give the connection between system and the kit. 12. Go to serial then click load program which downloads the ASCII file from system to the kit. 13. Execute the program and the output in the CRO. 2012-13/ODD/V/DSP/LM Page 112
PROGRAM-SQUARE WAVE START: STM NOP NOP NOP NOP REP: ST ST B DELAY: STM DEL1: PORTW DATA,04H BANZ DEL1,*AR1RET #0FFFH,AR1 #0H,DATA #0FFFH,DATA REP CALL DELAY CALL DELAY #140H,ST0 RSBX CPL
PROGRAM-SAWTOOTH WAVE .MMREGS .TEXT START: STM #140H,ST0 2012-13/ODD/V/DSP/LM Page 113
RSBX CPL NOP NOP NOP NOP
REP: ST INC: LD ADD STL ; DATA,A #1H,A A,DATA #0H,DATA
PORTW DATA,04H CMPM DATA,#0FFFH B REP BC INC,NTC
Page 114
RESULT: Thus the square wave and sawtooth waveforms were generated using TMS320C5416 Processor. EXP.NO:14 DATE: TABLE DATA TRANSFER Aim: To write and execute a program for accessing table using TMS320C5416 Processor. Requirements: 2012-13/ODD/V/DSP/LM Page 115
1. PC 2. Debugger software Algorithm: 1. Initialize the data pointer by 140h., which denotes the data memory A000h. 2. Set the maximum amplitude of the waveform. 3. Set the frequency of the waveform. 4. Set the output port address(DAC) 5. Complement the maximum amplitude to get the minimum amplitude of the waveform 6. Repeat the maximum amplitude and minimum amplitude to get the square waveform. 7. Halt the program. Procedure: 1. Turn on the DSP processor kit 2. Connect the CRO in the DAC output pin. 3. Open the debugger software. 4. In the menu go to view then click workspace. 5. Go to project and open a new project and create the project file 6. Go to file-new-assembly file 7. Type the assembly level program and save the file. 8. Go to project-add file to project which links the assembly file with the project
9. Click cmd file- add file to project which creates the cmd file associated with assembly file and project file 10. Go to project the click build which creates the ASCII file 11. Go to serial in the menu and click port settings which give the connection between system and the kit. 12. Go to serial then click load program which downloads the ASCII file from system to the kit. 2012-13/ODD/V/DSP/LM Page 116
13. Execute the program and the output in the CRO. PROGRAM: .MMREGS .TEXT START LD #140H RSBX CPL NOP NOP NOP NOP STM #0A100H,AR1 ST #TABLE,00H LD 00H,A RPT #04H READA *AR1+ H B H TABLE: .WORD 00123H .WORD 04567H .WORD 089ABH .WORD 0CDEFH .WORD 00123H
OUTPUT: A100 00123H A101 04567H A102 089ABH A103 0CDEFH A104 00123H
Page 117
RESULT: Thus the program for accessing table was written and executed using TMS320C5416 Processor.
Viva Questions MATLAB QUESTIONS 1. MAT LAB stands for what? 2. Which function is used to perform 2D DFT using FFT algorithm? 3. Which function is used to perform Kaiser window? Give the sample syntax for that. 4. What is the latest version of MATLAB? 2012-13/ODD/V/DSP/LM Page 118
5. List the areas of applications for MATLAB? 6. Which function is used to find the impulse invariant IIR digital filter? 7. Which function is used to perform 1D &2D DCT ? 8. Which function is used to find histogram of image? 9. Which function is used to find histogram equalization of image? 10. Which function is used to find correlation of a sequence? CIRCULAR CONVOLUTION QUESTIONS 1. Why we need circular convolution? 2. What is the difference between circular & linear convolution? 3. What is the length of output sequence after circular convolution if the lengths of input & impulse responses are M1 & M2 respectively? 4. State the circular convolution property of DFT? 5. Where we required convolution property? 6. What does zero padding mean? Where we required this concept? 7. What is difference between linear shifting & circular shifting of signal? Show with example. 8. What is difference between linear & circular folding of signal? Show with example. 9. What is the advantage with sectioned convolution?. LINEAR CONVOLUTION QUESTIONS 1. What is the requirement for convolution?. 2. What is the difference between convolution & correlation? 3. What is meant by impulse response? 4. Is it possible to represent any discrete time signal in terms of impulses? If yes, represent by using example. 5. Draw the h(2n-k) & h(n-2k) for the following sequence h(n) = { 4 3 2 1} assume (i) k= 3 (ii) k =5. 6. Write the expressions for LTI system convolution formula & causal LTI system convolution formula. 7. What us the length of linear convolution if length of input & impulse responses are 2012-13/ODD/V/DSP/LM Page 119
N1 & N2 respectively? 8. What is the difference between continuous and discrete convolution? FIR FILTER QUESTIONS 1. What are the advantages of FIR as compared to IIR? 2. How many types of FIR design methods are used in real time?. 3. What is meant by Gibbs Phenomenon? Where we found such type of effect in FIR filters? 4. What are the advantages& disadvantages of Rectangular window FIR filter as compared to remaining window techniques? 5. Which window technique having less peak amplitude of side lobe as compared to all? 6. What do you understand by linear phase responce? 7. To design all types of filters what would be the expected impulse response? 8. What are the properties of FIR filter?. 9. How the zeros in FIR filter is located? 10. What are the desirable characteristics of the window? 11. What are the specifications required to design filter? IIR FILTER QUESTIONS 1. What is meant by IIR filter? 2. What is the difference between recursive & non-recursive systems? 3. Write the difference equation for IIR system. 4. What are the mapping techniques in IIR filter design? Discuss the advantage & disadvantages of them. 5. What are IIR analog filters? What are the advantages & disadvantages of them? 6. What is the disadvantage in impulse invariance method? 7. What does warping effect mean? Where we found this effect? How can we eliminate warping effect 8. Explain the pole mapping procedure of Impulse invariant & bilinear transformation method. 9. For given same specification which difference we found in Butter worth & Tchebyshev filter. 10. What is the difference between type I & type II Tchebyshev filters?. 11. Where the poles are located for Butter worth & Tchedbyshev filters? 12. What is meant by spectral transformation? 13. Why we need spectral transformation in IIR filter? Fast Fourier Transforms QUESTION 1. What is the difference between continuous time & discrete time Fourier transform? 2. What is the condition for convergence of Fourier transform? 3. What is the difference between discrete Time Fourier Transform (DTFT)& DFT? 4. What is the difference between Z transform & DFT? 5. State convolution property of the DFT? Where we could use the convolution property? 6. State Parsevals theorem.? 7. State correlation property of the DFT.? 8. What is the difference between radix 2 & radix4 FFT algorithms? 2012-13/ODD/V/DSP/LM Page 120
9. Why we need FFT?. 10. What is the difference between decimation in time (DIT FFT) & Decimation in frequency (DIFFFT) algorithms? 11. What is meant by in-place computation in DIF & DIF algorithms? 12. Which properties are used in FFT to reduce no of computations? POWER SPECTRUM DENSITY QUESTION 1. What is the difference between correlation & auto correlation function? 2. What is the difference between PSD & ESD? 3. What is the unit for energy density spectrum? 4. What is the formula for PSD of a function? 5. Same power density spectrum signals always have same magnitude & phase spectrums Is above statement true (or) False: Justify your answer. 6. If we know the impulse response of the system, the How can you find output signal power density from the input signal? 7. What is the unit for power density spectrum? 8. What is the relation between auto correlation & PSD of a function ? DSP PROCESSORS QUESTIONS 1. How many types of DSP processors are available in the market? 2. TMS 320C6X, C stands for what? 3. What are the features of TMS 320C6X processor? 4. What is meant by VLIW architecture? Why we required in DSP processor? 5. How many functional units are in TMS 320C6X DSP processor? 6. What is meant by Circular addressing mode how is it useful for DSP? 7. Which instruction is used to move 16 bit constant in to the upper bits of a register? 8. What is the difference between Von Neumann architecture & Harvard architecture? 9. Which architecture is used in DSP processor? 10. How many instructions can we execute per cycle in TMS320C6X DSP processor? 11. What are the applications for the TMS320 DSPs? 12. Which soft ware tool is required to compile and run the DSP assembly program ? 13. What is the difference between full version Code composer studio &DSK CCS?
Page 121
floating point processorsi.have larger accuracyii.are much easier to programiii.can access larger memoryiv.It is harder to create an efficient program in C on a fixed point processors than on floating point processors42.What is code composer studio?43.Explain Von-Neumann and Harvard architectures PipelinePipelineStag 33.What is a Digital Signal Processor (DSP)?Microprocessor specifically designed to perform fast DSP operations (e.g., FastFourier Transforms, inner products, Multiply & Accumulate) Good at arithmetic operations (multiplication/division) Mostly programmed with Assembly and C through IntegratedDevelopment Environment (IDE)34.Differentiate between RISC and CISC architectures. RISC EmphasisonsoftwareSingle-clock,reducedinstruction onlylargecodesizeBetter Ccompilers CISC EmphasisonhardwareIncludesmulti-clock complexinstructionsSmallcodesizesPoor Ccompilers 35.Differentiate between General purpose MPU(Micro Processor Unit) and DSP Processor MPU are built for a range of general-purpose functions such as :Data manipulationMath calculationsControl systemsThey run large blocks of softwareThey are used in real-time and in unreal-time systems DSPs are single-minded, dedicated to: Perform mathematical calculationsSmall blocks of softwareHave a predictable execution timeReal-time onlyCould assist a general-purpose host MPU36.What is pipelining? DSP ArithmeticVarying internal formatMultiple memory accessSpecial addressing modeVery large internal memory Microprocessor General purposeFixed internal formatSingle memory accessGeneral addressing modeVery large external memory 37.What is parallel processing?38.What is MAC?39.What is barrel shifter? Why it is advantageous to use it in DSP processor?40.Differentiate between floating point DSP and fixed point DSP.41.Fixed Point/Floating Point fixed point processor are :i.cheaper ii.smaller iii.less power consumingiv.Harder to program1.Watch for errors: truncation, overflow, roundingv.Limited dynamic rangevi.Used in 95% of consumer products eStage PFPFDDEE
Page 122
Execute instructionExecute instructionRoute opcode to functional unitRoute opcode to functional unitDecode instructionDecode instructionGenerate program fetch addressGenerate program fetch addressRead opcodeRead opcode DescriptionDescription Floating Point Fixed Point A pplicationsModemsDigital Subscriber Line (DSL)Wireless Base stationsDigital Imaging3D GraphicsSpeech RecognitionVoice over IPApplicationsPortable Products2G, 2.5G and 3G Cell PhonesDigital Audio PlayersDigital Still CamerasVoice RecognitionHeadsetsFingerprint Recognition
Von Neumann Architecture : Single memory shared by both the program instructions and data Harvard Architecture : Two separate memories, a program memory(PM) for instructions, and adata memory (DM)for data44.What are Line-in, Line-out,Mic-in, Mic-out?Reference: Digital signal processing by Dr. Ganesh Rao & Vineeta P. Gejji.Texas instruments materials.
Page 123
Page 124
APPENDIX IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 2012-13/ODD/V/DSP/LM Page 125
Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (Critical Applications). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customers applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright W 1997, Texas Instruments Incorporated
Page 126
Page 127
Page 128
Page 129
Page 130
Page 131
Page 132
Page 133
Page 134
Page 135
Page 136
Page 137
Page 138
Page 139
Page 140
Page 141
Page 142
Page 143

DSP New Manual1

Caricato da

Informazioni sul documento

Titolo originale

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

DSP New Manual1

Caricato da

Copyright:

Formati disponibili

MOTHER TERASA COLLEGE OF ENGINEERING & TECHNOLOGY Mettusalai,Illupur

EC1315- DIGITAL SIGNAL PROCESSING LABORATORY

EC1315 DIGITAL SIGNAL PROCESSING LABORATORY LIST OF EXPERIMENTS USING TMS320C5X

SI.NO 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.

7. 8. 9. 10. 11. 12. 13. 14.

Input: Enter the range:4 Output: 0 0 0 0 1 1 1 1 1

Output: Enter the range:4 0 0 0 0 1 0 0 0 0

Input: Enter the range:4 Output: -4 -3 -2 -1 0 1 2 3 4

Input: Enter the amplitude:4 Enter the frequency:0.2 Output:

Result: 2012-13/ODD/V/DSP/LM Page 27

plot(w,20*log(abs(hz))); xlabel('Frequency in radians'); ylabel('Magnitude in db'); title('Band stop filter');

OUTPUT: Enter the number of samples:25

Result: Thus the Architecture of TMS320C50 DSP processor was studied.

DIRECT ADDRESSING ADDITION INP1 INP2 OUT .MMREGS

.SET 0H .SET 1H .SET 2H

INP1,A INP2,A A,OUT HLT OUTPUT: Data Memory: A002h

DATA 1234H Page 74

MEM A000H A001H

DATA 5A90H 014BH

#00H,A #1000H,AR4 #300H,AR6 AR4,A #22H,A A,*AR6 H

OUTPUT: Memory Data 3000H 1022H

PROGRAM: TXD .SET 0H 2012-13/ODD/V/DSP/LM Page 78

REPSAMP: 2012-13/ODD/V/DSP/LM Page 79

*,AR2 *+ DATA SERIAL *,AR0 REPSAMP,*AR0,#9000H AR1,#359 0,06 #0FH

SPLK #5FFH,DELAY RPT NOP LACC 0 AND #0FFFH DELAY

SUB #7FFH MAR *,AR0

SACL *+,0,AR1 BANZ REP1,*LACC DELAY SACL DATA

CALL SERIAL LAR LAR AR2,#9000H AR0,#719

REPSAMP1: MAR *,AR2

LACC *+ SACL DATA CALL SERIAL MAR *,AR0

LACC DATA 2012-13/ODD/V/DSP/LM Page 81

GRT9: LACC TXD 2012-13/ODD/V/DSP/LM Page 82

PORTW 1H,04H BANZ LOOP,*AR5STM STM #0A200H,AR2 #359,AR3

REPSER: 2012-13/ODD/V/DSP/LM Page 87

STM NOP NOP NOP NOP LD STL

CALL TXDATA RSBX CPL

#30H,A A,B #3AH,B LESS9,BLT #7H,A

CALL 8C69H SSBX INTM rpt nop RET #2ffh ;delay

;8C38H for 5416 mode 1

;fs = 41khz ; fc = 4khz ; N = 52

PROGRAM:BAND PASS FILTER 2012-13/ODD/V/DSP/LM Page 93

.SET .SET .SET .SET .SET .SET

0F000H 0F00H 00F0H 000FH 50H 51H

MACD *AR2-,TABLE,A STH A,1,0H 2012-13/ODD/V/DSP/LM Page 94

SERIAL: STM #140H,ST0 RSBX CPL NOP NOP NOP NOP

LD CALL STM RSBX NOP

#25H,A TXDATA #140H,ST0 CPL

;1st digit (from msb)

;1st digit (from msb)

LD DATA,A AND #B0,A CALL HEXASC CALL TXDATA

;1st digit (from msb)

TABLE: .word 208H .word 257H .word 218H 2012-13/ODD/V/DSP/LM Page 97

.word 3DH .word 0FFE4H 2012-13/ODD/V/DSP/LM Page 98

MVPD TABSIN,*AR0+ STM #2H,AR5 ;AR5 = STAGE LOOP

STGLOP: ST #0H,K 2012-13/ODD/V/DSP/LM Page 104

LD SUB STL LD SUB STL LD

BFY,A #1H,A A,BFYC GRP,A #1H,A A,GRPC DNS,A

STLM A,AR0 SUB STL LD LD #1H,A A,DNSC DNSC,A GRP,A ;N/2=8/2=4H

CMPM GRP,#4H BC LD NO_CHG,NTC #0H,A

NO_CHG: STL A,INCTF 2012-13/ODD/V/DSP/LM Page 105

GRPC,A ;AR3 = GROUP LOOP

STLM A,AR3 STM GRPLOP: ST LD #0H,K BFYC,A #INC,AR1

;k is initially 0 in all groups

,AR2 + DATA SERIAL ,AR0 REPSAMP,AR0,#9000H AR1,#359 0,06 #0FH

SACL +,0,AR1 BANZ REP1,LACC DELAY SACL DATA

LACC + SACL DATA CALL SERIAL MAR ,AR0