Instruction Fetch Unit: Drawbacks

Instruction Fetch Unit
Why does the PC use 30-bit counter?
ECE4680
30
Computer Organization and Architecture Designing a Multiple Cycle Processor

PC Clk imm16 Instruction<15:0> 16
Addr<31:2> PC<31:28> Target 4 Instruction<25:0> 26 30 1 Adder Adder SignExt 30 30 00 30 1 Mux 0 Addr<1:0> Instruction Memory 32
0 30 Mux 1 30
Jump
Instruction<31:0>
Branch
ECE4680 Multipath.1 2002-3-31 ECE4680 Multipath.4
Zero
2002-3-31
A Single Cycle Processor

ALUop op 6 Instr<31:26> RegDst Main Control ALUSrc 3 func Instr<5:0> 6 ALU Control ALUctr 3
The Main Control

op<5>
..
op<5>
<0>
..
op<5>
<0>
..
op<5>
<0>
..
op<5>
<0>
..
op<5>
<0>
..
op<0>
:
Rt Rs Rt
Branch Jump Clk Instruction Fetch Unit
Instruction<31:0> <16:20> <21:25> <11:15> <0:15> R-type ori lw sw beq jump
Rd RegDst
RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump ExtOp ALUop<2> ALUop<1> ALUop<0>
1 Mux 0 RegWr 5 5 5 busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32 ALUctr
Rt Zero ALU
Rs
Rd
Imm16 MemtoReg 0 Mux
MemWr
busW 32 Clk
32 32 WrEn Adr
Mux Data In 32 Clk
imm16 Instr<15:0>
16
Data Memory
ALUSrc ExtOp
2002-3-31
Concepts
Drawbacks of this Single Cycle Processor

Long cycle time:
Components Datapath Connections Bus for data Control Signals Functional/Combinational Sate/Memory/Sequential
Cycle time must be long enough for the load instruction: PCs Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew
instruction
Control
signals
Cycle time is much longer than needed for all other instructions. Examples: R-type instructions do not require data memory access Jump does not require ALU operation nor data memory access
ECE4680 Multipath.3
2002-3-31
ECE4680 Multipath.6
2002-3-31
Overview of a Multiple Cycle Implementation

The root of the single cycle processors problems: The cycle time has to be long enough for the slowest instruction Solution: Break the instruction into smaller steps Execute each step (instead of the entire instruction) in one cycle Cycle time: time it takes to execute the longest step, not the longest instruction Keep all the steps to have similar length
Race Condition Between Address and Write Enable

What is race condition?
This real (no clock input) register file may not work reliably in the single cycle processor because: We cannot guarantee Rw will be stable BEFORE RegWr = 1 There is a race between Rw (address) and RegWr (write enable)
5 5 5 32
Ra RegWr Rb
Reg File 32
busB 32
busA
Rw busW
This is the essence of the multiple cycle processor The advantages of the multiple cycle processor: Cycle time is much shorter Different instructions take different number of cycles to complete Load takes five cycles - Jump only takes three cycles Allows a functional unit to be used more than once per instruction Adder + ALU Instruction mem + Data mem
The real (no clock input) memory may not work reliably in the single cycle processor because: We cannot guarantee Address will be stable BEFORE WrEn = 1 There is a race between Adr and WrEn
32
WrEn Adr
Ideal Memory
Din Dout 32
32
ECE4680 Multipath.7
2002-3-31
ECE4680 Multipath.10
2002-3-31
The Five Steps of a Load Instruction

Instruction Fetch
Clk PC Old Value Clk-to-Q New Value Old Value Old Value Old Value Old Value Old Value Instruction Memory Access Time New Value
How to Avoid this Race Condition?

Data Memory Reg Wr
Instr Decode / Reg. Fetch
Address
Solution for the multiple cycle implementation: Make sure Address is stable by the end of Cycle N Assert Write Enable signal ONE cycle later at Cycle (N + 1) Address cannot change until Write Enable is disasserted
Rs, Rt, Rd, Op, Func ALUctr ExtOp ALUSrc RegWr busA busB Address busW
ECE4680 Multipath.8
Delay through Control Logic New Value New Value New Value Register File Write Time New Value
2
Old Value Delay through Extender & Mux Old Value Old Value
Register File Access Time New Value
3
New Value ALU Delay New Value
Data Memory Access Time Old Value New

2002-3-31 ECE4680 Multipath.11 2002-3-31
Register File & Memory Write Timing:

Ideal vs. Reality
In previous lectures for 1-cycle machine, register file and memory are simplified: Write happens at the clock tick Address, data, and write enable must be stable one set-up time before the clock tick
Dual-Port Ideal Memory

Dual Port Ideal Memory
32
WrEn Adr
Independent Read (RAdr, Dout) and Write (WAdr, Din) ports Read and write (to different location) can occur at the same instruction cycle
32
Ideal Memory
Din Dout
32
Read Port is a combinational path: Read Address Valid --> Memory Read Access Delay --> Data Out Valid Write Port is also a combinational path:
00 30 32 32
MemWr
In real life for m-cycle machines: Neither register file nor ideal memory has the clock input The write path is a combinational logic delay path: - Write enable goes to 1 and Din settles down - Memory write access delay - Din is written into mem[address] Important: Address and Data must be stable BEFORE Write Enable goes to 1
ECE4680 Multipath.9
Clk
RAdr<1:0> <31:2>
32
WrEn Adr
Ideal Memory
Din Dout 32
MemWrite = 1 --> Memory Write Access Delay --> Data In is written into location[WrAdr]
Ideal Memory
WrAdr Din Dout 32
32
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2002-3-31
Instruction Fetch Cycle: In the Beginning

Every cycle begins right AFTER the clock tick: mem[PC] PC<31:0> + 4
Clk One Logic Clock Cycle You are here! PCWr=? PC
32
Register Fetch / Instruction Decode

busA RegFile[rs] ; busB RegFile[rt] ;
ALU is not being used: ALUctr = xx

PCWr=0 PCWrCond=0 Zero IorD=x MemWr=0 IRWr=0
32 32 Rs 32 Rt Rt 0 Rd 1 5 5 0
PCSrc=x RegDst=x RegWr=0 ALUSelA=x

1
Mux
32
PC
32 0
0 32 0 1 2 3 32
Zero ALU
Mux
Instruction Reg
32
MemWr=?
RAdr
IRWr=? Instruction Reg 4

32 32
RAdr
Ra Rb Rw busW busB 32 busA 32
Mux
32 32
1 32
Ideal Memory
WrAdr 32 Din Dout 32
ALU
Reg File
Mux
Clk
32
32
Ideal Memory
32 32 WrAdr Din Dout 32
ALU Control ALUop=?
ALU Control
Go to the Control Func
Op 6 6 Imm 16
ALUSelB=xx ALUOp=xx
2002-3-31
Clk
Instruction Fetch Cycle: The End

Every cycle ends AT the next clock tick (storage element updates): IR mem[PC] PC<31:0> PC<31:0> + 4
Clk One Logic Clock Cycle You are here! PCWr=1 PC
Register Fetch / Instruction Decode (Continue)

busA Target
PCWr=0
Reg[rs] ; busB
Reg[rt] ;
Rfetch/Decode
ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s
Why can we not further send target address to PC?
PC + SignExt(Imm16)*4
PCWrCond=0 Zero MemWr=0 IRWr=0
32 32 Rs 32 Rt Rt 0 Rd 1 5 5
(speculative calculation)
PCSrc=x
1
BrWr=1
32
IorD=x
RegDst=x
RegWr=0
ALUSelA=0
Target
Mux
0 32
Zero ALU
Mux
Instruction Reg
PC
32
32
MemWr=0
RAdr
IRWr=1 Instruction Reg 4

32 32
32 32 32
RAdr
Mux
ALU
1 32
Clk
Ideal Memory
WrAdr 32 Din Dout 32
Reg File
0 1 2 3 32
Mux
32
32
32
Ideal Memory
WrAdr Din Dout
ALU Control ALUOp = Add
32
32
Clk
ECE4680 Multipath.14 2002-3-31
Beq Rtype Ori Memory

<< 2 Control
Op Func 6 6 Imm 16
ALU Control
Extend
ALUSelB=10
32
ALUOp=Add
2002-3-31
ExtOp=1
Instruction Fetch Cycle: Overall Picture

Ifetch
Why do we need PCWr unlike in 1-cycle machine?
Branch Completion
BrComplete
ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s
if (busA == busB) PC Target
PCWr=0 PCSrc=0 ALUSelA=0

1
PCWr=1
PCWrCond=x Zero IorD=0 MemWr=0 IRWr=1

32
BrWr=0 Target PC
IorD=x Mux
32

32
ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc
PCSrc=1 ALUSelA=1
1
BrWr=0
32
RegDst=x
RegWr=0
Target
Mux
0 32
PC
32 32 32 0 0
0 32 0 1 2 3 32
32
Zero ALU
32 32
Rs 32 Rt Rt 0 Rd 1 5 5
Zero ALU
Mux
Instruction Reg
RAdr
Mux
Instruction Reg
Mux
RAdr
1 32 32
Ideal Memory
WrAdr 32 Din Dout
busA 32 busB 32
1 32 32 32
Ideal Memory
WrAdr 32 Din Dout
Mux
Reg File
0 1 2 3 32
Mux
32
ALU Control ALUOp=Add

2002-3-31 ECE4680 Multipath.18
<< 2
Imm 16
ALU Control
ALUSelB=00
Extend
ALUSelB=01
32
ALUOp=Sub
2002-3-31
ExtOp=x
Instruction Decode: We have a R-type!

Next Cycle: R-type Execution
PCWr=0 PCWrCond=0 Zero IorD=x MemWr=0 IRWr=0
32 32 32 32 0 Rs 32 Rt Rt 0 Rd 1 5 5 0
A Multiple Cycle Delay Path

There is no register to save the results between: Register Fetch: busA Reg[rs] ; busB Reg[rt]
PCSrc=x BrWr=1
1 32
RegDst=x
RegWr=0
ALUSelA=0
Target
R-type Execution: ALU output busA op busB R-type Completion: Reg[rd] ALU output
Mux
PC
0 32 0 1 2 3 32
Zero ALU
Mux
RAdr
1 32 32
Ideal Memory
WrAdr 32 Din Dout
Register here to save outputs of Rfetch? IRWr=0

0
Instruction Reg
ALUselA Zero
32
R-type Execution
ALU Output busA op busB
Mux
Reg File
32
Rs 32 Rt Rt 0 Rd 1 5 5
Ra Rb Rw
Register here to save outputs of RExec?
Mux
Mux
Instruction Reg
busA 32
ALU
<< 2 Control
Op Func 6 6 Imm 16
ALU Control
Reg File
0 1 2 3 32
Mux
32
Extend
ALUSelB=10
32
busW busB 32
ALUOp=Add
1 Mux 0
ALU Control ALUOp

2002-3-31
ExtOp=1
ALUselB
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RExec
PCWr=0
PCWrCond=0 Zero IorD=x MemWr=0 IRWr=0

32 32
1: RegDst ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp
A Multiple Cycle Delay Path (Continue)

Register is NOT needed to save the outputs of Register Fetch: IRWr = 0: busA and busB will not change after Register Fetch
PCSrc=x ALUSelA=1
1
BrWr=0 Target
Register is NOT needed to save the outputs of R-type Execution: busA and busB will not change after Register Fetch Control signals ALUSelA, ALUSelB, and ALUOp will not change after R-type Execution Consequently ALU output will not change after R-type Execution In theory, you need a register to hold a signal value if:
32
RegDst=1
RegWr=0
Mux
32
PC
0
Rs 32 Rt Rt 0 Rd 1 1 Mux 0 5 5
0 32 0 1 2 3 32
Zero ALU
Mux
Instruction Reg
32 32
RAdr
32 32
Why not set RegDst=1 at next cycle?
R-type Completion
R[rd] <- ALU Output
PCWr=0
Mux
1 32 0
Ideal Memory
WrAdr 32 Din Dout
Reg File
(1) The signal is computed in one clock cycle and used in another. (2) AND the inputs to the functional block that computes this signal can change before the signal is written into a state element. You can save a register if Cond 1 is true BUT Cond 2 is false: But in practice, this will introduce a multiple cycle delay path: A logic delay path that takes multiple cycles to propagate from one storage element to the next storage element
Mux
<< 2
ALU Control
Imm 16
Extend
32
ExtOp=x
MemtoReg=x
ALUOp=Rtype ALUSelB=01
2002-3-31
Rfinish
Pros and Cons of a Multiple Cycle Delay Path

A 3-cycle path example: IR (storage) Reg File Read Advantages: Register savings We can share time among cycles: - If ALU takes longer than one cycle, still a OK as long as the entire path takes less than 3 cycles to finish
0

32
ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp
PCSrc=x ALUSelA=1
1
BrWr=0 Target
ALU
Reg File Write (storage)
RegDst=1
RegWr=1
Mux
32
PC
Rs 32 Rt Rt 0 Rd 1 1 Mux 0 5 5
0 32 0 1 2 3 32
Zero ALU
Mux
Instruction Reg
32 32
RAdr
32 32
Mux
1
Ideal Memory
WrAdr 32 Din Dout
Reg File
Mux
Mux
32
Rs 32 Rt Rt 0 Rd 1 1 Mux 0 5 5
Zero
32
Instruction Reg
Ra Rb Rw
busA 32
ALU
<< 2
ALU Control
Reg File
0 1 2 3 32
Mux
32
busW busB 32
Imm 16
Extend
32
ExtOp=x
MemtoReg=0
ALUOp=Rtype ALUSelB=01
ALU Control
ALUselB
2002-3-31
Pros and Cons of a Multiple Cycle Delay Path (Continue)

Disadvantage: Static timing analyzer, which ONLY looks at delay between two storage elements, will report this as a timing violation You have to ignore the static timing analyzers warnings But you may end up ignoring real timing violations Always TRY to put in registers between cycles to avoid MCDP
Ori Completion
ALUOp=Or
OriFinish
Reg[rt]
PCWr=0
ALU output
PCWrCond=0 Zero
x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr
PCSrc=x ALUSelA=1
1
BrWr=0 Target
IorD=x PC
32 32 0
MemWr=0 IRWr=0
32
RegDst=0
RegWr=1
Mux
32
Rs 32 Rt Rt 0 Rd 1 5 5
0 32 0 1 2 3 32
Zero ALU
Mux
Instruction Reg
RAdr
Mux
Rs 32 Rt Rt 0 Rd 1 1 Mux 0 5 5
Zero
32
32
Ra Rb Rw
1 32 32
Ideal Memory
WrAdr 32 Din Dout
Mux
Reg File
Instruction Reg
Mux
busA 32
32
ALU
Reg File
0 1 2 3 32
32
1 Mux 0
<< 2
ALU Control
Instruction Decode: We have an Ori!

Next Cycle: Ori Execution
Mux
busW busB 32
ALU Control
Imm 16
ALUselB
Extend
32
ExtOp=0
MemtoReg=0
ALUOp=Or ALUSelB=11
2002-3-31
Instruction Decode: We have a Memory Access!

Next Cycle: Memory Address Calculation
PCWr=0

32 32 Rs 32 Rt Rt 0 Rd 1 5 5
PCSrc=x RegDst=x RegWr=0 ALUSelA=0

1
BrWr=1
32
PCWr=0

32 32 Rs Rt 32 Rt 0 Rd 1 5 5 Ra Rb Rw busW busB 32 busA 32

1
BrWr=1
32
Target PC Zero
32 32 32
Target
Mux
Mux
PC
32 32 0
0 32 0 1 2 3 32
RAdr
0 32 0
Mux
Zero ALU
Intruction Reg
Mux
Instruction Reg
32 32
Ori Execution
ALU output busA or ZeroExt[Imm16]
PCWr=0
Mux
1
Ideal Memory
WrAdr 32 Din Dout
ALU
RAdr
Mux
Reg File
1 32 32
Ideal Memory
WrAdr 32 Din Dout
Reg File
Mux
Mux
32 1 2 3 32
<< 2 Control Op
Func 6 6 Imm 16
ALU Control
<< 2 Extend ALUSelB=10

32
ALUOp=Add
ExtOp=1
2002-3-31
ALU Control
Control
Op Func
6 6
Imm 16
Extend
ALUSelB=10
32
:
ALUOp=Add
2002-3-31
ExtOp=1
ALUOp=Or OriExec 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc
Memory Address Calculation

ALU output
BrWr=0
1
busA + SignExt[Imm16]
1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc
AdrCal

32 32 Rs 32 Rt Rt 0 Rd 1 5 5
PCSrc=x RegDst=0 RegWr=0 ALUSelA=1
PCWr=0

32 32 Rs 32 Rt Rt 0 Rd 1 1 Mux 0 5 5

1
BrWr=0 Target
32
Target PC Zero
32 32 32
Mux
Mux
32
PC
32 32 0
0 32 0 1 2 3 32
0 32 0 1 2 3 32
Zero ALU
Mux
Mux
Instruction Reg
Instruction Reg
RAdr
RAdr
32 32
Mux
1
Mux
ALU
Ideal Memory
WrAdr 32 Din Dout
Reg File
1 32 32
Ideal Memory
WrAdr 32 Din Dout
Reg File
1 Mux 0
Mux
Mux
32
<< 2
ALU Control
<< 2
ALU Control
Imm 16
Extend
32
ExtOp=0
MemtoReg=x
ALUOp=Or ALUSelB=11
Imm 16
Extend
32
ExtOp=1
MemtoReg=x
ALUOp=Add ALUSelB=11
2002-3-31
Memory Access for Store

mem[ALU output]
PCWr=0
busB

32 32
1: ExtOp SWmem MemWr ALUSelA ALUSelB=11 ALUOp=Add x: PCSrc,RegDst MemtoReg PCSrc=x
Putting it all together: Multiple Cycle Datapath
BrWr=0
1
PCWr
RegDst=x
RegWr=0
ALUSelA=1
32
Target PC Zero
32 32 32
PCWrCond Zero IorD MemWr IRWr

32 32 0
PCSrc RegDst RegWr ALUSelA

1
BrWr Target
Mux
Mux
32
PC
32 32 0
Rs 32 Rt Rt 0 Rd 1 1 Mux 0 5 5
0 32 0 1 2 3 32
RAdr
Rs 32 Rt Rt 0 Rd 1 1 Mux 0 5 5
0 32 0 1 2 3 32
Zero ALU
Mux
Mux
Instruction Reg
Instruction Reg
RAdr
32 32
Keep ALUSelA, ALUSelB, ALUOp same as previous cycle!

Memory Access for Load

Mem Dout
PCWr=0
Mux
1
Mux
ALU
Ideal Memory
WrAdr 32 Din Dout
Reg File
1 32 32
Ideal Memory
WrAdr 32 Din Dout
Reg File
Mux
Mux
32
<< 2
ALU Control
<< 2
ALU Control
Imm 16
Extend
32
ExtOp=1
MemtoReg=x
Imm 16
Extend
32
ALUOp ALUSelB
2002-3-31
ExtOp
MemtoReg
mem[ALU output]
1: ExtOp LWmem ALUSelA, IorD ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc
Summary
Disadvantages of the Single Cycle Processor Long cycle time
BrWr=0
1
PCWrCond=0 Zero IorD=1 MemWr=0 IRWr=0

32 32 Rs 32 Rt Rt 0 Rd 1 1 Mux 0 5 5
PCSrc=x RegDst=0 RegWr=0 ALUSelA=1
Cycle time is too long for all instructions except the Load Multiple Cycle Processor: Divide the instructions into smaller steps Execute each step (instead of the entire instruction) in one cycle
32
Target
Mux
PC
0
0 32 0 1 2 3 32
Zero ALU
Mux
Instruction Reg
32 32
RAdr
1 32 32
Ideal Memory
WrAdr 32 Din Dout
Do NOT confuse Multiple Cycle Processor with Multiple Cycle Delay Path Multiple Cycle Processor executes each instruction in multiple clock cycles Multiple Cycle Delay Path: a combinational logic path between two storage elements that takes more than one clock cycle to complete It is possible (desirable) to build a MC Processor without MCDP: Use a register to save a signals value whenever a signal is generated in one clock cycle and used in another cycle later
Write Back for Load

Reg[rt]
PCWr=0
Mux IorD=x
32 0
Reg File
Mux
32
<< 2
ALU Control
Imm 16
Extend
32
ExtOp=1
MemtoReg=x
2002-3-31 ECE4680 Multipath.35 2002-3-31
Mem Dout
32 Rs 32 Rt Rt 0 Rd 1 5 5
1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD
LWwr
Putting it all together: Control State Diagram

Ifetch
ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s
Rfetch/Decode
ALUOp=Add 1: BrWr, ExtOp ALUSelB=10 x: RegDst, PCSrc IorD, MemtoReg Others: 0s
BrComplete
beq
PCSrc=x ALUSelA=1
1
BrWr=0 Target
RegDst=0
RegWr=1
32
lw or sw Rtype
1: ExtOp LWmem ALUSelA, IorD ALUSelB=11 ALUOp=Add lw x: MemtoReg PCSrc
ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc
Mux
Ori OriExec
ALUOp=Or 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc
PC
0 32 0 1 2 3 32
Zero ALU
32 32
RAdr
1 32 32
Ideal Memory
WrAdr 32 Din Dout
Reg File
32
1: ExtOp ALUSelA ALUSelB=11 ALUOp=Add x: MemtoReg PCSrc
AdrCal
1: RegDst RExec ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp
Mux
Instruction Reg
Mux
1 Mux 0
Mux
sw LWwr
1: ALUSelA RegWr, ExtOp MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc IorD 1: ExtOp SWMem ALUOp=Rtype MemWr ALUSelA 1: RegDst, RegWr ALUSelB=11 ALUselA ALUOp=Add ALUSelB=01 x: PCSrc,RegDst x: IorD, PCSrc MemtoReg ExtOp
<< 2
ALU Control
Rfinish
OriFinish
ALUOp=Or x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr
Imm 16
Extend
32
ExtOp=1
MemtoReg=1
2002-3-31
2002-3-31
Where to get more information?

Next two lectures: Multiple Cycle Controller: Appendix C of your text book. Microprogramming: Section 5.5 of your text book. D. Patterson, Microprograming, Scientific America, March 1983. D. Patterson and D. Ditzel, The Case for the Reduced Instruction Set Computer, Computer Architecture News 8, 6 (October 15, 1980)
Homework. See the website.
2002-3-31

Instruction Fetch Unit: Drawbacks

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Instruction Fetch Unit: Drawbacks

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Instruction Fetch Unit

Why does the PC use 30-bit counter?

Computer Organization and Architecture Designing a Multiple Cycle Processor

A Single Cycle Processor

The Main Control

Branch Jump Clk Instruction Fetch Unit

Instruction<31:0> <16:20> <21:25> <11:15> <0:15> R-type ori lw sw beq jump

1 Mux 0 RegWr 5 5 5 busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32 ALUctr

Imm16 MemtoReg 0 Mux

Mux Data In 32 Clk

Drawbacks of this Single Cycle Processor

Overview of a Multiple Cycle Implementation

Race Condition Between Address and Write Enable

The Five Steps of a Load Instruction

How to Avoid this Race Condition?

Instr Decode / Reg. Fetch

Register File Access Time New Value

Data Memory Access Time Old Value New

Register File & Memory Write Timing:

Dual-Port Ideal Memory

Instruction Fetch Cycle: In the Beginning

Register Fetch / Instruction Decode

ALU is not being used: ALUctr = xx

PCSrc=x RegDst=x RegWr=0 ALUSelA=x

IRWr=? Instruction Reg 4

Ra Rb Rw busW busB 32 busA 32

ALU Control ALUop=?

Go to the Control Func

Instruction Fetch Cycle: The End

Register Fetch / Instruction Decode (Continue)

IRWr=1 Instruction Reg 4

Ra Rb Rw busW busB 32 busA 32

ALU Control ALUOp = Add

Beq Rtype Ori Memory

Instruction Fetch Cycle: Overall Picture

ALUOp=Add 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s

if (busA == busB) PC Target

PCWr=0 PCSrc=0 ALUSelA=0

PCWrCond=x Zero IorD=0 MemWr=0 IRWr=1

PCWrCond=1 Zero MemWr=0 IRWr=0

ALUOp=Sub ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCSrc

Ra Rb Rw busW busB 32 busA 32

ALU Control ALUOp=Add

Instruction Decode: We have a R-type!

A Multiple Cycle Delay Path

Ra Rb Rw busW busB 32 busA 32

Register here to save outputs of Rfetch? IRWr=0

Beq Rtype Ori Memory

Register here to save outputs of RExec?

ALU Control ALUOp

PCWrCond=0 Zero IorD=x MemWr=0 IRWr=0

1: RegDst ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD MemtoReg ExtOp

A Multiple Cycle Delay Path (Continue)

Ra Rb Rw busW busB 32 busA 32

Why not set RegDst=1 at next cycle?

Pros and Cons of a Multiple Cycle Delay Path

PCWrCond=0 Zero IorD=x MemWr=0 IRWr=0

ALUOp=Rtype 1: RegDst, RegWr ALUselA ALUSelB=01 x: IorD, PCSrc ExtOp

Reg File Write (storage)

Ra Rb Rw busW busB 32 busA 32

Pros and Cons of a Multiple Cycle Delay Path (Continue)

x: IorD, PCSrc ALUSelB=11 1: ALUSelA RegWr