SPICE Simulation

Chang Gung University

Department of Electrical Engineering

Outline Introduction to SPICE Elements & Units DC Analysis AC Analysis Transient Analysis Subcircuits

VLSI CAD

Objectives

Know the concept of SPICE simulation method. Understand the basic format for the .SP file. Study the fundamental circuit elements. Learn the analysis statement. Realize the usage of waveform tools.

VLSI CAD

Overview
1) Circuit design background A procedure to predict the circuit/system characteristic after manufacture.

Foundry Manufacturing

VLSI CAD

Overview
2) Circuit Simulation background

Circuit Simulation Tool

Model

Circuit Structure

Circuit characteristic or waveform

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Introduction to SPICE Simulation Program with Integrated Circuit Emphasis Developed in 1970s at Berkeley, therefore support common original SPICE syntax A circuit analysis tool for simulation of electrical circuits in transient and frequency domains There are lots of SPICE tools available over the market, HSPICE, Spectre, TSPICE, Pspice. Basic algorithm scheme of SPICE tools are similar, however the control of time step, equation solver and convergence control might be different.

VLSI CAD

Before start SPICE Understand the characteristic of physical model. Understand what kind of circuit you need. Understand what input sources. Understand the weakness of your circuit and know how to improve the circuit. Is the output waveform as your expect?

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Basic flow of SPICE

Circuit / system

Initial condition

Model, temp, supply voltage

Analyze type

DC/AC/TRAN Probe/measurement

Output waveform

Execute simulation

Change Circuit Parameter

YES

NO

Satisfy Spec.
YES

Next Spec.

NO

END

VLSI CAD

Netlist structure TITLE : first line is input netlist file title .OPTIONS : Set condition for simulation Analysis (AD,DC..) : statements to set sweep variables .PRINT/.Probe/.graph : generate output waveform .IC or .nodeset : Sets initial state source (I / V) : input source Schematic netlist : circuit description .Subckt/.ends .lib or .include : Call library or include some file .DATA / .param : specify varations .end

VLSI CAD

Rc.sp
* rc.sp * whoami@where.am.i 14/3/07 * Find the response of RC circuit to rising input *-----------------------------------------------* Parameters and models *-----------------------------------------------.option post *-----------------------------------------------* Simulation netlist *-----------------------------------------------Vin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps 1.8 R1 in out 2k C1 out gnd 100f *-----------------------------------------------* Stimulus *-----------------------------------------------.tran 20ps 800ps .plot v(in) v(out) .end
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in

out

gnd

Elements

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Units

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Independent Source (1)

Fixed Vname Vin Node+ Node- dc dc in vss value 1v (ac (ac value 0.5 ) )

Sinusoidal Vname Node+ Node- sin Vin in vss sin

DC 1v

AC 0.5v

Frequency 100meg

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Independent Source (2)

Square-wave Vname node+ node- pulse V1 V2 Td tr tf pw per Vin in vss pulse 0v 3.3v 0s 1ns 1ns 9ns 20ns Piece-wise linear Vname node+ Vin in 150ps 1.8

node pwl gnd pwl 800ps 1.8

t1 0ps

v1 0

t2 v2 100ps 0

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VLSI CAD

Exercise - I EX1: Using the pulse function to generate 500MHz with 50% duty cycle. EX2: Using the pulse function to generate 500MHz with 20% duty cycle. EX3: Using the pwl function to generate a step function with 200ps slew rate after 1ns. All the rising time and falling time is 100ps

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Passive Elements
Resistor Rname Rload Inductor Lname Lload Capacitor Cname Cload node+ node- value out vss 50 node+ node- value in out 1n node+ node- value out 0 1p

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Active Elements
MOS Mname Mn m=1 drain out gate in source body vss vss type nch W L M w=10u l=1u

Precise description Mname drain gate source body type W=<width> L=<length> + AS = <area source> AD = <area drain> + PS = <perimeter source> PD = <perimeter drain>

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Example -I
Inverter .prot .lib 'mm0355v.l' tt .unprot .options captab probe accurate .temp 25 .global VDD! VSS! Vdd VDD! 0 Vss VSS! 0 dc .op .tran .probe Mp Mn .end
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dc 0

3.3

50p 100n v(in) v(out) out out in in VDD! VSS! VDD! VSS! pch nch l= 0.35u w= 20u l= 0.35u w= 4u

Note: Node in is floating.

.SP File Format (2)

Inverter Title. To note what circuit is included in this file. It will be skipped when SPICE is runing. The content between .prot and .unprot will not display in the .lis file. Usually, it was used when you have some circuit secrets or you dont want the useless information, such as the library, show up in the list file. .lib command is used to specify the location of the technology library and the corner used in this simulation.

.prot .lib 'mm0355v.l' tt .unprot .options captab probe accurate .temp 25 Simulation temperature

Display the node capacitance in the .lis file. Only the node or element specified with .probe command will be displayed in the output file.
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Increase the simulation accuracy and the simulation time as well.

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.SP File Format (3)

.global Vdd Vss VDD! VDD! 0 VSS! 0 dc dc 0 3.3

VSS!

.global: Specify the global argument. All nodes with the same name will be treated as the same one.

Global ground. .op: DC operating point analysis. .tran: transient analysis. Time step is 50ps and stop time is 100ns
.op .tran .probe 50p 100n v(in) v(out)

.probe: Record the node waveform while the option probe is added in the .opstions statement.
VDD! VSS! VDD! VSS! pch nch l= 0.35u w= 20u l= 0.35u w= 4u

Mp Mn

out out

in in

Describe a PMOS and an NMOS.

.end

.end: EOF. Additional space is need or the .end statement will be ignored.
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Exercise - II EX1: A inverter has a size as follow: PMOS: W=3u, L=0.18u, m=1 NMOS: W=1u, L=0.18u, m=1 Please input a 500MHz with 50% duty cycle. Please observe the output waveform EX2: The same inverter as EX1, by adding a 0.5ps capacitor at output of inverter. Please observe the output waveform.

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.dc Statement (1)

Inverter .prot .lib 'mm0355v.l' tt .unprot .options captab probe accurate .temp 25 .global VDD! VSS! Vdd VDD! 0 Vss VSS! 0 dc .op .dc .probe Vin Mp Mn .end

.dc: dc voltage sweep. The voltage source Vin will change its voltage from 0V to 3.3V with a step of 0.1V.
dc 0 3.3

sweep v(out) in out out

vin

3.3

0.1

You must specify a certain dc value for the voltage source while performing dc sweep.

0 in in

dc VDD! VSS!

1.65 VDD! VSS!

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pch nch

l= 0.35u w= 20u l= 0.35u w= 4u

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.ac Statement (1)

Inverter .prot .lib 'mm0355v.l' tt .unprot .options captab probe accurate .temp 25 .global VDD! VSS! Vdd VDD! 0 Vss VSS! 0 dc .op .ac .probe

.ac: ac frequency sweep. Simulate 100 times/decade from 1Hz to 100MHz. The dec statement can be replaced by lin for linear scale.
dc 0 3.3

dec 100 vdb(out) vp(out)

100Meg

Display the node phase.

dc VDD! VSS! 1.65 VDD! VSS! ac pch nch

Display the node voltage in dB.

Vin Mp Mn .end in out out 0 in in

An ac voltage source is needed for ac simulation. If the amplitude of the ac voltage is 1, the output voltage will equals to the voltage gain.
1 l= 0.35u w= 20u l= 0.35u w= 4u

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.tran Statement and Output Waveforms

* rc.sp * whoami@where.am.i 26/8/06 * Find the response of RC circuit to rising input *-----------------------------------------------* Parameters and models *-----------------------------------------------.option post *-----------------------------------------------* Simulation netlist *-----------------------------------------------Vin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps 1.8 R1 in out 2k C1 out gnd 100f

in

out

gnd

*-----------------------------------------------* Stimulus *-----------------------------------------------Simulate from t=0 to t=800ps with a time step of 20ps. .tran 20ps 800ps .plot v(in) v(out) Equals to .print and .probe .end
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.PRINT Result (Textual)

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.PROBE Result (Graphical)

Voltage (V)

Time (sec)

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Sub-circuit
.subckt subckt_name node1 node2.noden . Define the inputs and outputs of the sub-circuit. . .ends (subckt_name)

The circuits described between the .subckt and the .ends statements can be re-used by using the X statement.
.subckt Mp Mn .ends Xname Xinv1 Xinv2 Xinv3 Xinv4 inverter out out inverter node1 input output1 output1 output2 in in in out vdd vss vdd vss pch nch w=20u w=5u l=0.35u l=0.35u

node2..noden output1 output2 output2 output4 inverter inverter inverter inverter

subckt_name

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Exercise - III

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Exercise - III
A waveform: B waveform: Frequency=500MHz Frequency=500MHz Tr=Tf=100p Tr=Tf=100p Duty cycle=40% Duty cycle=60% MOS size: PMOS : W=6.5u L=0.35u NMOS : W=1.9u L=0.35u

t=0.1n

A B

A C B

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Exercise - IV
NMOS: W=3.5m L=0.18m PMOS: W=3.5m L=0.18m

A B

3.3v

0.5ns

3ns

10.5ns

17.5ns

21.5ns

30ns

A B

0v 0ns

3.5ns

10ns

18ns

21ns

31ns

40ns

3.3v

0.5ns

5ns

10.5ns

13.5ns

19.5ns

25ns

0v 0ns

5.5ns

10ns

14ns

19ns

25.5ns

40ns

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Exercise - V
NMOS: W=3.5m L=0.18m PMOS: W=6.5m L=0.18m

A B

3.3v

0.5ns

3ns

10.5ns

17.5ns

21.5ns

30ns

A B

0v 0ns

3.5ns

10ns

18ns

21ns

31ns

40ns

3.3v

0.5ns

5ns

10.5ns

13.5ns

19.5ns

25ns

0v 0ns

5.5ns

10ns

14ns

19ns

25.5ns

40ns

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Exercise - VI
NMOS: W=3.5m L=0.18m PMOS: W=6.5m L=0.18m

A B

3.3v

0.5ns

3ns

10.5ns

17.5ns

21.5ns

30ns

A B

0v 0ns

3.5ns

10ns

18ns

21ns

31ns

40ns

3.3v

0.5ns

5ns

10.5ns

13.5ns

19.5ns

25ns

0v 0ns

5.5ns

10ns

14ns

19ns

25.5ns

40ns

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Exercise - VII
NMOS: W=3.5m L=0.18m PMOS: W=6.5m L=0.18m
A B C

3.3v

0.5ns

3ns

10.5ns

17.5ns

21.5ns

30ns

A B

0v 0ns

3.5ns

10ns

18ns

21ns

31ns

40ns

3.3v

0.5ns

5ns

10.5ns

13.5ns

19.5ns

25ns

0v 0ns

5.5ns

10ns

14ns

19ns

25.5ns

40ns

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Exercise - VIII
NMOS: W=3.5m L=0.18m PMOS: W=6.5m L=0.18m

Calculate the Ron of the transmission gate

Con

Vin

Vout

Con
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