Laboratory Short Course

Computer Operating Properly The COP

www.freescale.com/universityprograms

Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 2006. Document Number: LABS12CINTRO33S /REV 0

Reading this Document

Answers provided to the Instructor assume that the reader is using Freescale HCS12C Family Student Learning Kit, and CodeWarrior development software.

This short course has been created using an adapted version of the Process Oriented Guided Learning (POGIL) method. For more information visit www.pogil.org

Freescale Semiconductor

Overview
Most embedded systems must operate continuously without any user input, even if something goes wrong. Most of us have experienced having our desktop or laptop computer locking up and requiring a reboot of the system to get it working again. We simply cannot afford to do this in an embedded system. Ideally, we would write our software so that it never crashes or fails. This, as you can guess, is really hard to do and so our microcontroller manufacturer has included a hardware feature called the Computer Operating Properly, or COP, reset generator. If this hardware feature does not receive a confirmation signal that our program is running properly, it will generate a reset to restart our program from the beginning or from a restart place that we can choose. The COP is also called a watchdog timer.

Learning Objectives
In this module we will help you learn about the COP, or watchdog timer.

Success Criteria
When you complete this module you will be able to demonstrate a program illustrating how the COP can reset the program if it times out and that it does not generate a restart if the COP timer is reset properly in the program.

More Resources and Further Information

Cady, Fredrick M., Software and Hardware Engineering: Assembly and C Programming for the Freescale HCS12 Microcontroller, 2nd edition. (New York: Oxford University Press, Inc., 2008), Chapter 12 HCS12 Interrupts. Ganssle, Jack, Great Watchdogs, http://www.ganssle.com/watchdogs.htm

Explore 1. 1. 2. Download and read Great Watchdogs from http://www.ganssle.com/watchdogs.htm. Make a list of all the things that could go wrong in your program that having a COP reset would assist in making a recovery.

Basics of the COP in the HCS12

The COP reset circuitry guards against our program not working properly by expecting the program to execute a particular sequence of instructions at some interval. If the COP does not receive this sequence before it times out, it generates a reset by pulling the RESET_L signal low. This can reset all peripherals connected to the reset line. The CPU then fetches a COP reset vector to restart the program again. Thus the COP is treated like other interrupts except that it cannot be masked once the COP timer has been started. Often you would like to restart at the beginning of your program but in some situations you may choose to enter some diagnostic routine, such as updating a counter that counts the number of COP restarts that have occurred or lighting an LED, before restarting the program. You may also wish to leave some debugging breadcrumbs to help you understand why the COP is resetting the program.

Explore 2. 1. 2. In some processors the COP is enabled at reset and in others it is disabled. Which is the case for your microcontroller? The COPCTL COP Control Register has five control bits. a. Give the name and function of each bit. Bit 7: Bit 6: Bit 2:1:0: b. c. What is its address? What bits would you initialize to what value to have the COP time-out time be approximately 65 ms with your microcontroller?

Freescale Semiconductor

d. 3. 4.

Once the COP time rate select bits have been written, they cannot be changed in your program. Why is this a good thing?

The ARMCOP Arm COP Register is used to reset the COP timer. What is the sequence of actions that must occur within the time out period to successfully reset the timer? What is meant by a "windowed" COP operation and what does it help guard against?

The COP Reset Vector

When the COP timer times out it generates a processor reset and then uses a vector to transfer control to whatever code you would like to have executed. This is like an ordinary interrupt and you must use your software development system to initialize the vector address with the starting address of your code. Explore 3. 1. 2. What is the COP reset vector address? Assume your program has a section of code labeled "COP_reset_code". Show how to instruct your software development system to initialize the COP reset vector with the address of this code segment.

Problem 1 1. You are to verify that your microcontroller asserts the RESET_L signal each time the COP times out. Come up with a plan to do this and demonstrate it to your laboratory instructor.

Problem 2 1. Design and write a program that demonstrates you can use the COP to generate a reset if the program stops working for some reason. Demonstrate the following: a. b. Your program working correctly without the COP timing out when you are resetting it properly. Your program is reset by the COP if you do not reset it in a timely manner.

Your program must have some visual or audible indication showing the two operational modes and you should test for a variety of failures such as hanging up in a loop, memory contents being destroyed, etc.

Communication Inter-Group
1. 2. 3. Compare your solution to Problem 2 with the other laboratory group. Exchange source listings of your solutions. Are there any differences in the approaches the two groups have used to illustrate the operation of the COP? Is one approach better than the other?

Communication Reporting
1. 2. Demonstrate to your laboratory instructor your program that illustrates the operation of the COP. Prepare a memo report for the laboratory instructor. Include comments gained during your Inter-Group Communication where you looked at another group's solution. Include listings of your and the other group's programs. How does each solution compare in terms of rigorously testing for various faults from which the COP should allow you to recover. What did you learn from seeing the other group's solution?

Freescale Semiconductor

Revision History
Revision 0 Comments Initial Release Author Fred Cady

Freescale Semiconductor

How to Reach Us:

Home Page:
www.freescale.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright license granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.

e-mail:
support@freescale.com

USA/Europe or Locations Not Listed:

Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 1-800-521-6274 480-768-2130 support@freescale.com

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com

Japan:
Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 +81 3 5437 9125 support.japan@freescale.com

Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com

For Literature Requests Only:

Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com

Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. ARM is the registered trademark of ARM Limited. ARM9, ARM11, and ARML210 are the trademarks of ARM Limited. Java and all other Java-based marks are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries. The PowerPC name is a trademark of IBM Corp. and used under license. Freescale Semiconductor, Inc. 2006. Document Number: LABS12CINTRO33S /REV 0