VLSI Design and Characterization of Hybrid Macrocells

Project Guides: Dr. S. C. Bose Prof. D. Nagchoudhuri Scientist 'E2' Professor CEERI, Pilani DA-IICT, Gandhinagar Abstract The project emphasizes on to design Macrocells for Low-voltage applications in Analog domain and Low-power applications in digital domain under VLSI environment. In digital domain, project aims at the exploration of a design methodology for the hybrid adder architectures that can be implemented in lesser area without sacrificing the performance in terms of speed and power. In Analog Domain, Adder Macrocell has been designed for low amplitude high slew rate signals to produce sum of the signals in noisy environment. The transistor models used are Level 13 model of 1.2m CMOS Technology provided by Semiconductor Complex Limited (SCL), Chandigarh. Introduction Although standard cells are very easy to design, they consume unnecessary silicon area while considering all the cells to be of equal height. The standard cell layout approach allows the placement or routing of a circuit in fairly simpler way. Since all standard cells have same height, placement tool readily place them in rows. Power lines of all the cells in the same row are automatically connected. The space reserved between two rows of cells, called channel is used for routing purpose. But when it is required to use a building block with more complex functionality, macrocells that has no restrictions on its height and width are designed. Since the requirement of having a fixed height removed, the design of a macro-cell is more flexible and compact, so complicated functionality is possible. Digital Macrocell Design Methodology Since there is several combinations possible for the inputs to an adder, it is possible that some transistors are 'active' or switches only for a certain small set of critical combinations. So if the requirement is such as this set of combinations is not going to be used in some application, we can 'remove' the transistors corresponding to this critical set of combinations and save the area occupied by the transistors up to a great extent. In terms of number of input combinations possible for different architectures, silicon area can be reduced in terms of number of transistors used as well as the regularity in layout strategy to be followed, which has evolved after removing some transistors. Analog Macrocell Design The circuit implements a CMOS analog adder that takes two signals to produce sum output. Circuit uses no operational amplifier and takes only 10 transistors, thus consumes less area.

Work already done Design, layout and characterization of a Macrocell based on design methodology described briefly above Design of 4-bit slice of second Digital Macrocell based on a specific algorithm for fast carry generation using differential dynamic logic. Current Work Extrapolated 32-bit design and layout of second Digital Macrocell including input and output pads and buffers, which can be fabricated on chip in 1.2 m SCL technology. Layout and characterization of Analog Macrocell