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MMC/SD
DDR/SDR
memory
LCD
USB
connector
Flash
hard drive
IDE CD
802.11
WIFI
Keypads
Stereo
A/D, D/A
+amplifier
TLV430AIC23
12 MHz
Crystal
Crystal
32,768
KHz
Power supply
Power management,
core, I/O voltage Batteries
McBSP
PLL
RTC
MMC/SD
LCD
USB
GPIO
Parallel
bus GPIO
TI
DSP






























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Noise
source
Noise
victim
Coupling
channel












































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ADC TI DSP DAC AMP
CD, DVD
Analog
Analog
audio audio
Analog
audio
Digital
audio
Analog Analog
audio audio
Analog
Digital Digital Analog
High
power
analog
































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3.3 V
1.53.3 V
10 F 0.1 F
0.1 F
0.1 F
220
pF
5.6 K
5.6 K
5.6 K
pF
5.6K
0.1 F
220
220
pF
0.1 uF
5.6
K
Rmic
680
10 K
McBSP1.FSX
McBSP1.DX
McBSP1.DR
McBSP1.CLKX
McBSP1.CLKS
I2C.SDA
I2C.SCL
LRCIN (5)
DIN (4)
DOUT (6)
LRCOUT (7)
BCLK (3)
CLKOUT (2)
SDIN (23)
SCLK (24)
MODE (22)
TI DSP
15 pF 15 pF
XTI/MCLK (25) XTO (26)
3.3V
0.1
F
10
F
0.1
F
10
F
3.3V
1.0 F
100
47K
47K
1.0 F
100
1.0 F
100
47 K
47K
1.0 F
100
33
3.3V
0.1
F
10
F
10 F
BVDD (1)
DGND (28)
DVDD (27)
LLINEIN (20)
RLINEIN (19)
MICBIAS (17)
MICIN (18)
AVDD (14)
AGND (15)
HPVDD (8)
HPGND (11)
ROUT (13)
LHPOUT (9)
RHPOUT (10)
LOUT (12)
CLKOUT (2)
VMID (16)
AIC23
Analog input filters





















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System control and
communications
Compression
decompression
encription
formatting
transmission
Svideo or
composite out
NTSC/PAL
video
encoder
Video
palette
RGB out
composite in
Svideo or
NTSC/PAL
decoder
video
Input
capture
Realtime
signal processing
Output
display
Software codecs
Digital formats
Analog formats
Hardware codecs































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Wireless LAN SOC
(TI ACX100TNETW11
00b or
TNETW1130)
Bluetooth data receive
Shutdown
Control
Bluetooth
SOC
(BRF6100)
2.4 GHzb
radio
Wireless LAN
host interface host interface
Bluetooth



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C1 C2 C3 C4
L1 L2 L3 L4
V
p
+
1
LC

,
Z
o
+
L
C
,
T
d
+
1
Vp
+ LC

.
G
s
+source_reflections +
Z
s
*Z
o
Z
s
)Z
o
,
G
s
+load_reflections +
Z
L
*Z
o
Z
L
)Z
o
,




























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3.0 V
V
clk
Zs = 25
Td = 1.8 nS, Zo = 50 ohms
Transmission line
O
p
e
n
E
n
d
e
d
V
initial
+V
clk
Zo
Zs )Zo
+3
50
25 )50
+ 2V

s
+
Zs *Zo
Zs )Zo
+
25 *50
25 )50
+*0.333

L
+
Z
L
*Zo
Z
L
)Zo
+1
A
m
p
l
i
t
u
d
e
,

V
4.0
3.0
2.0
1.0
0
T1 T2 T3 T4 T5
Time


















































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Generator with 4 output
impedance and unterminated line
R
o
=4 Z=100 , L=8m
no reflections
Correctly terminated line
R
o
Z=50 , L=2m
R=50
2V
2V 100ns
100ns 2V
2V
Vclk
Zs=25
R
C
Load
Load Load
L2
Load
L1, Td=1.8ns, Zo=50
3.0
L
2
, max +L
tr
10
1



















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84.9 , 841.955 ps
6.000 in
CELL:A0
UIS512_UOS373_Y
Microstrip
2.000 in
84.9 , 280.652 ps
68.0
RD(B0)
10.0 pF
C(B0)
VpullDn=0.000V
CELL:B0 CELL:C0 CELL:D0
MT48LC16M16A2
CLK
MT48LC16M16A2
84.9 , 280.652 ps
2.000 in
CELL:D1
CLK
CELL:C1
Microstrip
Microstrip
OSCILLOSCOPE
Design file: 5912CLK.TLN Designer: TI
BoardSim/LineSim, HyperLynx
Comment: NOTE: The signals recorded at the terminating loads is identical therefore only the magenta signal is shown.
Date: Tuesday May 18, 2004 Time: 17:06:26
Show Latest Waveform = YES, Show Previous Waveform = YES
500.0
0.000
500.0
1000.0
1500.0
2000.0
2500.0
3000.0
3500.0
4000.0
4500.0
0.000 5.000 10.000 15.000 20.000 25.000 30.000 35.000 40.000 45.000 50.000
Time (ns)
V
o
l
t
a
g
e

m
V

Probe 1:U(A0)
Probe 2:U(D0)
Probe 3:U(D1)















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Vclk
Zs=25
C
L
Td=1.8ns, Zo=50
3.0
V
L
+ V
clk

1 * e *
(t*Td)t

,



























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OSCILLOSCOPE
Design file: 507201C.HYP Designer: TI
BoardSim/LineSim, HyperLynx
Date: Thursday Jul. 1, 2004 Time: 14:16:59
Net name: FLASH.CLK
Show Latest Waveform = YES, Show Previous Waveform = YES
3.000
2.000
1.000
0.000
1.000
2.000
3.000
4.000
5.000
6.000
7.000
0.000 40.00 80.00 120.00 160.00 200.00
Time (ns)
V
o
l
t
a
g
e

Probe 5:U2.E6






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OSCILLOSCOPE
Design file: 507201C.HYP Designer: TI
BoardSim/LineSim, HyperLynx
Date: Thursday Jul. 1, 2004 Time: 12:39:31
Net name: MCBSP1.CLKS
Show Latest Waveform = YES, Show Previous Waveform = YES
3.000
2.000
1.000
0.000
1.000
2.000
3.000
4.000
5.000
6.000
7.000
0.000 40.00 80.00 120.00 160.00 200.00
Time (ns)
V
o
l
t
a
g
e

Probe 5:U3.G13








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Ground grid
Input
signal
Current return
Signal trace is routed between the two ground paths of the grid
















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Ground grid
Input
signal
Current return
Signal trace is routed diagonally













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Low speed current return
High speed current return
A B
H
D
Ground
Current density
curve
Signal
trace
Return current density + I(D) +
Io
pH
1
1 )

D
H

2



















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H
D
Ground
Signal trace Signal trace
Crosstalk ^
K
1 )

D
H

2
,
where K is a constant less than 1
and depends on the risetime
and trace length
CELL:A0
12.000 in
80.2 , 1.770 ns
CELL:B0
Coupled stackup
U(A0).D0
UIS512_UOS373_Y
33.0
RS(A0)
U(B0).DQ0
EDK2516CBBH
DQ0
33.0
RS(A1)
UIS512_UOS373_Y
CELL:A1
U(A1).D1
U(B1).DQ1
EDK2516CBBH
Coupled stackup
12.000 in
80.2 , 1.770 ns
CELL:B1
DQ1 o
OSCILLOSCOPE
Design file: UNNAMED0.TLN Designer: TI
BoardSim/LineSim, HyperLynx
Date: Wednesday Aug. 4, 2004 Time: 17:40:38
Cursor 1, Voltage = 2.3mV, Time = 2.915ns
Cursor 2, Voltage = 242.6mV, Time = 6.188ns
Delta Voltage = 240.3mV, Delta Time = 3.274ns
Show Latest Waveform = YES
2000.0
1500.0
1000.0
500.0
0.000
500.0
1000.0
1500.0
2000.0
2500.0
3000.0
0.000 4.000 8.000 12.000 16.000 20.000
Time (ns)
V
o
l
t
a
g
e

m
V

Probe 3:U(B0).DQ0
Probe 4:U(B1).DQ1










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K
1 )

D
H

2
,
Max. Crosstalk +
K
1 )

D
H

2
+
1
1 )

5
10

2
+ 0.8V.
OSCILLOSCOPE
Design file: UNNAMED0.TLN Designer: TI
BoardSim/LineSim, HyperLynx
Date: Wednesday Aug. 4, 2004 Time: 17:38:41
Cursor 1, Voltage = 7.3mV, Time = 3.143ns
Cursor 2, Voltage = 90.5mV, Time = 6.368ns
Delta Voltage = 97.8mV, Delta Time = 3.226ns
Show Latest Waveform = YES
2000.0
1500.0
1000.0
500.0
0.000
500.0
1000.0
1500.0
2000.0
2500.0
3000.0
0.000 2.000 4.000 6.000 8.000 10.000 12.000 14.000 16.000 18.000 20.000
Time (ns)
V
o
l
t
a
g
e

m
V

Probe 3:U(B0).DQ0
Probe 4:U(B1).DQ1



















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l +
C
f
,




































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P
W
T
r
T
1T (3) (5)
Higher Tr reduces
amplitude of
harmonics
1
P
w
20dB/decade
T
r
1
40dB/decade
Frequency (harmonics)
Amplitude













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1
2
3
Power wiring or trace inductance
Load
cap
Power
supply
14
7
Current return path
1
2
3
Power wiring or trace inductance
Load
cap
Power
supply
14
7
Current return path













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SVS
TPS3809
V
DD
RESET
VIN
EN
TPS2034
TPS79601
EN
VIN
3.3V
SVS
V
DD
RESET
TPS3808
adjustable delay
3.3V @ 1A
1.26V @ 800mA
I/O
DSP
reset
Core
C67xx
SVS
TPS3809
V
DD
RESET
VIN
EN
TPS2034
TPS62040
EN
VIN
3.3V
SVS
V
DD
RESET
TPS3808
adjustable delay
3.3V @ 1A
1.26V @ 800mA
I/O
DSP
reset
Core
C67xx
SVS
V
DD
TPS3808










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1
2
3
Power wiring inductance
Load
cap
Power
supply
14
7
Current for charging the capacitor load
U19A
Droop + LMax
dl
dt
,
Max
dl
dt
+
1.52DV

T
r

2
C,
Droop + LMax
dl
dt
+ L
1.52DV
(T
r
)
C + 75 10
*9

1.52(2.64)
(2 10
*9)
2
50 10
*12
+ 3.76V.
























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C
R
L
VDD
Gnd
Z
c
, capacitor +
1
wC
,
Z
L
, indicator +wL,
1
wC
+wL,
w
2
+
1
LC
,
w +
1
LC

, where w + 2pf.
f +
1
2p LC

.
























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DCR
L C
f +
1
2p LC

.

R
L


















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uBGA
0.01 0.01 0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01 0.01 0.01 0.01
10uF
10uF
10uF
10uF
0.01
10uF
10uF
10uF
10uF
0.01





































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I
CRegion
+
I
Core
N
xM
I
CRegion
+C
dV
Core
dt
,
C +I
CRegion
+
dt
dV
Core
,
slow
slow slow
fast
REGION 4
REGION 1
REGION 2
REGION 3
A1
AA1 AA21
A21
I
IORegion
+
I
IO
K
xJ










































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I
IOTrans
+
V
IO
Z
o
I
IOTrans
+I
IORegion
)J I
IOTrans
I
IOTotal
+C
dV
IO
dt
,
C +I
IOTotal
dt
dV
IO
,
AA1 AA21
REGION 2
REGION 1 REGION 3
(digital PLL) (analog PLL, Y21)
REGION 4
A1 A21
Bottom view of the OMAP5910 package


































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680mA
13
x3 +157mA
180mA
21
x8 +69mA
3.3
60
x27 +1.5A
180mA
21
x4 +34mA
3.3
60
x30 +1.65A
680mA
13
x4 +290mA
180mA
21
x6 +51mA
3.3
60
x27 +1.5A

C +I
CRegion
dt
dV
Core
C +I
IOTotal
dt
dV
IO
C +157mA
(2nS)
(10mV)
+0.03mF
C +157A
(2nS)
(50mV)
+0.06mF

































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AA1 AA21
REGION 2
REGION 1 REGION 3
(digital PLL) (analog PLL, Y21)
REGION 4
A1 A21
4.7 F
0.022 F
0.022 F
0.022 F
0.022 F
0.022 F
4.7 F
Bottom view of the OMAP5910 package

































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Core
caps
IO
caps

1
2
3
14
7
DSP C1 C2
Ferrite bead, Z
Output
1
2
3
14
7
DSP C1
Output
Ferrite
bead,
Z1
Ferrite
Z2
bead,














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1
2
3
Ferrite bead
Load
cap
Power
supply
14
7
TI DSPA
V
DD
C2 C1
f
*3dB
+
1
2 p Z
o
C
1
,
f
*3dB
+
1
2 p Z C
2
,
f
*3dB
+
1
2 p Z C
2
+ 300MHz.
+
1
2 p (100)300 10
6
+ 5.3pF.






























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f
*3dB
+
1
2 p Z
1
C
1
f
*3dB
+
1
2 p Z
2
C
Load
.
f
*3dB
+
1
2 p Z
1
C
1
+ 300MHz.
+
1
2 p (100)300x10
6
+ 5.3pF.






































Adjacent P/G
Layer 1: Signal
Layer 2: Signal
Layer 3: Ground
Layer 4: Power
Layer 5: Signal
Layer 6: Signal
Poor routing layer no image plane
Best routing layer ground image plane
As close as possible for low impedance
and high parallel capacitance Cpp
Acceptable routing layer
Poor routing layer no image plane
C
pp
+k

r
A
d
, k = 0.2249 in. or 0.884 cm
e = dielectric constant = 4.1 to 4.7 for FRA
A = area
d = distance between planes

































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Nonadjacent P/G
Layer 1:
Layer 2:
Layer 3:
Layer 4:
Layer 5:
Layer 6:
Signal
Ground
Signal
Signal
Power
Signal
Acceptable routing layer
Higher power and ground impedance
Best routing layer
Acceptable routing layer
Higher power and grounding impedance
Acceptable routing layer




































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W
T
W1
H
Er
W
W1
H
T






















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PFD CP /N
REF
VCO
OUT
/M
R
C
C
f
out
+
M
N
f
in
,





































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Ideal
period
Jitter





























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t
1
t
2
t
3
Ideal period





















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PFD /N OSC
/M
f
REF f
OUT
f
OUT
+
M
N
f
IN
Digital
controller
DAC
DCO





























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VDD_3V3 VDD_PLL
L1
Ferrite
bead
C1
bead
L2
Ferrite
f
*3dB
(from_3.3V) +
1
2pZC
2
,
f
*3dB
(from_PLL) +
1
2pZC
1
,
VDD_3V3 VDD_PLL
L1
Ferrite
bead
C1
bead
L2
Ferrite
f
*3dB
(from_PLL) +
1
2pZC
1
,
f
*3dB
(from_PLL) +
1
2pZ
2
C
1
,
























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C1
VDD_3V3
C2 C3
10 F
R
VDD_PLL
C1
VDD_3V3
C2
VDD_PLL
Linear
reg
C3
10 F



































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100 300 1000 5000
55
50
45
40
35
30
25
F
i
e
l
d

s
t
r
e
n
g
t
h

(
d
B

V
/
m
)
Frequency (MHz)
Class A
Class B
48
43
34
37
216
88
960
Measuring distance = 10 m































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High speed
DSP
SDRAM
Current, I
Current, I
E +87.6 10
*16
[f
2
AI],
V
gnd
System
ground
plane
Cable
E +4.2x10
*7
[fLI]




















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dB
frequency
f
E
m
i
s
s
i
o
n
f
o
f +
1
pT
r
, where T
r
is risetime
Common mode
Differential mode
20dB/
Decade
20dB/
Decade

P
W
T
r
T
1T (3) (5)
Higher Tr reduces
amplitude of
harmonics
1
P
w
20dB/decade
T
r
1
40dB/decade
Frequency (harmonics)
Amplitude









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f
*3dB
+
1
pP
W
f
*3dB
+
1
pT
r,
,
max_trace_length +
l
20
+
c
20f
,

































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Direction of
return current
Trace
Direction of
current
flow
Return
current has a
Gaussian density distribution
H distance
above plain
Plane
Result:
Impedance mismatch
Reflections
Increased crosstalk

1
2
3
14
7
U19A
I
14081/SO 14081/SO
7
1
2
14
3
U19A
100 nF
I





























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I(peak) +
DV
Zo
+
3.3V
68
+48.5mA
V(droop) +L
dI
dt
+(1.44nH)
48.5mA
1nS
+70mV



















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Radiated Emissions from PCB
Radiated Emissions from PCB With Image Plane





















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