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Documenti di Cultura
Develop a standardized NAND Flash interface Accelerate time to market for NAND-based products
easy integration
full features
and enables faster speeds System signal reduction saves host pins Differential signaling and on-die termination improves signal integrity and allows for faster interface speeds
ONFI 2.2
Async Yes Yes 50 3.3V Sync (DDR) Yes Yes
DDR-200
Benet
More consistency among vendors Eases burden on rmware to identity features based on manufacture and device IDs Faster interface reduces data access time Lower I/O voltage means lower switching power Improves signal integrity enabling faster speeds Improves signal integrity enabling faster speeds VFBGA offers improved reliability and signal integrity Allows fastest devices to be run using slower interfaces Ability to stop the clock lowers power consumption Reports extended ECC correction details to host Improves pipelined reads Minimizes the SRAM required for lower-cost controllers Improves the ability to save host data fragments (short pages) Provides the ability to abort current erase operation for higher priority reads Improves the ability to accurately calculate power requirements for larger systems Improves writes with interleaved reads on another LUN NAND device performs ECC and provides corrected data to host Combines some signals enabling fewer signals to be routed to the host
ONFI 1.0
Yes Yes 50 1.8V
ONFI 2.3
Async Yes Yes 50 3.3V Sync (DDR) Yes Yes
DDR-200
ONFI 3.0
SDR (Async) Yes Yes 50 3.3V NV-DDR (Sync DDR) Yes Yes
DDR-200
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
TSOP LGA
TSOP LGA
TSOP LGA
TSOP LGA
BGA
DDR-200
Yes Yes
Yes Yes
SLC Flash
16K Page Performance*
333 MB/s
333 MB/s
291 MB/s
333 MB/s 8
333 MB/s
333 MB/s
333 MB/s
333 MB/s
164 MB/s
Cache Program
Cache Read
20 MB/s
41 MB/s
73 MB/s
146 MB/s
82 MB/s
Founders
onfi.org
333 MB/s