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-RE2R55B33
Submitted by: Name: Syed Mohammad Faiz Reg. Number:10902647 Name and Location of Company: DKOP Labs Pvt. Ltd.,Sector-2,Noida Period Training: 01/06/2012- 14/07/2012
Department of Electronics & Comm. Engg Lovely Professional University Phagwara140401, Punjab (India)
Ph. (01824-506960-61) Department of Electronics & Communication Engineering Lovely Professional University Phagwara (Distt. Kapurthala) Punjab India 144001 1|Page
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Ref:______________
Dated: __________
Certificate
Certified that this Training entitled VLSI Design submitted by Syed Mohammad Faiz (10902647), students of Electronics & Communication Engineering Department, Lovely Professional University, Phagwara Punjab in the partial fulfillment of the requirement for the award of Bachelors of Technology (Electronics & Communication Engineering) Degree of LPU, is a record of students own study carried under my supervision & guidance.
Mr. Sandeep Gupta Name and Signature of Training Supervisor Designation:- Chief Learning Officer
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Acknowledgement
In my six weak industrial training it is a wonderful experience to be a part of DESIGN KOP LABS where I have opportunity to work under brilliant minds. I owe my deep regards for the supporting and kind staff authorities who are helping me in my lean patches during these six weak. The knowledge I am gaining throughout my studies have the practical implementation during this period. I am grateful to all the staff of DKOP LABS and for their timely support and sharing of their experience with me. I would like to express my heartiest concern for Mr. Ajeet Kumar Singh for his able guidance and for his inspiring attitude, praiseworthy attitude and honest support. Not to forget the pain staking efforts of our college training and placement cell and specially my training and placement officer. Last but not the least I would express my utmost regards for the electronics and communication department of our Institute.
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Attachment Of Training Certificate issued from training institute with specific training area
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TABLE OF CONTENTS
S. NO. 1. 2. TITLE PAGE NO. 7 to 9 10 to 15
INTRODUCTION ORGANIZATION AND REQUIREMENT 2.1. VLSI Design Flow 2.2. HDL(Hardware Description Language) 2.2.1. Design using HDLs 2.2.2. Simulating and Debugging HDL code 2.2.3. Design verifications with HDLs 2.3. HDL and programming languages 2.4. Importance of HDLs 2.5. Advantages of HDL 2.6. Disadvantages of HDL 3. EXECUTION OF WORK 3.1. VERILOG(Verify Logic) 3.1.1. History of verilog 3.1.2. Design methodology 3.1.3. General syntax for writing VERILOG program 3.1.4. What is MODULE in verilog 3.1.5. First verilog program 3.1.6. Language elements 3.2. Different types of modeling used in verilog 3.2.1. Gate level modeling 3.2.2. Data flow modeling 3.2.2.1.Operators 3.2.3. Behavioral modeling 3.2.3.1.Types of Statements 3.2.4. Switch level modeling 3.2.4.1.... Cmos(complimentary metal oxide semiconducator) 3.2.4.2.Cmos inverter 3.3. FPGA(Field Programmable Gate Array) 3.3.1. FPGA Comparisons 3.3.2. FPGA Architecture 3.3.3. FPGA Design and Programming 3.4. CPLD(Complex Programmable Logic Device) 4. HARDWARE/ SOFTWARE IMPLIMENATION 4.1. EDA(Electronic Design Automation) tools 4.1.1. History of EDA tools 4.1.2. Current status 4.2. Software focuses on Design 4.3. Modelsim simulator 4.3.1. Introduction 4.3.2. Creating the working library 5|Page
16 to 44
45 to 48
ROLL NO.-RE2R55B33 4.3.3. Project flow 4.3.4. Multiple library flow SIMULATIVE/ HARWARE ANALYSIS 5.1. UART 5.2. UART Specifications 5.3. UART Receiving Subsystem 5.4. UART Transmitting Subsystem 5.5. Entire UART System REFERENCES FUTURE SCOPE OF TRAINING
5.
49 to 50
6. 7.
51 52
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1. INTRODUCTION
What is an IC (integrated circuit)? A chip or die where many circuit components and the wiring that connects them are manufactured simultaneously. Integrated circuits are used in almost all electronic equipment in use today and have revolutionized the world of electronics. A hybrid integrated circuit is a miniaturized electronic circuit constructed of individual semiconductor devices, as well as passive components, bonded to a substrate or circuit board. Integrated circuits were made possible by experimental discoveries which showed that semiconductor devices could perform the functions of vacuum tubes and by mid-20th-century technology advancements in semiconductor device fabrication the integration of large numbers of tiny transistors into a small chip was an enormous improvement over the manual assembly of circuits using electronic components. The integrated circuit's mass production capability, reliability, and building-block approach to circuit design ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. There are two main advantages of ICs over discrete circuits: cost and performance. Cost is low because the chips, with all their components, are printed as a unit by photolithography and not constructed as one transistor at a time. Furthermore, much less material is used to construct a circuit as a packaged IC die than as a discrete circuit. Performance is high since the components switch quickly and consume little power (compared to their discrete counterparts) because the components are small and close together
ROLL NO.-RE2R55B33 assembly work (because of fewer separate components), and a number of other advantages. Further development, driven by the same economic factors, led to "Large-Scale Integration" (LSI) in the mid 1970s, with tens of thousands of transistors per chip. Integrated circuits such as 1K-bit RAMs, calculator chips, and the first microprocessors, that began to be manufactured in moderate quantities in the early 1970s, had under 4000 transistors. True LSI circuits, approaching 10000 transistors, began to be produced around 1974, for computer main memories and second-generation microprocessors The final step in the development process, starting in the 1980s and continuing through the present, was "very large-scale integration" (VLSI). The development started with hundreds of thousands of transistors in the early 1980s, and continues beyond several billion transistors as of 2009. There was no single breakthrough that allowed this increase in complexity, though many factors helped. Manufacturers moved to smaller rules and cleaner fabs, so that they could make chips with more transistors and maintain adequate yield.
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Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. The term is no longer as common as it once was, as chips have increased in complexity into billions of transistors Uses photolithography to fabricate transistors, wires, on silicon wafers. Common technologies used used in VLSI are CMOS, Bipolar, Bi Cmos, etc.
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ROLL NO.-RE2R55B33 This design is usually used by the VLSI designers who uses HDLs (Hardware Description Language).in any design, specifications are written first. Specifications describe abstractly the functionality, interface, and overall architecture of the digital circuit to be designed. At this point the architects do need to think about how they will implement this circuit. A behavioral is then created to analyze the design in terms of functionality, performance, compliance to standards and other high level issues. Behavioral descriptions are written with HDLs. The behavioral description is manually converted to an RTL description in an HDL.The designers have to describe the dataflow that will implement the desired digital circuit. From this point onward, the design process is done with the help of EDA tools. Logic synthesis tools convert the RTL description to a gate level net list. A gate level net list is a description of circuit in terms of gates and connections between them. Logic synthesis tools ensure that gate level net list meets timing, area and power specifications. The gate level net list is a input to the place and route tool, which creates a layout. The layout is verified and then fabricated into the chip. Thus, most digital design activity is concentrating manually on optimizing the RTL description of the circuit.. After the RTL description is frozen, EDA tools are available to assist the user for the further processes. Designing at RTL level has shrunk the design cycle times from years to few months. It is also possible to do many design iterations in a short period of time. Behavioral synthesis tools have been emerged recently. These tools can create RTL description from a behavioral or algorithmic description of the circuit. As these tools mature, digital circuit design will become similar to high level computer programming. Designer will simply implement the HDL in algorithm in an HDL at a very abstract level. EDA tools will help the designers convert the behavioral descriptions to the final IC chip. It is note that although EDA tools are available to automate the processes and cut design cycle times, the designer is still the person who controls how the tool will work. EDA tools are susceptible to the GIGO: garbage in garbage out phenomenon. If used improperly the EDA tools will lead to inefficient designs. Thus, the designers still needs to understand the nuances of design methodologies, using EDA tool to obtain optimize design.
ROLL NO.-RE2R55B33 attribute of hardware. Languages whose only characteristic is to express circuit connectivity between a hierarchy of blocks are properly classified as net list languages used on electric computer-aided design (CAD). HDLs are used to write executable specifications of some piece of hardware. A simulation program, designed to implement the underlying semantics of the language statements, coupled with simulating the progress of time, provides the hardware designer with the ability to model a piece of hardware before it is created physically. It is this executability that gives HDLs the illusion of being programming languages. Simulators capable of supporting discrete-event (digital) and continuous-time (analog) modeling exist, and HDLs targeted for each are available. It is certainly possible to represent hardware semantics using traditional programming languages such as C++, although to function such programs must be augmented with extensive and unwieldy class libraries. Primarily, however, software programming languages do not include any capability for explicitly expressing time and this is why they do not function as a hardware description language. Before the recent introduction of SystemVerilog, C++ integration with a logic simulator was one of the few ways to use OOP in hardware verification. SystemVerilog is the first major HDL to offer object orientation and garbage collection.
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ROLL NO.-RE2R55B33 cannot be proven because they occupy an unbounded solution space. However, if provided a set of operating assumptions or constraints, a property checker can prove (or disprove) more properties, over the narrowed solution space. The assertions do not model circuit activity, but capture and document the "designer's intent" in the HDL code. In a simulation environment, the simulator evaluates all specified assertions, reporting the location and severity of any violations. In a synthesis environment, the synthesis tool usually operates with the policy of halting synthesis upon any violation. Assertion-based verification is still in its infancy, but is expected to become an integral part of the HDL design toolset.
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A Hardware Description Language (HDL) is a software programming language used to model the intended operation of a piece of hardware EDA tools are computer based software systems to design Very Large Scale Integrated circuits. Now EDA tools are available for almost every stage of VLSI design flow. But to start with we must convey design idea (that is in our mind) to EDA tool in such a way that the tool is able to understand that and generate a highly optimized design implementation. This transfer of idea from human beings to machines is called Design Entry. There are two methods of design entry: graphical and textual. Graphical method includes schematic entry and state diagram entry while textual method implies use of HDL's (Hardware Description Languages). Graphical method works fairly well up to a certain level of circuit complexity but in larger circuits they become cumbersome and time consuming.
Support for hardware concurrency and time frame are two main features that distinguishes HDLs from other programming language.
ROLL NO.-RE2R55B33 In the semiconductor and electronic design industry, Verilog is a hardware description language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL, is most commonly used in the design, verification, and implementation of digital logic chips at the register transfer level (RTL) of abstraction. It is also used in the verification of analog and mixed-signal circuits.
ROLL NO.-RE2R55B33 Verilog-2001 is the dominant flavor of Verilog supported by the majority of commercial EDA software packages. Verilog 2005 Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-2005) consists of minor corrections, spec clarifications, and a few new language features (such as the uwire keyword). A separate part of the Verilog standard, Verilog-AMS, attempts to integrate analog and mixed signal modelling with traditional Verilog. SystemVerilog SystemVerilog is a superset of Verilog-2005, with many new features and capabilities to aid design-verification and design-modeling.
TOP MODULE
SUB MODULE 1
SUB MODULE 2
SUB MODULE 3
cell
cell
cell
Sub Module 4
Sub Module5
cell
cell
cell
cell
cell
cell
cell
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<Module Internals>
... ...
Endmodule
Syntax :
module Module_Name(Port_List) ; <Port Declarations> <Internal Signals Declaration> <Functionality> endmodule The port list in module definitions contains names of ports (terminals) only and we must specify whether they are input, output or bi-directional terminals. So port declarations are the first thing we write in module internals. Ports are declared using Verilog keywords input, output and inout. Keyword inout is used for bi-directional ports. All internal signals between various hardware units must be assigned some name and declared its type. So second thing we write in module internals is internal signal declaration. Then follows the actual module functionality.
ROLL NO.-RE2R55B33 box with input and output terminals and that black box interacts with the outside environment through these terminals only. The relationship between these input and output terminals is hidden from the environment. Every module definition begins with a keyword module and ends with keyword endmodule. Only within these two keywords functionality of a module is specified. Each module has a module name and port list. Module name is an identifier for that particular module and port list contains the list of all input and output terminals for the module. To build a full adder from the half adder defined just now we have to create an instance of halfadder module in fulladder module. This instance is given a name and ports are connected appropriately. Certain predefined modules of basic hardware elements are provided in Verilog and we call them as primitives. These primitives can be instantiated inside modules in same way but giving them names is optional. So a module may contain instances of primitives and other modules.
in1 in2
sum
carry
module half_adder(sum, carry, in1, in2) ; output sum, carry ; input in1, in2 ; xor (sum, in1, in2) ; and (carry, in1, in2) ; endmodule
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carry_in a b HALF ADDER HALF ADDER sum
carry_out
module full_adder(sum, carry_out, a, b, carry_in) ; output sum, carry_out ; input a, b, carry_in ; wire w1, w2, w3; half_adder ha1(w1, w2, a, b); half_adder ha2(sum, w3, w1, carry_in); or (carry_out, w2, w3); endmodule
and
can
be
inserted
for
better
Comments
// The rest of the line is a comment. /* Multiple line comments */ /* Nesting /* comments */ is NOT allowed */ Comments make life easier for you and others also. So insert a lot of meaningful comments in your code
Operators
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a=~b;
Signal Values
0 1 x or X z or Z Logic Zero Logic One Unknown High Impedance
Representation of Number
Decimal Hex Octal Binary d or D h or H o or O b or B
Syntax
<size> '<radix> <number> size specifies number of bits to be occupied by number and is written only in decimal. radix determines the arithmetic base of number. number is the value expressed in the indicated base only. Number 2'b10 3'd6 6'o57 3'O4 8'H2d 32'haA19 5'B110x0 6'ozz 12'hZXb #Bits Base 2 3 6 3 8 Hex 32 Hex 5 Binary 6 12 Hex Storage Binary 10 Decimal 110 Octal 101111 Octal 100 00101101 1010101000011001 110x0 Octal zzzzzz zzzzxxxx1011
Number Format
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If we do not specify the size it takes default value which is machine and simulation dependent but is at least 32 bits. Also if we do not specify radix default is decimal base. Number 'bz 'h9 3 #Bits >= 32 >= 32 >= 32 Base Binary Hex Decimal Storage zz..zzz 0000..1001 000...011
If the size is greater than the value of number, the number in the most significant bit is extended for MSB = 0, x or z zero extended if MSB = 1. Number 8'bx001 5'o1 15'hzf 9'd5 #Bits 8 5 15 9 Hex Base Binary Storage xxxxx001 Octal 00001 zzzzzzzzzzz1111 Decimal 000000101
For negative numbers we place a minus sign before the number representation. Negative numbers are stored as 2's complement. Number #Bits Base Storage -6'd3 6 Decimal 111101 -3'b11 3 Binary 101 Underscores can be inserted in numbers to enhance readability and are ignored by Verilog. 12'b000111010100 12'b000_111_010_100
Identifiers are names given to different objects so that they can be referenced in design. An identifier is any sequence of letters [A-Z] and [a-z], digits [0-9], underscore [ _ ] and $ character. Cannot begin with $ or digits and are case sensitive. An identifier may contain up to 1024 characters. myid m_y_id 3my_id $myid _myid4 valid valid invalid invalid valid
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Keywords
Keywords are special words reserved by language, their meaning is Predefined and cannot be used as identifiers. All keywords are in lowercase.
always and assign begin buf bufif0 bufif1 case casex casez cmos deassign default defparam disable edge else end endcase endfunction endmodule endprimitive endspecify endtable endtask event
for force forever fork function highz0 highz1 if initial inout input integer join large rpmos medium module nand negedge nmos nor not notif0 notif1 output parameter
supply1 posedge table primitive task pull0 time pull1 tran pulldown tranif0 pullup tranif1 rcmos tri real tri0 realtime tri1 reg triand release trior repeat trireg rnmos vectored wait wire rtran xor rtranif0 rtranif1 scalared small specify xnor strength strong0 strong1 supply0
pmos
Data types
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Nets
Nets represent the interconnection between hardware elements. Value of a net variable is determined throughout the simulation by output of the components they are connected to (called Drivers). If no driver is connected to a net, the net defaults to a value of Z. Most commonly used type of net is wire. module my_ckt (f, a, b, c, d, e); output f ; input a, b, c, d, e ; wire n1; wire m1, x0, x1 ; endmodule keyword wire. 24 | P a g e In above circuit n1, m1, x0, x1 are nets. They are declared inside module by
ROLL NO.-RE2R55B33 Some other type of nets will be discussed later in advance Verilog concepts. Any undeclared nets default to type wire.
a b
n1 x0
c d
m1 x1
Registers
Register Type reg integer time real realtime Usage Stores a logic value Supports computation Stores time as a 64-bit unsigned quantity Stores values (e.g. delays) as real numbers Stores time values as real numbers
Registers are variables that store values. It is an abstraction of a hardware storage element, but it need not correspond directly to physical storage elements in a circuit. Registers retain value until another value is placed onto them.Unlike a net, a register does not need a driver. A register object may be assigned value within a procedural statement, a user sequential primitive,task, or function.
REG The reg kind of register data type is the one most commonly used. A reg data type models the feature of hardware that allows a logic value to be stored in a flip-flop or a latch. A reg object may never be the output of primitive gate or the target of a continuous assignment. The default value for a reg data type is X. 25 | P a g e
ROLL NO.-RE2R55B33 INTEGER The integer data type supports numeric computation in procedural code. Integers are represented internally to the word length of the host machine (at least 32 bits). A negative number is stored in 2s complement format. Registers declared as data types reg store values as unsigned quantities,whereas integers store values as signed quantities. REAL Accurate modeling of delay values might require the use of real data types. Real objects are stored in double precision, typically a 64-bit value. Real values can be specified in decimal and exponential notation. An object of type real may not be connected to a port or terminal of a primitive.Real numbers cannot have a range declaration and their default value is 0. TIME The data type time supports time-related computations within procedural code in Verilog models. Time variables are stored as unsigned 64-bit quantities. A variable of type time may not be used in a module port; nor may it be an input or output of a primitive. Data type realtime stores time values in real number format. The system function $time is invoked to get the current simulation time.
Constants
A constant in Verilog is declared with the keyword parameter, which declares and assigns values to the constant. The value of a constant may not be changed during simulation but parameters (or constants) can be changed at module instantiation or by using the defparam statement. parameter high_index = 22 ; parameter av_delay = (min_delay + max_delay) / 2 ; parameter initial_state = 8b1011_1000 ;
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Primitives
Verilog provides a robust set of built-in gate primitives. Primitives are like predefined modules. A logic circuit is described on gate to gate basis using these primitives. Primitives can be instantiated only within modules and use of identifier name with primitive instantiation is optional. The port list of a primitive have output(or outputs) written first, followed by inputs. AND if any of the input is 0, output is 0 else if any of input is x or z , output is x else if all inputs are 1, output is 1 NAND if any of the input is 0, output is 1 else if any of input is x or z , output is x else if all inputs are 1, output is 0 OR if any of the input is 1, output is 1 else if any of input is x or z , output is x else if all inputs are 0, output is 0 NOR if any of the input is 1, output is 0 else if any of input is x or z , output is x else if all inputs are 0, output is 1
XOR if any of the input is x or z, output is x else if odd number of inputs are 1, output is 1 else output is 0 XNOR if any of the input is x or z, output is x 27 | P a g e
ROLL NO.-RE2R55B33 else if even number of inputs are 1, output is 1 else output is 0 BUF if input is 1, output is 1 else if input is 0, output is 0 else if input is x or z, output is x NOT if input is 1, output is 0 else if input is 0, output is 1 else if input is x or z, output is x We can instantiate multiple primitives of same type by a single statement using comma-separated lists e.g. nand G1(y1, a1, a2, a3), (y2, b1, b2, b3), M2(d3, e1, e2);
Verilog gate level description of a and-or-invert logic gate module AOI(out, in1, in2, in3, in4) ; output out ; input in1, in2, in3, in4 ; wire y1, y2 ; and (y1, in1, in2) ; and a1(y2, in3, in4) ; nor (out, y1, y2); endmodule
in1 in2 y1 out in3 in4 y2
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assign sum = a ^ b ^ cin ; assign cout = (a & cin) | (b & cin) | (a & b) ;
endmodule Verilog has a robust set of built-in operators that manipulate the various types of data implemented in the language to produce values on nets and registers. Some of the operators are used within expressions on right-hand side of continuous assignment statements and procedural statements; others are used in Boolean expressions in conditional statements or with conditional operators.
3.2.2.1 Operators
Functional Group Logical && || ! Bitwise & | ~ ^ ~^ or ^~ Reduction & 30 | P a g e Reduction and Bitwise and Bitwise or Bitwise not Bitwise xor Bitwise xnor Logical and Logical or Logical not Operator Name
ROLL NO.-RE2R55B33 ~& | ~| ^ ~^ or ^~ Shift >> << Right Shift Left Shift Reduction nand Reduction or Reduction nor Reduction xor Reduction xnor
Operator
Name
Concatenation Replication
Greater than Less than Greater than or equal to Less than or equal to
Conditional
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Logical Operators
&& || ! - logical AND - logical OR - logical NOT
Logical operators evaluates to one bit value 0, 1, or x. These operators gives result on the basis of logical values of operands I.e. If operand has zero value, it is taken as logical false (0) If operand has non-zero value, it is taken as logical true (1) If a bit in any of the operand is x or z, whole operand is treated as x
A && B A || (!B) C || B
1 && 0 1 || 1 x || 0 x && 0 0
0 1 x
Reduction Operators
& | 32 | P a g e Reduction AND Reduction OR
ROLL NO.-RE2R55B33 ^ ~& ~| ~^ or ^~ Reduction XOR Reduction NAND Reduction NOR Reduction XNOR
Reduction operators are unary operators i.e. they act on single operands. They create a single-bit result by operating on a multibit operand. &(010101) a = 4b1001 b = ^a |(010x10) b=1^0^0^1 0|1|0|x|1|0 b=1 1 0&1&0&1&0&1 0
Bitwise Operators
& | ~ ^ ~^ - bitwise AND - bitwise OR - bitwise NOT - bitwise XOR - bitwise XNOR
Bitwise operators acts on individual bits of the operands. The operands may be scalar or vector. If one of the operand is shorter than the other, it will be zero extended to match the length of the longer operand. The bitwise not operator negates the individual bits of an operand. a = 4b1010 b = 4b1100 c = ~a d=a&b e = (101011) ^ b c = ~(1010) d = 1010 & 1100 e = 101011 ^ 1100 c = 0101 d = 1000 e = 101011 ^ 001100 e = 100111
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Shift Operators
>> << shift right shift left
Verilog shift operators operate on a single operand and shift (left or right) the bit pattern of the operand by a specified number of positions, filling zeroes in the position that are vacated. a = 4b1010 d = a >> 2 c = a << 1 d = 0010 c = 0100
Concatenation Operators
{ op1, op2, } This operator concatenates op1, op2, to a single number. The operand should be sized, no unsized constant operand is allowed. If the operand A is bit pattern 1011 and the operand B is the bit pattern 0001, then {A, B} is the bit pattern 1011_0001 {0011, {{01}, {10}}} = 0011_0110 Replication of same operand can be expressed by using a replication constant which specifies how many times to replicate the number inside the brackets ({ }). a = 1b1 b = 3b010 c = 3b101 catr = { 4{a}, b, 2{c} } catr = {1, 1, 1, 1, 010, 101, 101} Relational Operators > < >= <= greater than less than greater than or equal to less than or equal to 34 | P a g e
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The Verilog relational operators compare operands and produce a Boolean 0 or 1 (true or false) result. If any bit in one of the operands is unknown (x), the result is unknown.
ROLL NO.-RE2R55B33 must be enclosed within Sequential begin - end block Parallel fork - join block When using begin-end, we can give name to that group. This is called Named blocks.
Sequential statement
The begin - end keywords: Group several statements together. Cause the statements to be evaluated in sequentially (one at a time). Any timing within the sequential groups is relative to the previous statement. Delays in the sequence accumulate (each delay is added to the previous delay) Block finishes after the last statement in the block.
Conditional statement:
The if - else statement controls the execution of other statements, In programming language like c, if - else controls the flow of program. if (condition) statements; if (condition) statements; else statements; if (condition) statements; else if (condition) statements; ................ ................ else statements;
Case statement:
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ROLL NO.-RE2R55B33 The case statement compares a expression to a series of cases and executes the statement or statement group associated with the first matching case ? case statement supports single or multiple statements. ? Group multiple statements using begin and end keywords. case (<expression>) <case1> : <statement> <case2> : <statement> ..... default : <statement> endcase
Looping statement:
Looping statements appear inside a procedural blocks only, Verilog has four looping statements like any other programming language. forever repeat while for
ROLL NO.-RE2R55B33 q = d assignment runs when clock rises: exactly the Behavior you expect
ROLL NO.-RE2R55B33 logic functions on a chip. It was primarily this reason why CMOS won the race in the eighties and became the most used technology to be implemented in VLSI chips
CMOS Inverter (NOT gate) 3.3 FPGA(Field Programmable Gate Array) A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturinghence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial re-configuration of a portion of the design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together" somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.In addition to digital functions, some FPGAs have analog features. The most common analog feature is programmable slew rate and drive strength on each output pin, allowing the engineer to set slow rates on lightly loaded pins that would 39 | P a g e
ROLL NO.-RE2R55B33 otherwise ring unacceptably, and to set stronger, faster rates on heavily loaded pins on highspeed channels that would otherwise run too slow.Another relatively common analog feature is differential comparators on input pins designed to be connected to differential signaling channels. A few "mixed signalFPGAs" have integrated peripheral analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip.[5] Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.
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ROLL NO.-RE2R55B33 An application circuit must be mapped into an FPGA with adequate resources. While the number of CLBs/LABs and I/Os required is easily determined from the design, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. For example, a crossbar switch requires much more routing than a systolic array with the same gate count. Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, FPGA manufacturers try to provide just enough tracks so that most designs that will fit in terms of Lookup tables (LUTs) and IOs can be routed. This is determined by estimates such as those derived from Rent's rule or by experiments with existing designs. In general, a logic block (CLB or LAB) consists of a few logical cells (called ALM, LE, Slice etc.). A typical cell consists of a 4-input LUT, a Full adder (FA) and a D-type flip-flop, as shown below. The LUTs are in this figure split into two 3-input LUTs. In normal mode those are combined into a 4-input LUT through the left mux. In arithmetic mode, their outputs are fed to the FA. The selection of mode is programmed into the middle multiplexer. The output can be either synchronous or asynchronous, depending on the programming of the mux to the right, in the figure example. In practice, entire or parts of the FA are put as functions into the LUTs in order to save space.
Simplified example illustration of a logic cell. ALMs and Slices usually contains 2 or 4 structures similar to the example figure, with some shared signals.CLBs/LABs typically contains a few ALMs/LEs/Slices.In recent years, manufacturers have started moving to 6-input LUTs in their high performance parts, claiming increased performance. Since clock signals (and often other high-fanout signals) are normally routed via specialpurpose dedicated routing networks in commercial FPGAs, they and other signals are separately managed. For this example architecture, the locations of the FPGA logic block pins are shown below.
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Logic Block Pin Locations Each input is accessible from one side of the logic block, while the output pin can connect to routing wires in both the channel to the right and the channel below the logic block. Each logic block output pin can connect to any of the wiring segments in the channels adjacent to it. Similarly, an I/O pad can connect to any one of the wiring segments in the channel adjacent to it. For example, an I/O pad at the top of the chip can connect to any of the W wires (where W is the channel width) in the horizontal channel immediately below it. Generally, the FPGA routing is unsegmented. That is, each wiring segment spans only one logic block before it terminates in a switch box. By turning on some of the programmable switches within a switch box, longer paths can be constructed. For higher speed interconnect, some FPGA architectures use longer routing lines that span multiple logic blocks. Whenever a vertical and a horizontal channel intersect, there is a switch box. In this architecture, when a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent channel segments. The pattern, or topology, of switches used in this architecture is the planar or domain-based switch box topology. In this switch box topology, a wire in track number one connects only to wires in track number one in adjacent channel segments, wires in track number 2 connect only to other wires in track number 2 and so on. The figure below illustrates the connections in a switch box.
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Switch box topology Modern FPGA families expand upon the above capabilities to include higher level functionality fixed into the silicon. Having these common functions embedded into the silicon reduces the area required and gives those functions increased speed compared to building them from primitives. Examples of these include multipliers, generic DSP blocks, embedded processors, high speed IO logic and embedded memories. FPGAs are also widely used for systems validation including pre-silicon validation, postsilicon validation, and firmware development. This allows chip companies to validate their design before the chip is produced in the factory, reducing the time-to-market. To shrink the size and power consumption of FPGAs, vendors such as Tabula and Xilinx have introduced new 3D or stacked architectures. Following the introduction of its 28 nm 7-series FPGAs, Xilinx revealed that several of the highest-density parts in those FPGA product lines will be constructed using multiple dice in one package, employing technology developed for 3D construction and stacked-die assemblies. The technology stacks several (three or four) active FPGA dice side-by-side on a silicon interposer a single piece of silicon that carries passive interconnect.
ROLL NO.-RE2R55B33 process is complete, the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure the FPGA. This file is transferred to the FPGA/CPLD via a serial interface (JTAG) or to an external memory device like an EEPROM.The most common HDLs are VHDL and Verilog, although in an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves to raise the abstraction level through the introduction of alternative languages. National Instrument's LabVIEW graphical programming language (sometimes referred to as "G") has an FPGA add-in module available to target and program FPGA hardware.To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called IP cores, and are available from FPGA vendors and third-party IP suppliers (rarely free, and typically released under proprietary licenses). Other predefined circuits are available from developer communities such as OpenCores (typically released under free and open source licenses such as the GPL, BSD or similar license), and other sources. In a typical design flow, an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results. Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors. Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values backannotated onto the netlist.
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4.3.1 Introduction:
ModelSim is a verification and simulation tool for VHDL, Verilog, SystemVerilog, and mixedlanguage designs.This lesson provides a brief conceptual overview of the ModelSim simulation environment.It isdivided into fourtopics, which you will learn more about in subsequent lessons. Basic simulation flow. Project flow . Multiple library flow 46 | P a g e
ROLL NO.-RE2R55B33 Debugging tools Basic simulation 1. 2. 3. 4. Create a working library Compile design files Load and Run simulation Debug results
ROLL NO.-RE2R55B33 Add files to the project Compile design files Run simulations Debug results
As you can see, the flow is similar to the basic simulation flow. However, there are twoimportant differences: You do not have to create a working library in the project flow; it is done for you automatically. Projects are persistent. In other words, they will open every time you invoke ModelSim unless you specifically close them.
You can also link to resource libraries from within a project. If you are using a project, you would replace the first step above with these two steps: create the project and add the testbench to the project.
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ROLL NO.-RE2R55B33 of data bits and stop bits, and whether parity is being used. Common baud rates are 2400, 4800, 9600 and 19,200.
The interface circuit provides a buffer and status between the UART and the computer or FPGA.
ROLL NO.-RE2R55B33 However, instead of introducing another cnter, the transmitter usually shares the baud rate generator and uses an internal cnter to cnt through the 16 ticks.
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