Elonics E4000 - Low Power CMOS Multi-Band Tunner - Hardware Design Guide

Hardware Design Guide
Filename Document Number Version Modified Date Hardware Design Guide 1v3 1v4 June 2010
CONFIDENTIAL
Elonics Ltd Alba Centre Livingston EH54 7EG Tel: +44 1506 402 360 Fax: +44 1506 402 361 Web: www.elonics.com
Elonics E4000 Hardware Design Guide Rev 1v4
Copyright 2010 Elonics Ltd 1
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TOP TIPS TO GET BEST PERFORMANCE 1. 2. 3. Use low noise LDO for tuner Keep RF input track short Use recommended external components for the tuner Do not route tuner clock source close to noisy signals and do not route reference clock tracks close to sensitive areas of the PCB, e,g, RF input, LNAGND and LNAVDD Connect pins LNAGND, LNAGND2 and RFSHIELD to separate low noise ground plane
4.
5.
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E4000 KEY DESIGN CONSIDERASTIONS This hardware design guide is intended to assist in the layout of products using the Elonics E4000 RF tuner IC and to maximise system performance. Key layout considerations are listed below. More details relating to these may be found throughout the remainder of the hardware guide.
1. POWER SUPPLIES a. The E4000 1V5 supply must be low noise, >60dB PSRR. The supply should be generated using a low noise LDO regulator, not a DC/DC convertor. 2. RF INPUT TRACK AND PLACEMENT a. The RF track from the antenna connector to the tuner input should be kept as short as possible. This track should be designed as a 50 or 75R impedance line (to match the antenna). This track must run above a solid ground plane. b. The RF signal ground return path should be as low inductance as possible. E4000 pins 4, 6, 7 should connect to a solid ground plane that runs below the RF track. If there are multiple planes on different layers, these should be tied together using ground stitching vias particularly around the RF tracks and RF connector. c. In some applications such as a mobile phone there may be strong blocking signals present. The user may wish to add a filter before the tuner to eliminate the effect of these.
3. EXTERNAL COMPONENTS a. The E4000 should have 100nH inductors connected to AVDD, DVDD, DGND, PLL_VDD, and PLL_GND pins and placed as close as possible to the pin. These isolate tuner VDD domains from the sensitive analogue domains preventing noise degrading sensitivity performance.
b. TUN_DVDD and AVDD pins should have a 100pF decoupling capacitor placed to ground close to the E4000 pins. 100pF is effective in decoupling signals in the VHF and UHF frequency ranges. It is recommended that the Tuner Analogue Ground and LNA domains have an additional 100nF capacitor which will also filter lower frequency noise. Decoupling capacitors should be placed on the tuner side of any inductors.
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4. TUNER AND DEMODULATOR CLOCKS a. Do not route E4000 1V5 supply directly above the clock track and vias. This minimises coupling between the supply and reference clock in order to prevent pickup on the supply line of clock tones. In some applications, it may be possible for the E4000 tuner to share a clock with the demodulator. In this case, additional care must be taken with the routing of the clock track. Any noise that is coupled to the clock will pass to the tuners local oscillator and will degrade performance. The clock track is one of the most sensitive nets on the PCB. Any noise that gets onto this line will be amplified in the tuner and will make the local oscillator signal inside the tuner noisy (thus degrading sensitivity). Track should be routed so that it is shielded from any noisy signals. b. The E4000 may be used in a system that will power down the tuner when it is not used (e.g. a mobile phone). It is recommended that the tuner is shut down by the dedicated hardware input, NOT by disabling the 1V5 regulator to the tuner. This eliminates the possibility of phantom powering effects which may damage the tuner.
USB DONGLE DESIGN (FURTHER CONSIDERATIONS) 1. In a USB dongle, care must be taken with the design of the USB tracks. These are digital lines running at 480Mb/s so any imperfections in layout may result in noise from these lines coupling to the tuner and degrading sensitivity performance. The USB lines should be routed as a 90 Ohm differential impedance pair. These should be routed above a solid ground plane providing the return current path. Grounds should contain stitching vias around the USB tracks and connector. 2. USB tracks should have constant width and separation. Tracks should be routed as differential lines with the same track width and track separation so that 90 Ohm differential impedance is maintained. Track width = 250um. Separation from edge of one track to other = 150um
3. Some noisy PCs may inject noise through the USB lines. It is recommended that a common mode filter is placed in the USB tracks to prevent this noise coupling onto the dongle. This filter should be placed at the USB connector end of the lines.
4. Some PCs may isolate the USB connector chassis and electrical ground. The USB
electrical ground pin must be connected to the dongle ground plane. It is recommended that chassis ground is not connected on the dongle as noise may be coupled to the USB dongle.
Elonics E4000 Hardware Design Guide Rev 1v4 Copyright 2010 Elonics Ltd 4
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SET TOP BOX DESIGN (FURTHER CONSIDERATIONS
1. Use a series termination resistor of 33 Ohms for all MPEG data lines. The MPEG data lines are high speed digital lines. The series termination resistors combined with the capacitance of the connected IC input will provide an RC filter that will slow edges removing very high frequency harmonics and prevent these from coupling to the tuner and acting as noise. 2. In a set top box where there is an HDMI connection, the HDMI clock rate is typically 148MHz. Care must be taken to ensure that HDMI noise (148MHz or harmonics of this) do not couple to the tuner via supply or ground domains. It is recommended that the HDMI chip is physically separated from the tuner. 3. If a mobile phone or other RF device is used near the antenna of the E4000 (such as with an indoor aerial, it may pickup spurious GSM or other RF interferers affecting device performance. In such circumstances, it may be appropriate to use a filter that will pass all the UHF frequencies whilst attenuating GSM phone signals. Please contact Elonics for design suggestions.
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E4000 PIN INFORMATION
TUN_DGND1
TUN_DGND0
AVDD
AGND VBG REXT RFSHIELD RFIN LNAGND LNAGND2 LNAVDD
XTAL
Top view
TUN_DVDD
PLL_GND
PLL_VDD
CLOCKIN
CKOUTP CKOUTN GAIN1
Elonics E4000
GAIN0 IVOUTP IVOUTN QVOUTP QVOUTN
IFVDD
IFGND
A0
A1
STBYB
PDNB
SDAT
SCLK
QFN32 5x5mm
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PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name AGND VBG REXT RFSHIELD RFIN LNAGND LNAGND2 LNAVDD IFVDD IFGND A0 A1 STBYB PDNB SDAT SCLK QVOUTN QVOUTP IVOUTN IVOUTP GAIN0 GAIN1 CKOUTN CKOUTP TUN_DVDD TUN_DGND 0 TUN_DGND 1 CLOCKIN XTAL PLL_GND PLL_VDD AVDD Type Ground Analogue Output Analogue Output Ground Analogue Input Ground Ground Supply Supply Ground Digital Input Digital Input Digital Input Digital Input Digital I / O Digital Input Analogue Output Analogue Output Analogue Output Analogue Output Digital/PWM Digital/PWM LVDS or CMOS output LVDS or CMOS output Supply Ground Ground Oscillator Oscillator Ground Supply Supply Description 0V. Connect to Tuner analogue ground Band gap voltage. A 10nF decoupling capacitor should be placed between this pin and 0V. The capacitor should be placed close to this pin. Reference current generation. A 10k, 1%, resistor should be placed between this pin and 0V. RF Shield, connect to LNAGND RF input. 50R impedance. 0V 0V, connect to LNAGND 1.5V 1.5V 0V Tuner I C device address control (bit 0). (3.3V tolerant). Tuner I C device address control (bit 1). (3.3V tolerant). Normal operation = 1.5V (3.3V tolerant). Standby = 0V. If unused, connect AVDD Normal operation = 1.5V (3.3V tolerant). Power down = 0V. If unused, connect AVDD 2 I C data. Pull up to 1.5V (3.3V tolerant). Pull up resistor > 4.5k 2 I C clock input. (3V3 tolerant). Q Channel Output -ve Q Channel Output +ve I Channel Output -ve I Channel Output +ve Gain control input. Either digital IF or IF PWM input (3V3 tolerant). Gain control input. Either digital IF or RF PWM input (3V3 tolerant). Clock Output ve. If unused, should be left as no connect. Clock Output +ve. If unused, should be left as no connect. 1.5V 0V 0V Connect to crystal OR Clock input from external source (1.5V logic levels). Connect to crystal. If unused, should be left as no connect. 0V. Do not connect directly to LNAGND 1.5V 1.5V
2 2
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REFERENCE SCHEMATIC
TUNER DVDD (+1.5V) TUNER AVDD (+1.5V)
L6 100nH AVDD 25 C10 100pF TUN_DVDD PLL_VDD IFVDD 27 26 L3 100nH Tuner Ground TUN_DGND1 TUN_DGND0 LNAVDD 32 31 9 8
L2 L1 100nH 100nH
E4000
AGND0 LNAGND2 RFSH ELD 1 7 4
C3
C2
C5
C11
C12 100pF
100pF 100nF
100pF 100pF
L4 100nH
L5 100nH
FIT OPTION CLOCKIN 28 CLOCKIN
LNAGND IFGND PLL_GND 29 XTAL
6 10 30 Tuner Ground
IVOUTP CONNECT TO LNAGND C4 RFIN_1 100pF QVOUTP GAIN0 21 GA N0 5
20
C9 IVOUTP 100nF C8 IVOUTN 100nF IF OUTPUTS
IVOUTN
19
RF INPUT
RFIN_1 18 C7 QVOUTP 100nF C6 QVOUTN 100nF
AGC CONTROL INPUTS
QVOUTN
17
GAIN1
22
GA N1
I2C ADDRESS SELECT
A0
11
A0
CKOUTP
24
CKOUTP
A1
12 A1
CKOUTN
23
CKOUTN
MICRO CONTROL I/F
SDAT
15
SDAT REXT VBG
3 2
SCLK
16
SCLK
HARDWARE CONTROL I/F
PDNB
14
PDNB
C1 10nF
R1 10k
STBYB
13
STBYB
Tuner Ground
IMPORTANT NOTES 1. E4000 metal paddle (bottom of package) should be connected to TUNER GROUND 2. Pins 4, 6, 7 should be connected to a common LNAGND plane, separate from the tuner ground plane 3. C6,7,8,9 Optional dependent on ability to match output common mode voltage to input common mode voltage of baseband demodulator input
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REFERENCE CIRCUIT
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REFERENCE CIRCUIT SELECTION OF KEY COMPONENTS

Function RF Tuner ESD Protection Diode Crystal Type Elonics E4000 ESD0P8RFL or BAV99 Baseband Clock (Optional) Value Quantity Size 1 QFN32 1 28.8MHz 1 HC-49SM DIP (Load Capacitance <20pF) Spec
Notes Schematic Reference
U1 Elonics E4000 Tuner (Please refer tuner spec Back to back diode. Low noise, < 2 pF < 2nH ESD Optional ESD protection D1 for RF input Optional, can use Fundalmental Load Capacitance <20pF; Shunt Capacitance<7pF; ESR<100Ohm; Freq Tolerance demodulator clock from crystal <50ppm; Aging/Year <5ppm; Operating Temp -20 o Y1 to -70 C X7R Ceramic 16V C4 X7R Ceramic 16V C6,C7,C8.C9
Input AC Coupling Output AC coupling Supply Decoupling Supply Decoupling Supply Decoupling
Capacitor Capacitor (Optional) Capacitor Capacitor Inductor
100pF 100nF 100nF 100pF 100nH
1 0603 4 0603 1 0603 5 0603 5 0603
Reference Decoupling Reference Bias I2C pull ups
Capacitor Reference Bias Resisitor
10nF 10k 10k
1 0603 1 0603 2 0603
X7R Ceramic 16V X7R Ceramic 16V 100nH inductor +/-10 %, dc resisatance < 1 Ohm, Low Q < 20, Multilayer e.g TDK MLK1005S82N, ferite bead MMZ1608D560 X7R Ceramic 16V Thick film 1% 0.0625W 100ppm Thick film 1% 0.0625W 100ppm
C2 C3,C5,C10,C11,C12
L1,L2,L3,L5,L6 C1 R1 R2,R3
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RF LAYOUT CONSIDERATIONS RF INPUT SIGNAL The layout of the RF input track structure is particularly important in ensuring that the tuner design will work as desired (RF connector to E4000 RFIN pin 5). At RF frequencies, the dimensions of PCB traces may be such that they approach or are greater than the electrical wavelength of the transmitted signal. Thus track lengths may be long enough that reflections due to mismatch may support varying magnitude and phase of voltages and currents along the length of the track. It is therefore desirable that the PCB designer aims to keep the RF input track as short as is possible. Also, in order that voltage reflections are small and that such a standing wave is not generated, the source impedance should match the transmission line impedance which should match the load impedance. In the case of a TV receiver this means that the antenna, transmission line and TV tuner IC should all be designed to have equal impedances, typically 50 or 75Ohms. In practical terms, the E4000 has been implemented so that impedance is around 65Ohms. This means that the magnitude of Reflection, (S11 or Return loss), is low in a 50Ohm or 75Ohm system. Either a 50Ohm or a 75Ohm impedance antenna can be used and the transmission line impedance should be designed to match the chosen value.
E4000 Return loss

0 100 -10
300
500
700
900 50R source impedance 75R source impedance
S11 (dB)
-20 -30 -40 -50 Frequency (MHz)
Note: A device with return loss, (S11), of lower than -10dB is generally considered to be well matched to the source impedance.
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RF INPUT CONNECTOR
The guideline is that the distance between the input connector and the RF input pin (pin5) should be kept as small as possible. This is to ensure track losses are kept to a minimum and reduce the possibility of signal reflections occurring.
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RF INPUT AC COUPLING CAPACITOR The E4000 input should be AC coupled, if connected to anything other than a passive antenna. For a DVB-T application covering 174 858MHz, the recommended capacitor is a 100pF 0402 size capacitor. The capacitor value is chosen such that it is large enough to permit low frequency signals to be passed. The self resonance of this capacitor should be greater than the highest operating frequency otherwise a resonance may be introduced somewhere in the wanted frequency band. Care should be taken to ensure the ESR (effective series resistance) of the capacitor remains low for the entire band of operation. The chart below shows a typical response for a 100pF 0402capacitor.
Self resonant frequency
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RF INPUT TRACK RF input tracks need to be referenced to LNAGND. LNAGND should be a plane below and adjacent to RF track. An example is shown below of a typical configuration.
Tuner GND
LNAGND (next to & below RF input track)
Ground stitching vias
The inductance of the LNAGND plane should be very low as RF ground return currents will flow in this domain. If possible, there should be ground stitching vias running alongside the RF track to tie planes on different layers together. The ground of the input connector should be connected to LNAGND.
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DESIGN OF AN IMPEDANCE CONTROLLED TRANSMISSION LINE
The most common design of an impedance controlled line uses a microstrip structure. The impedance of the transmission line is determined by the inductance of the transmission line and by the capacitance between the transmission line and the ground plane below. These in turn will be determined by the width of the transmission line, the thickness of the dielectric layer between the transmission line and the ground plane and the dielectric constant of the PCB material. Transmission line impedance can be calculated using free tools such as Agilent Appcad. However, as a general rule, for a 50Ohm transmission line, track width needs to be around 2 x dielectric thickness when using FR4 PCB material. It is critical that the RF input track has a ground reference. If a microstrip structure is used, this should be a solid plane below the RF input track.
Transmission line
H
PCB Dielectric Gnd plane
W Note: At the time of writing, Appcad could be downloaded from http://www.hp.woodshot.com/
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TRANSMISSION LINE STUBS
Any components in the transmission line should be placed so that these do not create stubs. A stub may introduce a point where a reflection can occur, potentially resulting in frequency loss due to interference between the original signal and any reflected, (time delayed), signal. GOOD LAYOUT
ESD diode
AC coupling capacitor Signal to RF Tuner Signal from antenna Good layout. ESD diode pad is part of the transmission line, minimising any stubs and reflections. All signal reaches RF tuner at the same time.
POOR LAYOUT
AC coupling capacitor Signal to RF Tuner
Signal path 1
Signal path 2 Signal from antenna
Poor layout. ESD diode pad is located away from the transmission line. A stub is introduced allowing some of the RF signal to flow down this branch of the transmission line. The signal may be reflected from the diode back to the tuner. Since this may reach the tuner at a different time from the signal transmitted straight through the AC coupling cap. Constructive or destructive interference of the time delayed signals may be cause ripple in the frequency response
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GROUND RETURN PATH The RF signal will flow from the antenna to the TV tuner along the microstrip transmission line. The return current will flow from the TV tuner back to the antenna through the ground connections. Care must be taken to ensure that the ground connections between the TV tuner LNA and the PCB ground connection minimise inductance as otherwise high frequency signals may be attenuated. The PCB designer should ensure that there is a solid ground plane from the TV tuner to the RF connector. The E4000 LNAGND pins should connect to this plane as close to the IC as is possible. The RF connector grounds should have vias to the ground plane as close to the connector as is possible.
GND vias should be placed close to the RF connector gnd pins
Solid GND plane beneath RF track
GND Vias should be placed close to E4000 IC
GROUND STITCHING VIAS Ideally, the E4000 LNAGND pins should also connect directly to the RF connector on the top side of the board also reducing ground return inductance. If this is done then the PCB designer should add ground stitching vias connecting the top ground plane to the ground plane below. These vias will tie the two ground planes to the same voltage level at the point where the via connects. Stitching vias should be placed close together so as to prevent high frequency voltage waves from being supported between via connections.
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SUPPLY AND GROUND CONSIDERATIONS 1.5V SUPPLY GENERATION
It is important to note that a DVB-T TV tuner is expected to have a sensitivity of around -97.5dBm (QPSK ). In a 50 Ohm impedance system, this equates to a voltage level of only 3uV (RMS peak) for the signal. It is essential that the tuner supply and ground noise must be very low to enable a signal of this small amplitude to be detected. In a typical application, the main system voltage will be 3.3V or higher. It is recommended that the tuner 1V5 supply is generated using a low noise LDO. The use of an LDO for the tuner will also isolate the tuner from noisy digital ICs providing some immunity to the noise generated by these. A DC-DC regulator is not recommended to supply the E4000 directly unless the user is confident that it will not generate supply noise. A DC-DC regulator typically generates large amounts of switching noise that can increase the system noise and degrade sensitivity performance. A designer may wish to use a DC-DC convertor further back in the system, for example to go from 5V to 3.3V. Careful attention should be paid to the design of this circuit to minimise the noise generated. While the subsequent LDO will provide some rejection of noise, if the level of noise is very high, some of this may still get through the LDO to the tuner.
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E4000 SUPPLY AND GROUND DOMAINS The E4000 has separate supply and ground domains on-chip. This isolates the very sensitive circuits from noisier digital circuits. Care should be taken when routing these domains on the PCB such that isolation between domains is maintained. The different domains are highlighted in the table below. IMPORTANT NOTES THE VERY SENSITIVE CIRCUITRY SHOULD OPERATE FROM THE LNAVDD AND LNAGND DOMAIN. NOISIER CIRCUITS OPERATE FROM THE TUN_DVDD, TUN_DGND0/1, PLL_VDD AND PLL_GND DOMAINS.
Pin 1 4 6 7 8 9 10 25 26 27 30 31 32
Name AGND RFSHIELD LNAGND LNAGND2 LNAVDD IFVDD IFGND TUN_DVDD TUN_DGND0 TUN_DGND1 PLL_GND PLL_VDD AVDD
Type TUNER_GND LNAGND LNAGND LNAGND LNAVDD 1V5 TUNERGND DVDD DGND DGND RFGND RFVDD 1V5
Description 0V 0V 0V 0V 1.5V 1.5V 0V 1.5V 0V 0V 0V 1.5V 1.5V
The recommended implementation of supply and ground filtering and decoupling such that isolation of domains is achieved are described below.
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LNAVDD DOMAIN Pin 4 6 7 8 Name RFSHIELD LNAGND LNAGND2 LNAVDD Type LNAGND LNAGND LNAGND LNAVDD Description 0V 0V 0V 1.5V
1.5V 8 LNAVDD 100nF 100pF 4 RFSHIELD 6 LNAGND Tuner GND 7 LNAGND2 100nH
The E4000 Low noise amplifier is powered from the LNA VDD and GND domain. It is critical that noise is not present on this domain. Any nose pickup will be amplified through the tuner degrading sensitivity performance. The inductor that is present in the LNAGND domain is intended to filter noise, presenting this from coupling onto this domain. There should NOT be an inductor placed in the LNAVDD line. The LNAs high frequency currents are sourced from this line. An inductor would limit the frequency response causing loss at high frequency. The LNAVDD and LNAGND domains are decoupled using a 100pF and 100nF pair. The two capacitors will decouple a wide range of frequencies of noise. Note: The RF input connector ground MUST connect to the LNAGND domain. Signal currents will flow from the RF connector to the E4000 IC. Ground return currents will flow from the E4000 back to the RF connector.
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DVDD DOMAIN Pin 25 26 27 Name TUN_DVDD TUN_DGND0 TUN_DGND1 Type DVDD DGND DGND Description 1.5V 0V 0V
100nH
1V5
100pF
TUN_DVDD
TUN_DGND1 Tuner GND TUN_DGND0

100nH
The E4000 digital circuit operates from the DVDD and DGND domain. The fast edge speeds of digital clocks may generate harmonics of the reference clock frequency. This may act as noise and should be isolated from the LNA domain. The inductors in DVDD and DGND domains are intended to filter noise going out of the chip and propagating to other domains.
PLL_VDD and PLL_GND DOMAIN Pin 30 31 Name PLL_GND PLL_VDD Type PLL GND PLL VDD
100nH 1.5V 31 PLL_VDD
Description 0V 1.5V
100pF Tuner GND 100nH
30 PLL_GND
The E4000 frequency synthesizer is powered from the PLLVDD and PLLGND domain. Again, inductors should be added in supply and ground lines to prevent any noise that is generated by these circuits from coupling to the LNA domain.
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IFVDD Pin 9 10 Name IFVDD IFGND Type 1V5 TUNERGND Description 1.5V 0V
1V5 100pF
9 IFVDD
Tuner GND
10 IFGND
AVDD Pin 1 32 Name AGND AVDD Type TUNER_GND 1V5

100nH 32 AVDD
Description 0V 1.5V
100pF Tuner GND 1 AGND GND Pad
The ground paddle of the E4000 tuner (metal pad under package) should be connected to AGND. Note 1: Decoupling caps should be placed on the top side of the PCB as close as is possible to the E4000 IC Note 2: For applications where there is a demodulator present, it is recommended that this ground is isolated from the tuner ground using an inductor. This prevents digital noise from the demodulator reaching the tuner and degrading performance. Note 3: For some applications such as a canned tuner, the RF connector ground is part of the connector ground. In this case it may not be possible to separate tuner and LNA grounds as the shield will connect these together. If this is the case ,it is recommended that the inductor between LNAGND and Tuner GND domains is removed and these planes also connected together on the PCB.
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RF LAYOUT CONSIDERATIONS RF INPUT SIGNAL The layout of the RF input track structure is particularly important in ensuring that the tuner design will work as desired (RF connector to E4000 RFIN pin 5). At RF frequencies, the dimensions of PCB traces may be such that they approach or are greater than the electrical wavelength of the transmitted signal. Thus track lengths may be long enough that reflections due to mismatch may support varying magnitude and phase of voltages and currents along the length of the track. It is therefore desirable that the PCB designer aims to keep the RF input track as short as is possible. Also, in order that voltage reflections are small and that such a standing wave is not generated, the source impedance should match the transmission line impedance which should match the load impedance. In the case of a TV receiver this means that the antenna, transmission line and TV tuner IC should all be designed to have equal impedances. In practical terms, the E4000 has been implemented so that impedance is around 65Ohms. This means that the magnitude of Reflection, (S11 or Return loss), is low in a 50Ohm or 75Ohm system. Either a 50Ohm or a 75Ohm impedance antenna can be used and the transmission line impedance should be designed to match the chosen value.
E4000 Return loss

0 100 -10
300
500
700
900 50R source impedance 75R source impedance
S11 (dB)
-20 -30 -40 -50 Frequency (MHz)
Note: A device with return loss, (S11), of lower than -10dB is generally considered to be well matched to the source impedance.
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RF INPUT CONNECTOR
The guideline is that the distance between the input connector and the RF input pin (pin5) should be kept as small as possible. This is to ensure track losses are kept to a minimum and reduce the possibility of signal reflections occurring.
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RF INPUT AC COUPLING CAPACITOR The E4000 input should be AC coupled, if connected to anything other than a passive antenna. For a DVB-T application covering 174 858MHz, the recommended capacitor is a 100pF 0402 size capacitor. The capacitor value is chosen such that it is large enough to permit low frequency signals to be passed. The self resonance of this capacitor should be greater than the highest operating frequency otherwise a resonance may be introduced somewhere in the wanted frequency band. Care should be taken to ensure the ESR (effective series resistance) of the capacitor remains low for the entire band of operation. The chart below shows a typical response for a 100pF 0402capacitor.
Self resonant frequency
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RF INPUT TRACK RF input tracks need to be referenced to LNAGND. LNAGND should be a plane below and adjacent to RF track. An example is shown below of a typical configuration.
Tuner GND
LNAGND (next to & below RF input track)
Ground stitching vias
The inductance of the LNAGND plane should be very low as RF ground return currents will flow in this domain. If possible, there should be ground stitching vias running alongside the RF track to tie planes on different layers together. The ground of the input connector should be connected to LNAGND.
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DESIGN OF AN IMPEDANCE CONTROLLED TRANSMISSION LINE
The most common design of an impedance controlled line uses a microstrip structure. The impedance of the transmission line is determined by the inductance of the transmission line and by the capacitance between the transmission line and the ground plane below. These in turn will be determined by the width of the transmission line, the thickness of the dielectric layer between the transmission line and the ground plane and the dielectric constant of the PCB material. Transmission line impedance can be calculated using free tools such as Agilent Appcad. However, as a general rule, for a 50Ohm transmission line, track width needs to be around 2 x dielectric thickness when using FR4 PCB material. It is critical that the RF input track has a ground reference. If a microstrip structure is used, this should be a solid plane below the RF input track.
Transmission line
H
PCB Dielectric Gnd plane
W Note: At the time of writing, Appcad could be downloaded from http://www.hp.woodshot.com/
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TRANSMISSION LINE STUBS
Any components in the transmission line should be placed so that these do not create stubs. A stub may introduce a point where a reflection can occur, potentially resulting in frequency loss due to interference between the original signal and any reflected, (time delayed), signal. GOOD LAYOUT
ESD diode
AC coupling capacitor Signal to RF Tuner Signal from antenna Good layout. ESD diode pad is part of the transmission line, minimising any stubs and reflections. All signal reaches RF tuner at the same time.
POOR LAYOUT
AC coupling capacitor Signal to RF Tuner
Signal path 1
Signal path 2 Signal from antenna
Poor layout. ESD diode pad is located away from the transmission line. A stub is introduced allowing some of the RF signal to flow down this branch of the transmission line. The signal may be reflected from the diode back to the tuner. Since this may reach the tuner at a different time from the signal transmitted straight through the AC coupling cap. Constructive or destructive interference of the time delayed signals may be cause ripple in the frequency response
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GROUND RETURN PATH The RF signal will flow from the antenna to the TV tuner along the microstrip transmission line. The return current will flow from the TV tuner back to the antenna through the ground connections. Care must be taken to ensure that the ground connections between the TV tuner LNA and the PCB ground connection minimise inductance as otherwise high frequency signals may be attenuated. The PCB designer should ensure that there is a solid ground plane from the TV tuner to the RF connector. The E4000 LNAGND pins should connect to this plane as close to the IC as is possible. The RF connector grounds should have vias to the ground plane as close to the connector as is possible.
GND vias should be placed close to the RF connector gnd pins
Solid GND plane beneath RF track
GND Vias should be placed close to E4000 IC
GROUND STITCHING VIAS Ideally, the E4000 LNAGND pins should also connect directly to the RF connector on the top side of the board also reducing ground return inductance. If this is done then the PCB designer should add ground stitching vias connecting the top ground plane to the ground plane below. These vias will tie the two ground planes to the same voltage level at the point where the via connects. Stitching vias should be placed close together so as to prevent high frequency voltage waves from being supported between via connections.
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PCB STACKUP (4 LAYER BOARD)
The diagram above illustrates the four layers of the PCB board. Each layer has been partitioned into a specific requirement. Layer 1, the top layer is used for placement of the E4000 tuner and if applicable, the demodulator. This layer may also be used for routing of the high speed signal tracks. It is recommended that this layer is not flooded with ground around the tuner so that noise does not unintentionally couple from signal lines to ground planes or vice versa. The exception to this is that the LNAGND between the RF connector and the E4000 Gnd pins should be connected on the top side so as to minimise ground return path inductance. Layer 2 should be a ground plane this provides the ground reference for any impedance controlled tracks. Layer 3 may be used as a power plane. Layer 4 may be used for components and routing of low speed signals. Note: Where a 2 layer construction is used, layer 3 and 4 may be omitted, with power being routed on layer 1 or 2. Care must be taken to make sure that high frequency signal ground return paths run continuously over a ground plane and do not cross over tracking.
Where there are multiple layers of ground plane, these should be stitched together using vias. This will minimise inductance between ground planes and will tie different planes to the same potential level. Vias should be placed close together so as to prevent standing waves being set up within the ground plane area between two vias, (high frequency ground bounce).
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PACKAGE DRAWING
QFN: 32 PIN QFN PLASTIC PACKAGE 5 x 5 x 0.9 BODY, 0.50 mm LEAD PITCH Top View D A e B 3 pin 1 Bottom View Detail A
E1
E2
EXPOSED PAD
2x 2x
aaa C D2 aaa C D1 Detail A 6 Nx b Detail B ccc C Edge View bbb M C A B 0.165 typ
A3
Nx 0.08 C
C 4
Nx k
Detail B
0.4 7 L1
Symbol A A1 A3 D D1 D2 E E1 E2 L L1 b N e k R T
Common Dimensions Minimum Nominal Maximum 0.85 0.90 1.0 0 0.02 0.05 0.20 ref 4.90 5.0 5.1 3.5 3.2 3.3 3.4 4.90 5.0 5.1 3.5 3.20 3.30 3.40 0.35 0.40 0.45 0.1 0.18 0.23 0.30 32 0.50 0.20 b min/2 0.15
A1
Notes 1. JEDEC ref MO-220 2. All dimensions are in millimeters 3. Pin 1 orientation identified by chamfer on corner of exposed die pad 4. Datum C and the seating plane are defined by the flat surface of the metallised terminal 5. Dimension e represents the terminal pitch 6. Dimension b applies to metallised terminal and is measured 0.25 to 0.30mm from terminal tip 7. Dimension L1 represents terminal pull back from package edge. Where terminal pull back exists, only upper half of lead is vis ble on package edge due to half etching of leadframe 8. Package surface shall be matt finish, Ra 1.6 2.2 9. Leadframe material is copper A194 10. Coplanarity applies to the exposed pad as well as the terminals
Symbol aaa bbb ccc
Tolerances for Form & Position 0.15 0.10 0.10
Notes
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0.27 typ
0.4
LOOPBACK CIRCUIT
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EXAMPLE LAYOUT (4 LAYERS) Component Placement
IF Output AC Coupling Capacitors Short RF input track to E4000
E4000 (metal bottom paddle) connected to AGND Tuner Crystal (Clock Source)
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EXAMPLE LAYOUT (4 LAYERS) Layer 1 Signals and Key Connections
RF Input AC Coupling Capacitor IF Outputs, AC Coupled
Short RF input track to E4000
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EXAMPLE LAYOUT (4 LAYERS) Layer 2, LNAGND and Tuner GND Layer
LNAGND plane under RF input track. Ground stitching vias to other ground planes
Bottom pad of the E4000 connected to Tuner GND plane
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EXAMPLE LAYOUT (4 LAYERS) Layer 3, 1.5V Supply
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EXAMPLE LAYOUT (4 LAYERS) Layer 3, Tuner GND Layer
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LEGAL NOTICES Product information is current as of publication date. Elonics Ltd (Elonics) products and services are sold subject to Elonics terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Elonics warrants performance of its products to the specifications in effect at the date of shipment. Elonics reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Elonics to verify that the information is current. Testing and other quality control techniques are utilised to the extent Elonics deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Elonics is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Elonics products. Elonics is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in an Elonics product. Elonics products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customers own risk. Elonics does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Elonics covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third partys products or services does not constitute Elonics approval, licence, warranty or endorsement thereof. Any third party trademarks contained in this document belong to the respective third party owner. Reproduction of information from Elonics datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Elonics is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differs from those contained in this datasheet or in Elonics standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that persons own risk. Elonics is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
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REVISION HISTORY Revision 1v0 1v2 1v3 1v4 Date January 2010 March 2010 April 2010 June 2010 Description of changes Initial Release Major revision of all sections Minor revision to all sections Updated pin names
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Elonics E4000 - Low Power CMOS Multi-Band Tunner - Hardware Design Guide

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Elonics E4000 - Low Power CMOS Multi-Band Tunner - Hardware Design Guide

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Hardware Design Guide

Elonics E4000 Hardware Design Guide Rev 1v4

Copyright 2010 Elonics Ltd 1

Elonics E4000 Hardware Design Guide Rev 1v4

Copyright 2010 Elonics Ltd 2

Elonics E4000 Hardware Design Guide Rev 1v4

Copyright 2010 Elonics Ltd 3

SET TOP BOX DESIGN (FURTHER CONSIDERATIONS

Elonics E4000 Hardware Design Guide Rev 1v4

Copyright 2010 Elonics Ltd 5

E4000 PIN INFORMATION

AGND VBG REXT RFSHIELD RFIN LNAGND LNAGND2 LNAVDD

CKOUTP CKOUTN GAIN1

GAIN0 IVOUTP IVOUTN QVOUTP QVOUTN

Elonics E4000 Hardware Design Guide Rev 1v4

Copyright 2010 Elonics Ltd 6

Elonics E4000 Hardware Design Guide Rev 1v4

Copyright 2010 Elonics Ltd 7

FIT OPTION CLOCKIN 28 CLOCKIN

LNAGND IFGND PLL_GND 29 XTAL

IVOUTP CONNECT TO LNAGND C4 RFIN_1 100pF QVOUTP GAIN0 21 GA N0 5

C9 IVOUTP 100nF C8 IVOUTN 100nF IF OUTPUTS

RFIN_1 18 C7 QVOUTP 100nF C6 QVOUTN 100nF

AGC CONTROL INPUTS

I2C ADDRESS SELECT

MICRO CONTROL I/F

SDAT REXT VBG

HARDWARE CONTROL I/F

Elonics E4000 Hardware Design Guide Rev 1v4

Copyright 2010 Elonics Ltd 8

Elonics E4000 Hardware Design Guide Rev 1v4

Copyright 2010 Elonics Ltd 9

REFERENCE CIRCUIT SELECTION OF KEY COMPONENTS

Capacitor Capacitor (Optional) Capacitor Capacitor Inductor

100pF 100nF 100nF 100pF 100nH

1 0603 4 0603 1 0603 5 0603 5 0603

Reference Decoupling Reference Bias I2C pull ups

Capacitor Reference Bias Resisitor

10nF 10k 10k

1 0603 1 0603 2 0603

Elonics E4000 Hardware Design Guide Rev 1v4

Copyright 2010 Elonics Ltd 10

E4000 Return loss

900 50R source impedance 75R source impedance

-20 -30 -40 -50 Frequency (MHz)

Elonics E4000 Hardware Design Guide Rev 1v4

Copyright 2010 Elonics Ltd 11

Elonics E4000 Hardware Design Guide Rev 1v4

Copyright 2010 Elonics Ltd 12

Self resonant frequency

Elonics E4000 Hardware Design Guide Rev 1v4

Copyright 2010 Elonics Ltd 13

LNAGND (next to & below RF input track)

Ground stitching vias

Elonics E4000 Hardware Design Guide Rev 1v4

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DESIGN OF AN IMPEDANCE CONTROLLED TRANSMISSION LINE

W Note: At the time of writing, Appcad could be downloaded from http://www.hp.woodshot.com/

Elonics E4000 Hardware Design Guide Rev 1v4

Copyright 2010 Elonics Ltd 15

TRANSMISSION LINE STUBS

AC coupling capacitor Signal to RF Tuner

Signal path 2 Signal from antenna