EL - 213 Lab Report

Group Members :
Abhimanyu Garg Dhruv Raval Jaysheel Goda -201001095 - 201001091 - 201001094

Aim: To design a BJT Double stage Amplifier based on following conditions: 1. Design a CE Amplifier whose gain is 300. 2. Design a CE Amplifier, without Emitter Capacitor, whose gain is 10. 3. Connect both stages obtained in (1) and (2), with + without emitter capacitor. Check out overall voltage gain and Bandwidth 4. Connect both stages obtained in (1) and (2), without + with emitter capacitor. Check out overall voltage gain and Bandwidth 5. Do small signal analysis of (3) & (4). 6. Implement (3) & (4) in Hardware. Given Data: 1. 2. 3. 4. 5. 6. 7. Calculations:

with emitter capacitor without emitter capacitor

Pspice and Hardware Observations: 1. With Emitter Capacitor a. Circuit Diagram

[Circuit Diagram of One Stage CE Amplifier] b. Gain Obtained from PSpice Gain: 47.87 dB

c. Hardware observations Frequency (* ) (in Hertz) 100 500 1k 2k 5k 10k 20k 30k 100k 200k 500k 1M 40 40 40 40 40 40 40 40 40 40 40 40

(in Volts) 3.9 6.4 6.5 6.5 6.5 6.6 6.6 6.6 6.0 4.4 2.6 1.6 97.5 160 162.5 162.5 162.5 165 165 165 150 110 65 40

(in decibels) 39.78 44.08 44.21 44.21 44.21 44.35 44.35 44.35 43.52 40.82 36.26 32.04

d. Comparison Gain in Pspice : 47.87 Gain in Hardware: 44.35 2. Without Emitter capacitor a. Circuit Diagram

[Circuit Diagram of One stage CE Amplifier with emitter capacitor]

b. Gain Obtained from Pspice Gain: 19.58 dB

[Gain obtained from 1 stage common emitter amplifier with bypass capacitor] c. Hardware Observations Frequency (* ) 100 500 1k 2k 5k 10k 20k 50k 100k 200k 500k 1M 40 40 40 40 40 40 40 40 40 40 40 40

(in Volts) 0.4 0.43 0.43 0.42 0.42 0.42 0.4 0.38 0.32 0.24 0.12 0.06 10 10.75 10.75 10.50 10.50 10.50 10 9.5 8 6 3 1.5 (in decibels) 20 20.62 20.62 20.42 20.42 20.42 20 19.55 18.06 15.56 9.54 3.52

d. Comparison Gain in Pspice: 19.58 dB Gain in Hardware: 20.62 dB

3. 2 stage CE Amplifier : with a. Circuit Diagram

+ without

[Circuit of double stage amplifier. With and without bypass capacitor.] b. Gain and Bandwidth of double stage Amplifier Gain : 63.02 dB (1445.49 V/V) Bandwidth: 383.6KHz

c. Small Signal Analysis

[Equivalent diagram of above circuit diagram]

d. Hardware observations Frequency (* 1 3 100 3 500 3 1k 3 2k 3 10k 3 20k 3 50k 3 100k 3 200k 3 250k 3 300k 3 500k 3

) 1 2.5 3 5 5 5 5 5.1 4.2 3.5 2.8 2.5 1.5 333.3 833.3 1000 1666.6 1666.6 1666.6 1666.6 1700 1400 1166.6 933.3 833.3 500 50.46 58.42 60 64.44 64.44 64.44 64.44 64.61 62.92 61.34 59.40 58.42 53.98

e. Comparison Gain in PSpice: 63.02dB Gain in Hardware: 64.62dB Gain theoretically: 65.27dB 4. 2 stage CE Amplifier : without a. Circuit Diagram + with

[Circuit of double stage amplifier. Without and with bypass capacitor.] b. Gain and Bandwidth of 2 stage amplifier Gain: 56.01dB (631.68 V/V) Bandwidth: 40.69kHz

c. Small Signal Analysis

[Equivalent diagram of above circuit diagram]

d. Hardware Observations Frequency (* 100 3 500 3 1k 3 2k 3 10k 3 20k 3 23k 3 30k 3 50k 3 100k 3 500k 3

) 1 1.9 2 2 2 2 1.9 1.8 1.4 1.0 0.4 333.3 633.3 666.6 666.6 666.6 666.6 633.3 600 466.6 333.3 133.3 50.45 56.03 56.47 56.47 56.47 56.47 56.03 55.56 53.38 50.45 42.49

e. Comparison Gain in PSpice: 56.01dB Gain in Hardware: 56.47dB Gain theoretically: 56.24dB Conclusion: An amplifier is the building block of most electronic systems. A single stage amplifier cannot supply enough signal output. A single stage that operates with a low level signal does not have enough output power. Hence, two stages are cascaded to provide a greater signal. This is achieved by coupling two amplifier stages such that the output of first stage drives the input of the second through coupling device. This type of connection is called two-stage and the amplifier is called two stage amplifier. Since the amplifiers are cascaded the overall gain of the amplifier will be given by, Av=Av1 * Av2 If the gains are represented in dB the overall gain is the sum of the individual gains: Av=Av1 + Av2 The resistance R1, R2 & RE form a biasing and stabilisation network. The emitter bypass capacitor CE offers low reactance path to the signal. Without this capacitor, the gain of each stage would be very low due to negative feedback at various stages. The purpose of coupling device is to transfer ac output of first stage to the input of the next stage to isolate the dc conditions of one stage from the next. When ac signal is applied to the base of first transistor, it appears in the amplified form across the collector load RC. The amplified signal across is given to the base of the next stage through a coupling capacitor CC. The second stage further amplifies the signal and the overall gain considerably increases. The overall gain is less than the product of the individual gains. This is because when a second stage is made to follow the first stage, the effective load resistance of the first stage is reduced due to the shunting effect of the input resistance of second stage. This reduces the gain of the stage which is loaded by the next stage. Here, in our experiment, we have more gain in with CE configurations due to the reason explained above. For two-stage amplifiers, the overall gain of with + w/o configuration is more than w/o + with configuration because in with+w/o the input of 2nd stage is more than input of 2nd stage of w/o + with as Ce provides low reactance path. Moreover, gain of w/o in 2nd stage is more than w/o in 1st stage, thus amplifying the signal even more.