National University of Sciences & Technology (NUST) School of Electrical Engineering and Computer Science (SEECS) Department of Electrical

Engineering

Embedded System Design

Course Code: EE-430 Credit Hours: 3+1 Instructor: Dr. Osman Hasan Office: Room # ALecture Days: Class Room: Knowledge Group: Digital Systems & Signal Processing Semester: Prerequisite Codes: Discipline: Telephone: E-mail: Consulting Hours: Updates on LMS: Fall 2012 EE 241 Digital Logic Design

osman.hasan@seecs.edu.pk By Appointment Every Friday

Course Description:
In today's world, embedded systems are everywhere -- homes, offices, cars, factories, hospitals, planes and consumer electronics. Their huge numbers and new complexity call for a new design approach, one that emphasizes high-level tools and hardware/software tradeoffs, rather than low-level assembly-language programming and logic design. This course presents the traditionally distinct fields of software and hardware design in a new unified approach. It covers trends and challenges, introduces the design and use of singlepurpose processors ("hardware") and general-purpose processors ("software"), describes memories and buses, and illustrates hardware/software tradeoffs, chip technologies, and modern design tools.

Course Outcomes/Objectives:
Introduction to the basic concepts of the Embedded System Design from both the hardware and software viewpoints. General Purpose, Application Specific and Single Purpose processors will be introduced and Embedded System design based on these three technologies will be the prime focus of this course. Students are expected to learn the primary approaches and technologies used in the domain of Embedded System design and apply them to build Embedded Systems to solve real-world problems.

Books:
Text Book: Reference Books: Embedded System Design: A unified Hardware/Software Introduction, Frank Vahid and Tony Givargis, 2002. Computer as Components, Wayne Wolf, 2005 Embedded Systems Design, Steve Heath, 2003

Weightages:
Quizzes: Assignments: OHTs: Final Exam: Lab + Final Lab Exam/Project: 12% 8% 22% 33% 25%

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National University of Sciences & Technology (NUST) School of Electrical Engineering and Computer Science (SEECS) Department of Electrical Engineering
Tools / Software Requirement:
Sofware Tools: Xilinx v12.2, Modelsim, Proteus, Keil, MPLab. Hardware Tools: Virtex-5(ml507) evaluation platform, 89C51 micro-controller is required for practical work. The system administration has installed all the software in the lab.

Main Topics to be Covered:

The course spans over a number of different topics as under: Introduction to Embedded Systems Design Challenges Processor Technology IC Technology Design Technology Custom Single Purpose Processors Custom Single Purpose Processor Design RTL Level Optimizing Single Purpose Processor General-Purpose Processors Basic Architecture and Operations Programmers view Development Environment Application-Specific Instruction-Set processors (ASIPs) Selecting a Microprocessor, General Purpose Processor Design Standard Single-Purpose Processors Timers, Counters, UART PWM, LCD & Keypad Controllers Stepper Motor Controllers, A/D Converters Memory Memory Types, Composing Memory Memory Hierarchy and Cache Interfacing I/O Addressing, Interrupts Direct Memory Access (DMA) Arbitration, Multiple Bus Architectures Advanced Communication Principles Serial/Parallel/Wireless Protocols State machine and concurrent process models Hierarchial/Concurrent state machine model (HCFSM) Program-state machine model (PSM) Concurrent processes Dataflow model Real-time systems Multiple Tasks and Multiple Processes Context Switching Operating Systems Scheduling Policies Inter-process Communication Mechanisms Page 2 of 4

National University of Sciences & Technology (NUST) School of Electrical Engineering and Computer Science (SEECS) Department of Electrical Engineering Lecture Breakdown
Week No. 1 Lecture No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Topic Introduction to Embedded Systems Introduction to Embedded Systems Introduction to Embedded Systems Custom Single-Purpose Processors Custom Single-Purpose Processors Custom Single-Purpose Processors Custom Single-Purpose Processors General-Purpose Processors General-Purpose Processors General-Purpose Processors General-Purpose Processors General-Purpose Processors General-Purpose Processors Standard Single-Purpose Processors Standard Single-Purpose Processors Standard Single-Purpose Processors Standard Single-Purpose Processors Standard Single-Purpose Processors Memory Memory Memory Memory Memory Interfacing Interfacing Interfacing Interfacing Interfacing Interfacing Interfacing Interfacing Interfacing Interfacing State machine and concurrent process models State machine and concurrent process models State machine and concurrent process models State machine and concurrent process models State machine and concurrent Description Course Introduction, Motivation Design Challenges, Processor Technology IC Technology, Design Technology Combinational Logic Design, Sequential Logic Design Custom Single-Purpose Processor Design RT-Level Optimizing Custom Single-Purpose Processor Design Basic Architecture Operations Programmers view Development Environment Application-Specific Instruction-Set processors (ASIPs) Selecting a Microprocessor, General Purpose Processor Design Timers and Counters UART, Pulse Width Modulators, LCD controllers, Keypad controllers, Stepper Motor Controllers A/D converters, Real-Time Clocks Write Ability and Storage Permenance Memory Types Memory Types, Composing Memory, Memory Hierarchy and Cache Memory Hierarchy and Cache Communication Basics I/O Addressing I/O Addressing Interrupts Direct Memory Access Arbitration, Multiple Bus Architectures Advanced Communication Principles Serial Protocols Parallel Protocols Wireless Protocols Hierarchical/Concurrent state machine model (HCFSM) Program-state machine model (PSM) Concurrent processes Dataflow model Real-time systems Page 3 of 4

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National University of Sciences & Technology (NUST) School of Electrical Engineering and Computer Science (SEECS) Department of Electrical Engineering
process models State machine and concurrent process models State machine and concurrent process models Operating Systems Operating Systems Operating Systems Operating Systems Operating Systems Concluding Discussions Concluding Discussions Concluding Discussions

39 14 40 41 42 43 44 45 46 47 48

Multiple Tasks and Multiple Processes Context Switching Introduction Introduction Scheduling Policies Inter-process Communication Mechanisms Inter-process Communication Mechanisms Case Studies Recent Trends Recent Trends

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Grading Policy:
Quiz Policy: The quizzes will be unannounced and normally last for ten minutes. The question framed is to test the
concepts involved in last few lectures. Number of quizzes that will be used for evaluation is at the instructors discretion. Grading for quizzes will be on a fixed scale of 0 to 10. A score of 10 indicates an exceptional attempt towards the answer and a score of 1 indicates your answer is entirely wrong but you made a reasonable effort towards the solution. Scores in between indicate very good (8-9), good (6-7), satisfactory (4-5), and poor (2-3) attempt. Failure to make a reasonable effort to answer a question scores a 0. In order to develop comprehensive understanding of the subject, assignments will be given. Late assignments will also be accepted / graded. All assignments will count towards the total (No best-of policy). The students are advised to do the assignment themselves. Copying of assignments is highly discouraged and violations will be dealt with severely by referring any occurrences to the disciplinary committee. The questions in the assignment are meant to be challenging to give students confidence and extensive knowledge about the subject matter and enable them to prepare for the exams. The labs will be conducted for three hours every week. A lab handout will be given in advance for study and analysis The lab handouts will also be placed on LMS. The students are to submit their results by giving a lab report at the end of lab for evaluation. One lab report per group will be required. However, students will also be evaluated by oral viva during the lab. SEECS maintains a zero tolerance policy towards plagiarism. While collaboration in this course is highly encouraged, you must ensure that you do not claim other peoples work/ ideas as your own. Plagiarism occurs when the words, ideas, assertions, theories, figures, images, programming codes of others are presented as your own work. You must cite and acknowledge all sources of information in your assignments. Failing to comply with the SEECS plagiarism policy will lead to strict penalties including zero marks in assignments and referral to the academic coordination office for disciplinary action.

Assignment Policy:

Lab Conduct:

Plagiarism:

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